Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	96921455	13996	0	0
claim_transition_if_regwen_rd_A	96921455	1406	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96921455	13996	0	0
T56	734439	3	0	0
T79	1141	0	0	0
T106	266897	0	0	0
T111	0	16	0	0
T130	0	2	0	0
T131	0	4	0	0
T176	0	4	0	0
T177	0	2	0	0
T178	0	3	0	0
T179	0	1	0	0
T180	0	14	0	0
T181	0	4	0	0
T182	14823	0	0	0
T183	1644	0	0	0
T184	1467	0	0	0
T185	211649	0	0	0
T186	27042	0	0	0
T187	1930	0	0	0
T188	6882	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96921455	1406	0	0
T38	30838	0	0	0
T111	190553	0	0	0
T112	58418	0	0	0
T113	2214	0	0	0
T114	494169	0	0	0
T115	4366	0	0	0
T116	27032	0	0	0
T131	256434	3	0	0
T142	0	47	0	0
T150	0	10	0	0
T151	0	9	0	0
T172	0	9	0	0
T173	0	75	0	0
T176	0	6	0	0
T179	0	8	0	0
T189	0	11	0	0
T190	0	14	0	0
T191	5284	0	0	0
T192	28848	0	0	0