Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1358499	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1581908

1

T1

1365

T3

23

T9

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2592726	1			T1	2329		T3	23		T9	20
values[0x0]	173346	1			T1	131		T3	11		T9	3
values[0x1]	174335	1			T1	159		T3	10		T9	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1077470	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1862937

1

T1

1616

T3

24

T9

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8263	1			T1	11		T4	2		T23	8
valid_sources[0x01]	8076	1			T1	9		T12	6		T25	8
valid_sources[0x02]	8019	1			T1	10		T4	1		T12	2
valid_sources[0x03]	8142	1			T1	12		T4	2		T12	6
valid_sources[0x04]	9435	1			T1	9		T3	1		T4	1
valid_sources[0x05]	8359	1			T1	12		T3	1		T4	1
valid_sources[0x06]	17099	1			T1	8		T4	2		T12	4
valid_sources[0x07]	8292	1			T1	8		T3	2		T4	1
valid_sources[0x08]	8534	1			T1	6		T12	3		T13	14
valid_sources[0x09]	50467	1			T1	11		T4	1		T12	6
valid_sources[0x0a]	9145	1			T1	8		T3	2		T4	3
valid_sources[0x0b]	18992	1			T1	11		T4	6		T12	8
valid_sources[0x0c]	22806	1			T1	7		T4	2		T12	1
valid_sources[0x0d]	8707	1			T1	10		T4	1		T12	3
valid_sources[0x0e]	8410	1			T1	6		T3	1		T4	4
valid_sources[0x0f]	9022	1			T1	5		T10	933		T12	13
valid_sources[0x10]	7759	1			T1	13		T4	4		T12	4
valid_sources[0x11]	8120	1			T1	10		T3	1		T4	5
valid_sources[0x12]	8516	1			T1	6		T4	3		T25	4
valid_sources[0x13]	27830	1			T1	3		T4	1		T12	4
valid_sources[0x14]	19750	1			T1	5		T12	6		T25	7
valid_sources[0x15]	8481	1			T1	11		T12	4		T25	2
valid_sources[0x16]	8398	1			T1	4		T9	28		T4	3
valid_sources[0x17]	9821	1			T1	16		T4	4		T12	4
valid_sources[0x18]	8256	1			T1	11		T4	1		T23	4
valid_sources[0x19]	8180	1			T1	15		T4	1		T12	3
valid_sources[0x1a]	41962	1			T1	14		T3	1		T4	1
valid_sources[0x1b]	8971	1			T1	7		T3	1		T4	2
valid_sources[0x1c]	67505	1			T1	12		T4	2		T12	10
valid_sources[0x1d]	10159	1			T1	19		T4	2		T25	2
valid_sources[0x1e]	9746	1			T1	12		T12	1		T25	4
valid_sources[0x1f]	8102	1			T1	11		T4	2		T12	4
valid_sources[0x20]	7851	1			T1	6		T4	1		T12	18
valid_sources[0x21]	8182	1			T1	6		T4	1		T12	1
valid_sources[0x22]	8317	1			T1	12		T4	2		T12	7
valid_sources[0x23]	8111	1			T1	11		T4	4		T12	17
valid_sources[0x24]	8663	1			T1	7		T4	1		T12	9
valid_sources[0x25]	9728	1			T1	20		T4	4		T12	2
valid_sources[0x26]	8191	1			T1	23		T4	1		T25	10
valid_sources[0x27]	9242	1			T1	6		T4	3		T12	1
valid_sources[0x28]	10967	1			T1	14		T4	1		T12	1
valid_sources[0x29]	8302	1			T1	8		T4	1		T12	8
valid_sources[0x2a]	11202	1			T1	19		T4	5		T12	7
valid_sources[0x2b]	7801	1			T1	14		T4	4		T12	10
valid_sources[0x2c]	13677	1			T1	13		T3	1		T4	2
valid_sources[0x2d]	8549	1			T1	9		T12	10		T13	6
valid_sources[0x2e]	11478	1			T1	6		T4	2		T12	12
valid_sources[0x2f]	8359	1			T1	7		T12	3		T13	5
valid_sources[0x30]	9198	1			T1	13		T4	1		T12	1
valid_sources[0x31]	7996	1			T1	12		T4	2		T12	4
valid_sources[0x32]	11864	1			T1	9		T4	1		T12	6
valid_sources[0x33]	8258	1			T1	7		T4	3		T12	2
valid_sources[0x34]	12506	1			T1	14		T4	4		T12	2
valid_sources[0x35]	7935	1			T1	7		T4	1		T12	11
valid_sources[0x36]	9110	1			T1	16		T4	2		T12	5
valid_sources[0x37]	8343	1			T1	11		T4	1		T12	3
valid_sources[0x38]	8953	1			T1	7		T3	1		T4	5
valid_sources[0x39]	9855	1			T1	10		T4	1		T12	4
valid_sources[0x3a]	11754	1			T1	9		T4	2		T25	4
valid_sources[0x3b]	9353	1			T1	13		T12	5		T25	8
valid_sources[0x3c]	8427	1			T1	5		T3	1		T4	1
valid_sources[0x3d]	8103	1			T1	11		T4	2		T12	12
valid_sources[0x3e]	9877	1			T1	9		T12	5		T25	7
valid_sources[0x3f]	7914	1			T1	7		T4	1		T12	3
valid_sources[0x40]	8142	1			T1	8		T4	1		T12	4
valid_sources[0x41]	8441	1			T1	8		T3	1		T4	3
valid_sources[0x42]	8637	1			T1	6		T4	1		T12	1
valid_sources[0x43]	10498	1			T1	25		T4	2		T12	1
valid_sources[0x44]	8422	1			T1	12		T4	1		T12	13
valid_sources[0x45]	10829	1			T1	10		T4	1		T12	7
valid_sources[0x46]	8097	1			T1	9		T12	1		T25	4
valid_sources[0x47]	8702	1			T1	12		T4	3		T12	2
valid_sources[0x48]	8963	1			T1	7		T4	1		T12	6
valid_sources[0x49]	7839	1			T1	11		T4	2		T12	2
valid_sources[0x4a]	10183	1			T1	12		T4	2		T12	2
valid_sources[0x4b]	8424	1			T1	13		T4	2		T12	9
valid_sources[0x4c]	8709	1			T1	11		T4	1		T12	4
valid_sources[0x4d]	8214	1			T1	10		T4	1		T12	6
valid_sources[0x4e]	8246	1			T1	3		T12	2		T25	3
valid_sources[0x4f]	7917	1			T1	5		T12	15		T25	3
valid_sources[0x50]	8628	1			T1	13		T12	2		T82	1
valid_sources[0x51]	8035	1			T1	9		T4	1		T12	3
valid_sources[0x52]	10139	1			T1	9		T4	2		T12	2
valid_sources[0x53]	8072	1			T1	13		T12	4		T25	3
valid_sources[0x54]	9619	1			T1	11		T12	4		T25	6
valid_sources[0x55]	24328	1			T1	10		T4	5		T12	8
valid_sources[0x56]	9592	1			T1	11		T4	1		T12	2
valid_sources[0x57]	20433	1			T1	11		T4	1		T25	2
valid_sources[0x58]	7918	1			T1	12		T4	2		T12	9
valid_sources[0x59]	9743	1			T1	16		T12	1		T25	1
valid_sources[0x5a]	8270	1			T1	8		T4	5		T12	3
valid_sources[0x5b]	25713	1			T1	14		T3	1		T4	1
valid_sources[0x5c]	11502	1			T1	8		T4	1		T12	5
valid_sources[0x5d]	8146	1			T1	9		T4	3		T12	11
valid_sources[0x5e]	8321	1			T1	10		T3	1		T25	5
valid_sources[0x5f]	8227	1			T1	11		T4	5		T12	5
valid_sources[0x60]	8630	1			T1	11		T4	1		T12	1
valid_sources[0x61]	8835	1			T1	19		T4	2		T12	5
valid_sources[0x62]	15601	1			T1	8		T4	2		T12	4
valid_sources[0x63]	7803	1			T1	7		T4	2		T12	2
valid_sources[0x64]	9409	1			T1	13		T4	1		T13	3
valid_sources[0x65]	8757	1			T1	15		T4	1		T12	5
valid_sources[0x66]	7978	1			T1	11		T4	5		T12	8
valid_sources[0x67]	44253	1			T1	8		T4	1		T12	2
valid_sources[0x68]	8159	1			T1	11		T12	5		T13	3
valid_sources[0x69]	8336	1			T1	8		T4	1		T12	6
valid_sources[0x6a]	8267	1			T1	2		T4	2		T12	1
valid_sources[0x6b]	8675	1			T1	21		T4	3		T12	8
valid_sources[0x6c]	69142	1			T1	16		T4	4		T25	5
valid_sources[0x6d]	8041	1			T1	8		T4	2		T12	3
valid_sources[0x6e]	8376	1			T1	8		T12	4		T25	6
valid_sources[0x6f]	10464	1			T1	12		T12	9		T25	5
valid_sources[0x70]	8177	1			T1	9		T4	3		T12	5
valid_sources[0x71]	8115	1			T1	7		T12	8		T25	6
valid_sources[0x72]	8499	1			T1	13		T4	2		T12	12
valid_sources[0x73]	8228	1			T1	4		T4	1		T12	14
valid_sources[0x74]	10658	1			T1	11		T4	5		T12	5
valid_sources[0x75]	8311	1			T1	13		T4	2		T12	15
valid_sources[0x76]	9564	1			T1	5		T4	3		T12	8
valid_sources[0x77]	9688	1			T1	17		T12	4		T13	10
valid_sources[0x78]	8313	1			T1	9		T4	5		T12	18
valid_sources[0x79]	11567	1			T1	6		T3	2		T4	2
valid_sources[0x7a]	8498	1			T1	22		T3	1		T4	3
valid_sources[0x7b]	9266	1			T1	10		T4	1		T12	3
valid_sources[0x7c]	8671	1			T1	20		T4	1		T12	10
valid_sources[0x7d]	27315	1			T1	4		T4	3		T12	10
valid_sources[0x7e]	8590	1			T1	7		T12	16		T13	3
valid_sources[0x7f]	8735	1			T1	8		T4	1		T12	2
valid_sources[0x80]	8806	1			T1	7		T4	2		T12	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1281791

1

T1

1112

T3

13

T4

99

values[0x0]

all_enables

biggest_size

150527

1

T1

114

T3

7

T9

2

values[0x1]

all_enables

biggest_size

149590

1

T1

139

T3

3

T9

3