Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	103571845	15955	0	0
claim_transition_if_regwen_rd_A	103571845	1596	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103571845	15955	0	0
T6	12882	0	0	0
T18	0	4	0	0
T28	198486	9	0	0
T29	112164	3	0	0
T30	82292	0	0	0
T46	11728	0	0	0
T61	19856	0	0	0
T90	0	6	0	0
T93	0	2	0	0
T109	0	10	0	0
T140	0	4	0	0
T141	0	2	0	0
T142	0	1	0	0
T143	0	9	0	0
T144	2779	0	0	0
T145	1273	0	0	0
T146	1363	0	0	0
T147	19574	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103571845	1596	0	0
T75	4771	0	0	0
T93	361578	2	0	0
T94	1108	0	0	0
T95	37263	0	0	0
T96	52427	0	0	0
T97	124399	0	0	0
T98	15517	0	0	0
T99	47020	0	0	0
T112	0	44	0	0
T115	0	38	0	0
T120	0	53	0	0
T148	0	12	0	0
T149	0	4	0	0
T150	0	108	0	0
T151	0	10	0	0
T152	0	6	0	0
T153	0	4	0	0
T154	1501	0	0	0
T155	19596	0	0	0