Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.64	100.00	55.56	75.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic	75.00			75.00
tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic	75.00			75.00
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic	85.19	100.00	55.56				100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic	85.19	100.00	55.56				100.00

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
75.00			75.00				gen_scan.i_dft_tck_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
75.00			75.00				u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_clock_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rst_n_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	8	6	75.00
Total Bits 0->1	4	3	75.00
Total Bits 1->0	4	3	75.00

Ports	4	3	75.00
Port Bits	8	6	75.00
Port Bits 0->1	4	3	75.00
Port Bits 1->0	4	3	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sel_i	No	No		No		INPUT
clk_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	73235141	73233513	0	0
selKnown1	101338057	101336429	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	73235141	73233513	0	0
T1	100575	100573	0	0
T2	126410	126408	0	0
T3	7925	7923	0	0
T4	17	15	0	0
T5	0	46729	0	0
T9	2	0	0	0
T10	60	58	0	0
T11	56	54	0	0
T12	76	74	0	0
T13	15	13	0	0
T14	84	82	0	0
T21	0	433674	0	0
T22	0	29770	0	0
T23	0	90	0	0
T25	0	80	0	0
T27	0	152235	0	0
T28	0	124722	0	0
T29	0	977310	0	0
T30	0	60070	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	101338057	101336429	0	0
T1	219251	219250	0	0
T2	169909	169908	0	0
T3	4852	4851	0	0
T4	6102	6101	0	0
T5	4	3	0	0
T7	0	2	0	0
T8	0	2	0	0
T9	1307	1306	0	0
T10	18047	18046	0	0
T11	19556	19555	0	0
T12	31104	31103	0	0
T13	5584	5583	0	0
T14	64012	64011	0	0
T15	1	0	0	0
T21	1	0	0	0
T22	1	0	0	0
T24	1	0	0	0
T27	1	0	0	0
T31	0	5	0	0
T32	0	5	0	0
T33	0	3	0	0
T34	0	4	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	1	0	0	0
T39	1	0	0	0
T40	1	0	0	0
T41	1	0	0	0

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	8	6	75.00
Total Bits 0->1	4	3	75.00
Total Bits 1->0	4	3	75.00

Ports	4	3	75.00
Port Bits	8	6	75.00
Port Bits 0->1	4	3	75.00
Port Bits 1->0	4	3	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
sel_i	No	No		No		INPUT
clk_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	8	6	75.00
Total Bits 0->1	4	3	75.00
Total Bits 1->0	4	3	75.00

Ports	4	3	75.00
Port Bits	8	6	75.00
Port Bits 0->1	4	3	75.00
Port Bits 1->0	4	3	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk0_i	Yes	Yes	T1,T2,T5	Yes	T1,T2,T3	INPUT
clk1_i	Yes	Yes	T3,T5,T6	Yes	T5,T7,T8	INPUT
sel_i	No	No		No		INPUT
clk_o	Yes	Yes	T1,T2,T5	Yes	T1,T2,T3	OUTPUT

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	73178517	73177703	0	0
selKnown1	101337120	101336306	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	73178517	73177703	0	0
T1	100528	100527	0	0
T2	126359	126358	0	0
T3	7924	7923	0	0
T4	1	0	0	0
T5	0	46729	0	0
T9	1	0	0	0
T10	1	0	0	0
T11	1	0	0	0
T12	1	0	0	0
T13	1	0	0	0
T14	1	0	0	0
T21	0	433674	0	0
T22	0	29770	0	0
T27	0	152235	0	0
T28	0	124722	0	0
T29	0	977310	0	0
T30	0	60070	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	101337120	101336306	0	0
T1	219251	219250	0	0
T2	169909	169908	0	0
T3	4852	4851	0	0
T4	6102	6101	0	0
T9	1307	1306	0	0
T10	18047	18046	0	0
T11	19556	19555	0	0
T12	31104	31103	0	0
T13	5584	5583	0	0
T14	64012	64011	0	0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	56624	55810	0	0
selKnown1	937	123	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	56624	55810	0	0
T1	47	46	0	0
T2	51	50	0	0
T3	1	0	0	0
T4	16	15	0	0
T9	1	0	0	0
T10	59	58	0	0
T11	55	54	0	0
T12	75	74	0	0
T13	14	13	0	0
T14	83	82	0	0
T23	0	90	0	0
T25	0	80	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	937	123	0	0
T5	4	3	0	0
T7	0	2	0	0
T8	0	2	0	0
T15	1	0	0	0
T21	1	0	0	0
T22	1	0	0	0
T24	1	0	0	0
T27	1	0	0	0
T31	0	5	0	0
T32	0	5	0	0
T33	0	3	0	0
T34	0	4	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	1	0	0	0
T39	1	0	0	0
T40	1	0	0	0
T41	1	0	0	0