Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1552173	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1774960

1

T1

716

T2

21

T3

3072

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2978216	1			T1	567		T2	26		T3	3660
values[0x0]	173713	1			T1	292		T2	3		T3	801
values[0x1]	175204	1			T1	268		T2	5		T3	876

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1232249	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2094884

1

T1

816

T2

25

T3

3596

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10073	1			T1	6		T3	15		T11	1
valid_sources[0x01]	10147	1			T1	2		T3	29		T11	3
valid_sources[0x02]	29403	1			T1	1		T3	19		T11	3
valid_sources[0x03]	14305	1			T1	4		T3	28		T11	6
valid_sources[0x04]	10448	1			T1	6		T3	17		T11	1
valid_sources[0x05]	14669	1			T1	6		T3	29		T11	4
valid_sources[0x06]	9883	1			T1	7		T3	18		T10	1
valid_sources[0x07]	10532	1			T3	13		T10	2		T11	4
valid_sources[0x08]	10150	1			T1	6		T3	11		T10	1
valid_sources[0x09]	10178	1			T1	6		T2	2		T3	33
valid_sources[0x0a]	10197	1			T1	5		T3	43		T11	4
valid_sources[0x0b]	10333	1			T1	3		T3	8		T11	3
valid_sources[0x0c]	43968	1			T1	3		T3	15		T11	4
valid_sources[0x0d]	10696	1			T1	6		T3	18		T11	2
valid_sources[0x0e]	11653	1			T3	19		T14	6		T22	5
valid_sources[0x0f]	14827	1			T1	8		T3	31		T11	5
valid_sources[0x10]	10169	1			T1	1		T3	8		T10	1
valid_sources[0x11]	10485	1			T1	5		T3	38		T11	4
valid_sources[0x12]	56571	1			T1	5		T3	24		T11	6
valid_sources[0x13]	11001	1			T1	3		T3	33		T11	1
valid_sources[0x14]	63305	1			T1	2		T3	16		T11	6
valid_sources[0x15]	16332	1			T1	3		T3	15		T11	5
valid_sources[0x16]	10111	1			T1	2		T3	22		T11	3
valid_sources[0x17]	9874	1			T1	6		T3	17		T14	7
valid_sources[0x18]	10387	1			T1	2		T3	22		T10	1
valid_sources[0x19]	11774	1			T1	5		T3	21		T11	3
valid_sources[0x1a]	10276	1			T1	3		T3	20		T14	12
valid_sources[0x1b]	10613	1			T1	10		T2	6		T3	24
valid_sources[0x1c]	10224	1			T1	7		T3	12		T11	3
valid_sources[0x1d]	11122	1			T1	13		T3	9		T10	2
valid_sources[0x1e]	9991	1			T1	2		T3	19		T11	2
valid_sources[0x1f]	21737	1			T1	2		T3	30		T10	1
valid_sources[0x20]	10782	1			T1	3		T3	16		T10	3
valid_sources[0x21]	12320	1			T1	3		T3	15		T11	3
valid_sources[0x22]	10133	1			T1	7		T3	16		T11	4
valid_sources[0x23]	11710	1			T1	4		T3	31		T10	3
valid_sources[0x24]	10499	1			T1	3		T3	14		T11	3
valid_sources[0x25]	32480	1			T3	22		T10	3		T11	3
valid_sources[0x26]	11548	1			T1	1		T3	40		T11	4
valid_sources[0x27]	10463	1			T1	2		T3	18		T11	4
valid_sources[0x28]	11819	1			T1	3		T3	15		T11	6
valid_sources[0x29]	10064	1			T1	9		T3	14		T11	1
valid_sources[0x2a]	12697	1			T1	5		T3	14		T10	2
valid_sources[0x2b]	10182	1			T1	9		T3	28		T11	8
valid_sources[0x2c]	10665	1			T1	2		T3	21		T10	1
valid_sources[0x2d]	10290	1			T1	1		T3	8		T11	1
valid_sources[0x2e]	10716	1			T1	9		T3	9		T10	1
valid_sources[0x2f]	43254	1			T1	5		T3	32		T11	4
valid_sources[0x30]	10169	1			T1	4		T3	18		T11	2
valid_sources[0x31]	12663	1			T1	1		T3	20		T11	4
valid_sources[0x32]	9871	1			T1	4		T3	15		T10	2
valid_sources[0x33]	9999	1			T1	12		T3	24		T10	1
valid_sources[0x34]	10186	1			T1	6		T3	15		T11	4
valid_sources[0x35]	10025	1			T1	9		T3	19		T11	3
valid_sources[0x36]	10613	1			T1	1		T3	30		T11	2
valid_sources[0x37]	10528	1			T3	24		T11	2		T14	9
valid_sources[0x38]	10220	1			T1	6		T2	3		T3	27
valid_sources[0x39]	12027	1			T1	2		T3	17		T11	2
valid_sources[0x3a]	9947	1			T1	3		T3	20		T11	4
valid_sources[0x3b]	10468	1			T1	4		T3	16		T11	6
valid_sources[0x3c]	14532	1			T1	5		T3	25		T14	9
valid_sources[0x3d]	10465	1			T1	2		T3	22		T11	6
valid_sources[0x3e]	10083	1			T1	2		T3	22		T10	2
valid_sources[0x3f]	12457	1			T1	4		T3	24		T10	1
valid_sources[0x40]	10371	1			T1	4		T3	17		T11	2
valid_sources[0x41]	16780	1			T1	1		T3	28		T14	2
valid_sources[0x42]	50829	1			T1	6		T3	30		T11	6
valid_sources[0x43]	10747	1			T1	5		T3	16		T11	1
valid_sources[0x44]	10294	1			T1	9		T3	12		T11	1
valid_sources[0x45]	10184	1			T1	4		T3	12		T10	3
valid_sources[0x46]	10055	1			T1	2		T3	30		T11	2
valid_sources[0x47]	10469	1			T1	6		T3	14		T11	2
valid_sources[0x48]	11003	1			T1	1		T3	12		T11	4
valid_sources[0x49]	9971	1			T1	2		T3	4		T11	1
valid_sources[0x4a]	11648	1			T1	4		T3	23		T11	2
valid_sources[0x4b]	10003	1			T1	1		T3	21		T11	1
valid_sources[0x4c]	11724	1			T1	1		T3	10		T11	3
valid_sources[0x4d]	10754	1			T1	2		T3	15		T11	1
valid_sources[0x4e]	10221	1			T1	2		T3	18		T11	3
valid_sources[0x4f]	9980	1			T1	4		T3	16		T11	7
valid_sources[0x50]	10976	1			T1	5		T3	15		T11	5
valid_sources[0x51]	10524	1			T1	3		T3	33		T14	11
valid_sources[0x52]	10360	1			T1	5		T3	13		T11	2
valid_sources[0x53]	9914	1			T1	1		T3	13		T11	3
valid_sources[0x54]	11481	1			T1	6		T3	25		T11	3
valid_sources[0x55]	12112	1			T3	26		T11	5		T22	5
valid_sources[0x56]	11361	1			T1	12		T3	33		T11	4
valid_sources[0x57]	10679	1			T3	15		T10	1		T11	4
valid_sources[0x58]	10035	1			T1	2		T3	25		T14	12
valid_sources[0x59]	9877	1			T1	3		T3	22		T11	5
valid_sources[0x5a]	10557	1			T1	23		T3	19		T11	8
valid_sources[0x5b]	9841	1			T1	11		T3	11		T11	2
valid_sources[0x5c]	9969	1			T1	1		T3	17		T10	1
valid_sources[0x5d]	10240	1			T1	9		T3	34		T11	6
valid_sources[0x5e]	11424	1			T1	5		T3	17		T11	1
valid_sources[0x5f]	10436	1			T1	6		T3	16		T11	3
valid_sources[0x60]	10594	1			T1	2		T3	21		T11	3
valid_sources[0x61]	10071	1			T1	2		T3	16		T11	1
valid_sources[0x62]	9918	1			T1	3		T3	19		T11	2
valid_sources[0x63]	10204	1			T1	13		T3	23		T11	3
valid_sources[0x64]	10322	1			T1	4		T3	21		T11	4
valid_sources[0x65]	11201	1			T1	2		T3	34		T11	2
valid_sources[0x66]	9826	1			T1	1		T3	11		T10	3
valid_sources[0x67]	10044	1			T3	13		T11	4		T14	3
valid_sources[0x68]	19603	1			T1	2		T3	16		T10	2
valid_sources[0x69]	11686	1			T1	2		T3	18		T11	3
valid_sources[0x6a]	10434	1			T1	11		T3	41		T11	2
valid_sources[0x6b]	11965	1			T1	2		T3	26		T11	2
valid_sources[0x6c]	10323	1			T1	1		T3	30		T11	5
valid_sources[0x6d]	21574	1			T1	5		T3	24		T10	2
valid_sources[0x6e]	12812	1			T1	5		T3	11		T11	5
valid_sources[0x6f]	10183	1			T1	2		T2	6		T3	24
valid_sources[0x70]	9829	1			T1	2		T3	23		T11	6
valid_sources[0x71]	11475	1			T1	1		T3	12		T11	1
valid_sources[0x72]	10101	1			T1	7		T3	28		T14	8
valid_sources[0x73]	10448	1			T1	8		T3	21		T11	4
valid_sources[0x74]	10606	1			T1	2		T3	10		T10	1
valid_sources[0x75]	10613	1			T1	2		T3	12		T11	1
valid_sources[0x76]	10093	1			T1	2		T3	10		T11	1
valid_sources[0x77]	15300	1			T1	2		T3	15		T11	2
valid_sources[0x78]	38748	1			T1	2		T3	18		T11	5
valid_sources[0x79]	10437	1			T1	8		T3	30		T11	2
valid_sources[0x7a]	11182	1			T1	7		T3	22		T11	3
valid_sources[0x7b]	10108	1			T1	3		T3	30		T11	6
valid_sources[0x7c]	10197	1			T1	11		T3	23		T11	3
valid_sources[0x7d]	11154	1			T1	2		T3	21		T11	2
valid_sources[0x7e]	9871	1			T1	6		T3	17		T10	1
valid_sources[0x7f]	11007	1			T1	1		T3	24		T10	2
valid_sources[0x80]	10471	1			T1	7		T3	17		T11	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1474341

1

T1

238

T2

15

T3

1630

values[0x0]

all_enables

biggest_size

150849

1

T1

254

T2

3

T3

691

values[0x1]

all_enables

biggest_size

149770

1

T1

224

T2

3

T3

751