Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	102835560	14349	0	0
claim_transition_if_regwen_rd_A	102835560	1294	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102835560	14349	0	0
T9	25390	0	0	0
T17	0	11	0	0
T43	138388	2	0	0
T46	50073	0	0	0
T48	0	4	0	0
T54	30486	0	0	0
T64	0	8	0	0
T66	23801	0	0	0
T152	0	6	0	0
T153	0	3	0	0
T154	0	4	0	0
T155	0	4	0	0
T156	0	6	0	0
T157	0	9	0	0
T158	5111	0	0	0
T159	1390	0	0	0
T160	3792	0	0	0
T161	1228	0	0	0
T162	23901	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102835560	1294	0	0
T33	40122	0	0	0
T48	436932	8	0	0
T119	0	14	0	0
T120	0	4	0	0
T153	0	16	0	0
T163	0	2	0	0
T164	0	1	0	0
T165	0	12	0	0
T166	0	132	0	0
T167	0	30	0	0
T168	0	10	0	0
T169	5278	0	0	0
T170	1176	0	0	0
T171	34295	0	0	0
T172	18135	0	0	0
T173	28012	0	0	0
T174	3169	0	0	0
T175	32799	0	0	0
T176	17335	0	0	0