Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1562085	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1781914

1

T1

221

T2

13

T3

841

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2998209	1			T1	183		T3	699		T4	2305
values[0x0]	172125	1			T1	91		T2	20		T3	296
values[0x1]	173665	1			T1	77		T2	22		T3	256

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1240157	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2103842

1

T1

245

T2

16

T3

931

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8748	1			T3	9		T4	1		T11	3
valid_sources[0x01]	9010	1			T1	1		T3	5		T4	9
valid_sources[0x02]	8278	1			T3	7		T4	15		T11	1
valid_sources[0x03]	10420	1			T3	2		T4	13		T11	2
valid_sources[0x04]	8337	1			T1	10		T3	6		T4	9
valid_sources[0x05]	9335	1			T1	1		T3	8		T4	32
valid_sources[0x06]	9931	1			T1	5		T3	2		T4	10
valid_sources[0x07]	8275	1			T3	13		T4	13		T28	13
valid_sources[0x08]	8378	1			T1	1		T3	2		T4	4
valid_sources[0x09]	11338	1			T3	4		T4	9		T11	3
valid_sources[0x0a]	98694	1			T3	6		T4	5		T11	2
valid_sources[0x0b]	8201	1			T1	3		T3	4		T4	19
valid_sources[0x0c]	10122	1			T1	12		T3	2		T4	25
valid_sources[0x0d]	8483	1			T1	1		T3	6		T4	11
valid_sources[0x0e]	8116	1			T3	4		T4	33		T19	13
valid_sources[0x0f]	8449	1			T3	2		T4	27		T11	2
valid_sources[0x10]	11469	1			T2	1		T3	4		T4	19
valid_sources[0x11]	9138	1			T3	5		T4	3		T11	7
valid_sources[0x12]	8291	1			T3	2		T4	1		T11	6
valid_sources[0x13]	8298	1			T1	2		T3	2		T4	13
valid_sources[0x14]	8437	1			T3	5		T4	3		T11	1
valid_sources[0x15]	9082	1			T2	1		T3	5		T11	3
valid_sources[0x16]	9893	1			T1	5		T3	7		T4	31
valid_sources[0x17]	8075	1			T2	1		T3	4		T4	10
valid_sources[0x18]	8158	1			T2	1		T3	4		T4	12
valid_sources[0x19]	8437	1			T3	5		T4	10		T11	13
valid_sources[0x1a]	99129	1			T3	8		T4	6		T11	1
valid_sources[0x1b]	7961	1			T3	2		T4	6		T11	3
valid_sources[0x1c]	10501	1			T3	5		T4	10		T12	8
valid_sources[0x1d]	11967	1			T1	1		T3	3		T4	9
valid_sources[0x1e]	8439	1			T2	1		T3	6		T4	11
valid_sources[0x1f]	9355	1			T1	2		T3	3		T11	7
valid_sources[0x20]	8314	1			T3	8		T4	15		T11	3
valid_sources[0x21]	58532	1			T3	4		T4	6		T19	15
valid_sources[0x22]	8175	1			T1	1		T4	27		T12	13
valid_sources[0x23]	10269	1			T1	1		T3	4		T4	18
valid_sources[0x24]	7931	1			T3	6		T11	9		T12	8
valid_sources[0x25]	8199	1			T3	1		T4	3		T11	2
valid_sources[0x26]	9795	1			T3	5		T4	27		T11	1
valid_sources[0x27]	9670	1			T3	5		T4	49		T11	6
valid_sources[0x28]	8250	1			T3	2		T11	4		T19	9
valid_sources[0x29]	8446	1			T3	6		T4	6		T11	4
valid_sources[0x2a]	10160	1			T1	13		T3	11		T4	16
valid_sources[0x2b]	9126	1			T3	2		T4	1		T11	13
valid_sources[0x2c]	21860	1			T3	5		T4	5		T11	6
valid_sources[0x2d]	9743	1			T1	2		T3	3		T4	14
valid_sources[0x2e]	9764	1			T1	4		T2	1		T11	7
valid_sources[0x2f]	8160	1			T1	2		T3	11		T11	2
valid_sources[0x30]	9417	1			T3	2		T4	7		T11	5
valid_sources[0x31]	9197	1			T3	7		T4	2		T11	5
valid_sources[0x32]	37617	1			T3	5		T4	33		T11	4
valid_sources[0x33]	7983	1			T3	3		T4	4		T19	15
valid_sources[0x34]	8553	1			T1	1		T3	4		T11	1
valid_sources[0x35]	8554	1			T2	1		T3	6		T4	2
valid_sources[0x36]	8258	1			T3	4		T4	10		T11	7
valid_sources[0x37]	9174	1			T3	3		T4	16		T28	1
valid_sources[0x38]	8586	1			T3	3		T4	13		T19	17
valid_sources[0x39]	8283	1			T3	7		T4	32		T11	2
valid_sources[0x3a]	8261	1			T4	2		T11	2		T28	2
valid_sources[0x3b]	9519	1			T1	10		T2	1		T3	2
valid_sources[0x3c]	8291	1			T3	7		T4	14		T11	3
valid_sources[0x3d]	8694	1			T3	4		T19	18		T112	4
valid_sources[0x3e]	8431	1			T2	1		T3	9		T4	3
valid_sources[0x3f]	10157	1			T1	5		T2	1		T3	4
valid_sources[0x40]	9156	1			T2	1		T3	3		T4	8
valid_sources[0x41]	161812	1			T1	5		T3	7		T4	69
valid_sources[0x42]	8308	1			T2	1		T3	9		T4	12
valid_sources[0x43]	8152	1			T3	4		T11	7		T19	21
valid_sources[0x44]	8659	1			T3	7		T4	34		T11	1
valid_sources[0x45]	8261	1			T3	5		T4	7		T11	2
valid_sources[0x46]	7991	1			T1	4		T3	4		T4	13
valid_sources[0x47]	8232	1			T3	6		T11	6		T28	6
valid_sources[0x48]	8013	1			T1	2		T3	8		T4	2
valid_sources[0x49]	12269	1			T1	7		T3	8		T4	16
valid_sources[0x4a]	8172	1			T1	10		T3	7		T4	46
valid_sources[0x4b]	8232	1			T3	4		T4	15		T11	2
valid_sources[0x4c]	10918	1			T1	1		T3	4		T4	44
valid_sources[0x4d]	7987	1			T3	3		T11	9		T19	12
valid_sources[0x4e]	8185	1			T3	6		T4	4		T19	17
valid_sources[0x4f]	8134	1			T1	3		T2	1		T3	2
valid_sources[0x50]	8434	1			T3	10		T4	28		T11	5
valid_sources[0x51]	12430	1			T3	5		T4	6		T28	4
valid_sources[0x52]	8179	1			T1	1		T2	3		T3	7
valid_sources[0x53]	8294	1			T2	1		T3	1		T4	29
valid_sources[0x54]	8381	1			T1	5		T3	6		T4	13
valid_sources[0x55]	9751	1			T3	5		T4	15		T11	2
valid_sources[0x56]	12542	1			T1	4		T3	2		T4	5
valid_sources[0x57]	9012	1			T1	6		T3	6		T4	8
valid_sources[0x58]	8475	1			T3	6		T4	1		T11	1
valid_sources[0x59]	8451	1			T3	8		T4	5		T11	1
valid_sources[0x5a]	8741	1			T3	6		T4	12		T12	56
valid_sources[0x5b]	8143	1			T3	8		T11	1		T28	2
valid_sources[0x5c]	8545	1			T1	6		T3	5		T4	3
valid_sources[0x5d]	8187	1			T3	5		T4	7		T28	2
valid_sources[0x5e]	8202	1			T3	4		T4	28		T19	21
valid_sources[0x5f]	10139	1			T1	1		T3	5		T4	12
valid_sources[0x60]	58163	1			T3	6		T4	18		T11	5
valid_sources[0x61]	10153	1			T3	8		T4	25		T11	2
valid_sources[0x62]	8263	1			T3	2		T4	2		T28	6
valid_sources[0x63]	8056	1			T1	2		T2	1		T3	8
valid_sources[0x64]	8335	1			T3	7		T4	23		T28	5
valid_sources[0x65]	8466	1			T1	5		T3	5		T4	15
valid_sources[0x66]	8140	1			T3	13		T4	11		T11	3
valid_sources[0x67]	14141	1			T3	2		T4	13		T11	2
valid_sources[0x68]	8327	1			T1	4		T3	6		T4	16
valid_sources[0x69]	8574	1			T3	1		T4	1		T28	2
valid_sources[0x6a]	10540	1			T1	4		T3	9		T4	2
valid_sources[0x6b]	14408	1			T1	2		T3	2		T4	5
valid_sources[0x6c]	8024	1			T1	3		T2	1		T3	5
valid_sources[0x6d]	11546	1			T3	10		T4	17		T11	4
valid_sources[0x6e]	8458	1			T3	5		T4	5		T19	16
valid_sources[0x6f]	17289	1			T2	1		T3	6		T4	4
valid_sources[0x70]	8161	1			T2	1		T3	9		T4	10
valid_sources[0x71]	8607	1			T3	8		T4	20		T11	1
valid_sources[0x72]	8546	1			T3	3		T11	3		T19	17
valid_sources[0x73]	9841	1			T1	2		T3	4		T4	9
valid_sources[0x74]	8441	1			T1	3		T2	1		T3	6
valid_sources[0x75]	10740	1			T3	2		T4	28		T11	1
valid_sources[0x76]	8390	1			T3	3		T4	2		T11	1
valid_sources[0x77]	9658	1			T3	3		T4	4		T11	1
valid_sources[0x78]	104175	1			T3	2		T4	17		T12	11
valid_sources[0x79]	8122	1			T3	4		T4	8		T11	1
valid_sources[0x7a]	9496	1			T3	3		T28	3		T19	16
valid_sources[0x7b]	42864	1			T1	6		T3	7		T11	3
valid_sources[0x7c]	9081	1			T1	5		T2	1		T3	7
valid_sources[0x7d]	8591	1			T3	7		T4	6		T11	2
valid_sources[0x7e]	8704	1			T1	3		T3	3		T4	35
valid_sources[0x7f]	10311	1			T3	5		T4	19		T28	6
valid_sources[0x80]	8473	1			T1	3		T3	3		T4	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1484079

1

T1

70

T3

357

T4

1159

values[0x0]

all_enables

biggest_size

149154

1

T1

83

T2

8

T3

259

values[0x1]

all_enables

biggest_size

148681

1

T1

68

T2

5

T3

225