Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	103673176	13703	0	0
claim_transition_if_regwen_rd_A	103673176	1448	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103673176	13703	0	0
T43	0	7	0	0
T44	0	2	0	0
T59	37239	0	0	0
T79	0	8	0	0
T90	252462	1	0	0
T91	198429	2	0	0
T114	0	1	0	0
T115	0	2	0	0
T119	0	1	0	0
T154	0	10	0	0
T155	0	3	0	0
T156	37282	0	0	0
T157	9478	0	0	0
T158	36097	0	0	0
T159	29351	0	0	0
T160	36828	0	0	0
T161	121227	0	0	0
T162	7222	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103673176	1448	0	0
T43	0	1	0	0
T59	37239	0	0	0
T90	252462	12	0	0
T91	198429	0	0	0
T114	0	11	0	0
T119	0	11	0	0
T124	0	8	0	0
T131	0	15	0	0
T155	0	1	0	0
T156	37282	0	0	0
T157	9478	0	0	0
T158	36097	0	0	0
T159	29351	0	0	0
T160	36828	0	0	0
T161	121227	0	0	0
T162	7222	0	0	0
T163	0	5	0	0
T164	0	10	0	0
T165	0	2	0	0