Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1953186	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2181798

1

T1

127

T2

877

T3

182178

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3771540	1			T1	159		T2	781		T3	357410
values[0x0]	181458	1			T1	80		T2	319		T3	1886
values[0x1]	181986	1			T1	77		T2	265		T3	1842

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1552717	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2582267

1

T1

149

T2

982

T3

218410

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12223	1			T2	13		T3	1427		T14	8
valid_sources[0x01]	11834	1			T2	14		T3	1281		T14	11
valid_sources[0x02]	13316	1			T1	3		T2	2		T3	1457
valid_sources[0x03]	13231	1			T3	1295		T14	16		T21	2
valid_sources[0x04]	12484	1			T2	6		T3	1344		T14	32
valid_sources[0x05]	14208	1			T2	5		T3	1352		T14	12
valid_sources[0x06]	19860	1			T2	4		T3	1450		T14	21
valid_sources[0x07]	13191	1			T1	1		T2	6		T3	1266
valid_sources[0x08]	148287	1			T1	1		T2	3		T3	1381
valid_sources[0x09]	11737	1			T1	3		T2	4		T3	1384
valid_sources[0x0a]	14072	1			T1	3		T2	9		T3	1410
valid_sources[0x0b]	13694	1			T1	2		T2	7		T3	1303
valid_sources[0x0c]	11934	1			T2	7		T3	1507		T14	18
valid_sources[0x0d]	11974	1			T3	1384		T14	35		T78	5
valid_sources[0x0e]	13050	1			T2	2		T3	1410		T14	16
valid_sources[0x0f]	11914	1			T1	3		T2	10		T3	1312
valid_sources[0x10]	15332	1			T2	6		T3	1509		T14	10
valid_sources[0x11]	11999	1			T2	18		T3	1388		T14	11
valid_sources[0x12]	14294	1			T3	1497		T14	13		T15	126
valid_sources[0x13]	11982	1			T2	2		T3	1426		T13	1
valid_sources[0x14]	12160	1			T1	3		T2	4		T3	1500
valid_sources[0x15]	11708	1			T2	4		T3	1298		T14	13
valid_sources[0x16]	12851	1			T1	5		T2	3		T3	1451
valid_sources[0x17]	17775	1			T1	1		T2	5		T3	1363
valid_sources[0x18]	11838	1			T1	1		T2	6		T3	1542
valid_sources[0x19]	14173	1			T1	3		T2	6		T3	1489
valid_sources[0x1a]	33067	1			T2	5		T3	1398		T14	9
valid_sources[0x1b]	11918	1			T2	6		T3	1297		T14	14
valid_sources[0x1c]	11644	1			T1	2		T2	3		T3	1432
valid_sources[0x1d]	12604	1			T1	7		T2	9		T3	1282
valid_sources[0x1e]	11615	1			T2	1		T3	1475		T14	4
valid_sources[0x1f]	11398	1			T1	4		T2	6		T3	1339
valid_sources[0x20]	12064	1			T2	12		T3	1385		T14	17
valid_sources[0x21]	33996	1			T1	2		T2	8		T3	1557
valid_sources[0x22]	35299	1			T3	1459		T14	5		T21	8
valid_sources[0x23]	12813	1			T1	4		T2	2		T3	1403
valid_sources[0x24]	12597	1			T2	9		T3	1338		T14	12
valid_sources[0x25]	11654	1			T1	2		T2	2		T3	1364
valid_sources[0x26]	12404	1			T2	6		T3	1371		T14	12
valid_sources[0x27]	11789	1			T2	5		T3	1299		T14	15
valid_sources[0x28]	12017	1			T2	4		T3	1401		T14	7
valid_sources[0x29]	14093	1			T1	1		T2	7		T3	1375
valid_sources[0x2a]	12881	1			T1	1		T2	1		T3	1398
valid_sources[0x2b]	11895	1			T2	1		T3	1308		T14	18
valid_sources[0x2c]	11539	1			T1	1		T2	7		T3	1498
valid_sources[0x2d]	13046	1			T2	17		T3	1342		T14	22
valid_sources[0x2e]	14939	1			T1	1		T2	1		T3	1406
valid_sources[0x2f]	12141	1			T2	3		T3	1392		T14	33
valid_sources[0x30]	12126	1			T3	1572		T14	23		T15	144
valid_sources[0x31]	12299	1			T1	1		T2	4		T3	1466
valid_sources[0x32]	11775	1			T2	9		T3	1376		T14	22
valid_sources[0x33]	11627	1			T1	7		T2	4		T3	1431
valid_sources[0x34]	12280	1			T2	4		T3	1388		T14	15
valid_sources[0x35]	11705	1			T1	1		T2	2		T3	1366
valid_sources[0x36]	12420	1			T1	1		T2	1		T3	1477
valid_sources[0x37]	13387	1			T2	10		T3	1430		T14	15
valid_sources[0x38]	13946	1			T1	5		T2	4		T3	1332
valid_sources[0x39]	11724	1			T2	6		T3	1321		T14	11
valid_sources[0x3a]	11858	1			T2	2		T3	1373		T14	22
valid_sources[0x3b]	12611	1			T2	6		T3	1524		T14	18
valid_sources[0x3c]	22787	1			T1	4		T2	2		T3	1383
valid_sources[0x3d]	28995	1			T1	2		T2	2		T3	1450
valid_sources[0x3e]	27147	1			T3	1291		T14	10		T16	1
valid_sources[0x3f]	12776	1			T2	18		T3	1491		T14	15
valid_sources[0x40]	12927	1			T2	5		T3	1498		T14	21
valid_sources[0x41]	12007	1			T1	2		T2	10		T3	1466
valid_sources[0x42]	12250	1			T2	2		T3	1420		T14	7
valid_sources[0x43]	11494	1			T1	3		T2	5		T3	1362
valid_sources[0x44]	11645	1			T1	1		T2	2		T3	1375
valid_sources[0x45]	12090	1			T1	1		T2	3		T3	1403
valid_sources[0x46]	11705	1			T1	1		T2	1		T3	1437
valid_sources[0x47]	12987	1			T2	2		T3	1396		T14	10
valid_sources[0x48]	13266	1			T2	23		T3	1306		T14	21
valid_sources[0x49]	12087	1			T1	1		T2	3		T3	1513
valid_sources[0x4a]	12028	1			T1	2		T2	10		T3	1281
valid_sources[0x4b]	12169	1			T1	1		T2	13		T3	1374
valid_sources[0x4c]	11983	1			T2	1		T3	1410		T14	4
valid_sources[0x4d]	12019	1			T1	1		T2	12		T3	1535
valid_sources[0x4e]	12653	1			T1	1		T2	1		T3	1384
valid_sources[0x4f]	13933	1			T2	3		T3	1390		T14	29
valid_sources[0x50]	14516	1			T1	2		T2	8		T3	1394
valid_sources[0x51]	12946	1			T1	2		T2	5		T3	1279
valid_sources[0x52]	12908	1			T2	8		T3	1367		T14	5
valid_sources[0x53]	13521	1			T1	3		T2	7		T3	1279
valid_sources[0x54]	13658	1			T2	1		T3	1453		T14	16
valid_sources[0x55]	12231	1			T1	1		T2	11		T3	1481
valid_sources[0x56]	11951	1			T1	1		T2	12		T3	1378
valid_sources[0x57]	13377	1			T1	9		T3	1333		T14	5
valid_sources[0x58]	11920	1			T2	8		T3	1378		T14	27
valid_sources[0x59]	11802	1			T2	1		T3	1457		T14	4
valid_sources[0x5a]	12340	1			T1	2		T2	6		T3	1369
valid_sources[0x5b]	13252	1			T1	2		T2	1		T3	1400
valid_sources[0x5c]	13047	1			T1	2		T2	3		T3	1436
valid_sources[0x5d]	12861	1			T2	3		T3	1357		T14	9
valid_sources[0x5e]	86022	1			T1	2		T2	7		T3	1423
valid_sources[0x5f]	13441	1			T2	5		T3	1537		T14	12
valid_sources[0x60]	11856	1			T1	7		T2	8		T3	1515
valid_sources[0x61]	12859	1			T1	2		T2	4		T3	1470
valid_sources[0x62]	13790	1			T2	13		T3	1339		T14	14
valid_sources[0x63]	11725	1			T2	6		T3	1370		T14	4
valid_sources[0x64]	11739	1			T1	2		T2	2		T3	1389
valid_sources[0x65]	11710	1			T1	4		T2	6		T3	1360
valid_sources[0x66]	11803	1			T1	1		T2	1		T3	1414
valid_sources[0x67]	11526	1			T2	4		T3	1511		T14	46
valid_sources[0x68]	11422	1			T2	6		T3	1286		T14	4
valid_sources[0x69]	11944	1			T1	4		T2	2		T3	1361
valid_sources[0x6a]	12195	1			T1	2		T2	10		T3	1447
valid_sources[0x6b]	11772	1			T1	4		T2	26		T3	1472
valid_sources[0x6c]	11835	1			T2	8		T3	1486		T14	9
valid_sources[0x6d]	13144	1			T1	2		T2	5		T3	1326
valid_sources[0x6e]	12169	1			T1	7		T2	2		T3	1360
valid_sources[0x6f]	17736	1			T2	4		T3	1395		T14	13
valid_sources[0x70]	49492	1			T1	1		T2	1		T3	1475
valid_sources[0x71]	12170	1			T1	1		T2	8		T3	1447
valid_sources[0x72]	12145	1			T1	1		T2	11		T3	1313
valid_sources[0x73]	14227	1			T1	2		T2	2		T3	1356
valid_sources[0x74]	11801	1			T1	1		T2	3		T3	1468
valid_sources[0x75]	12479	1			T2	3		T3	1316		T14	8
valid_sources[0x76]	12034	1			T2	11		T3	1488		T14	11
valid_sources[0x77]	12003	1			T1	3		T2	2		T3	1341
valid_sources[0x78]	12123	1			T1	3		T2	4		T3	1455
valid_sources[0x79]	11449	1			T2	4		T3	1359		T14	14
valid_sources[0x7a]	12204	1			T1	6		T2	2		T3	1440
valid_sources[0x7b]	13786	1			T2	1		T3	1522		T14	14
valid_sources[0x7c]	11838	1			T2	8		T3	1546		T14	20
valid_sources[0x7d]	11417	1			T2	4		T3	1346		T14	21
valid_sources[0x7e]	11600	1			T1	1		T2	8		T3	1425
valid_sources[0x7f]	11857	1			T1	1		T3	1607		T13	2
valid_sources[0x80]	11655	1			T1	1		T2	4		T3	1433

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1868184

1

T1

75

T2

367

T3

178947

values[0x0]

all_enables

biggest_size

157630

1

T1

32

T2

278

T3

1641

values[0x1]

all_enables

biggest_size

155984

1

T1

20

T2

232

T3

1590