Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	114997512	13923	0	0
claim_transition_if_regwen_rd_A	114997512	1908	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114997512	13923	0	0
T3	470541	9	0	0
T4	283306	0	0	0
T9	130057	0	0	0
T10	15496	0	0	0
T11	23183	0	0	0
T12	1286	0	0	0
T13	844	0	0	0
T14	224537	0	0	0
T21	3444	0	0	0
T44	0	2	0	0
T78	805	0	0	0
T80	0	3	0	0
T87	0	2	0	0
T94	0	1	0	0
T95	0	14	0	0
T96	0	4	0	0
T136	0	9	0	0
T137	0	2	0	0
T138	0	1	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114997512	1908	0	0
T51	22485	0	0	0
T94	145976	0	0	0
T98	0	18	0	0
T121	0	58	0	0
T132	0	2	0	0
T137	293277	3	0	0
T139	0	6	0	0
T140	0	2	0	0
T141	0	1	0	0
T142	0	14	0	0
T143	0	5	0	0
T144	0	5	0	0
T145	151004	0	0	0
T146	1317	0	0	0
T147	7491	0	0	0
T148	72753	0	0	0
T149	30091	0	0	0
T150	2964	0	0	0
T151	849090	0	0	0