Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1400586	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1618016

1

T1

7090

T2

27

T3

305

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2679009	1			T1	13017		T2	43		T3	275
values[0x0]	169303	1			T1	367		T2	4		T3	104
values[0x1]	170290	1			T1	383		T2	4		T3	80

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1111914	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1906688

1

T1

8461

T2

30

T3

335

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12474	1			T1	54		T4	5		T28	3
valid_sources[0x01]	9514	1			T1	66		T4	3		T31	6
valid_sources[0x02]	9449	1			T1	71		T4	6		T31	12
valid_sources[0x03]	9570	1			T1	49		T31	3		T21	2
valid_sources[0x04]	9480	1			T1	42		T4	1		T11	1
valid_sources[0x05]	11807	1			T1	65		T4	7		T31	1
valid_sources[0x06]	9604	1			T1	61		T31	2		T21	3
valid_sources[0x07]	9115	1			T1	47		T2	5		T4	3
valid_sources[0x08]	9519	1			T1	67		T31	6		T21	3
valid_sources[0x09]	9496	1			T1	54		T4	5		T21	9
valid_sources[0x0a]	9821	1			T1	56		T31	2		T21	4
valid_sources[0x0b]	9726	1			T1	61		T4	5		T28	6
valid_sources[0x0c]	9358	1			T1	54		T4	2		T31	8
valid_sources[0x0d]	11194	1			T1	59		T31	2		T21	3
valid_sources[0x0e]	9782	1			T1	40		T21	1		T28	1
valid_sources[0x0f]	9723	1			T1	48		T4	2		T31	2
valid_sources[0x10]	9904	1			T1	44		T4	5		T31	4
valid_sources[0x11]	9580	1			T1	55		T4	4		T21	2
valid_sources[0x12]	12949	1			T1	52		T4	9		T11	1
valid_sources[0x13]	12054	1			T1	57		T4	4		T31	7
valid_sources[0x14]	10195	1			T1	61		T4	5		T31	7
valid_sources[0x15]	9669	1			T1	47		T31	2		T21	4
valid_sources[0x16]	9463	1			T1	57		T4	3		T12	7
valid_sources[0x17]	10651	1			T1	47		T4	6		T31	6
valid_sources[0x18]	9464	1			T1	49		T4	2		T31	8
valid_sources[0x19]	11055	1			T1	44		T4	7		T28	3
valid_sources[0x1a]	9757	1			T1	56		T4	6		T21	1
valid_sources[0x1b]	9279	1			T1	62		T4	2		T31	2
valid_sources[0x1c]	9490	1			T1	36		T4	5		T31	2
valid_sources[0x1d]	9855	1			T1	70		T4	10		T21	5
valid_sources[0x1e]	9594	1			T1	56		T4	7		T21	5
valid_sources[0x1f]	9696	1			T1	59		T31	3		T21	22
valid_sources[0x20]	9216	1			T1	52		T4	6		T31	1
valid_sources[0x21]	9043	1			T1	62		T4	9		T31	2
valid_sources[0x22]	9507	1			T1	44		T4	4		T28	6
valid_sources[0x23]	9380	1			T1	43		T13	1		T31	8
valid_sources[0x24]	11933	1			T1	46		T4	4		T28	7
valid_sources[0x25]	9866	1			T1	38		T4	1		T21	10
valid_sources[0x26]	13044	1			T1	45		T4	6		T31	5
valid_sources[0x27]	9444	1			T1	42		T4	5		T31	9
valid_sources[0x28]	9285	1			T1	54		T4	6		T31	3
valid_sources[0x29]	9989	1			T1	65		T31	10		T28	1
valid_sources[0x2a]	10614	1			T1	50		T4	7		T31	2
valid_sources[0x2b]	9450	1			T1	39		T4	4		T31	2
valid_sources[0x2c]	9850	1			T1	61		T4	8		T31	8
valid_sources[0x2d]	9997	1			T1	55		T31	2		T21	3
valid_sources[0x2e]	11438	1			T1	40		T4	6		T13	2
valid_sources[0x2f]	9459	1			T1	49		T4	2		T11	1
valid_sources[0x30]	10200	1			T1	62		T4	7		T11	1
valid_sources[0x31]	10581	1			T1	57		T4	8		T21	7
valid_sources[0x32]	10685	1			T1	50		T21	3		T28	4
valid_sources[0x33]	9337	1			T1	50		T4	8		T21	9
valid_sources[0x34]	8952	1			T1	57		T4	4		T13	2
valid_sources[0x35]	9325	1			T1	71		T4	7		T31	3
valid_sources[0x36]	10661	1			T1	51		T4	2		T31	6
valid_sources[0x37]	9746	1			T1	60		T4	10		T31	3
valid_sources[0x38]	15661	1			T1	47		T4	4		T31	8
valid_sources[0x39]	9125	1			T1	63		T2	1		T4	1
valid_sources[0x3a]	10575	1			T1	51		T21	6		T28	4
valid_sources[0x3b]	9730	1			T1	64		T4	1		T31	12
valid_sources[0x3c]	10418	1			T1	36		T4	9		T31	5
valid_sources[0x3d]	11909	1			T1	51		T4	7		T12	9
valid_sources[0x3e]	9407	1			T1	57		T4	1		T31	5
valid_sources[0x3f]	16178	1			T1	53		T4	3		T31	8
valid_sources[0x40]	10133	1			T1	55		T4	10		T31	4
valid_sources[0x41]	9471	1			T1	68		T31	3		T28	4
valid_sources[0x42]	9137	1			T1	47		T4	2		T28	1
valid_sources[0x43]	14680	1			T1	39		T4	2		T21	4
valid_sources[0x44]	10553	1			T1	65		T4	5		T31	1
valid_sources[0x45]	9395	1			T1	63		T4	4		T31	2
valid_sources[0x46]	9895	1			T1	61		T4	10		T31	18
valid_sources[0x47]	9785	1			T1	46		T4	1		T31	1
valid_sources[0x48]	10134	1			T1	52		T4	1		T21	5
valid_sources[0x49]	9773	1			T1	55		T31	5		T21	13
valid_sources[0x4a]	9444	1			T1	65		T4	3		T31	9
valid_sources[0x4b]	9695	1			T1	41		T4	16		T31	4
valid_sources[0x4c]	9466	1			T1	60		T4	6		T31	9
valid_sources[0x4d]	11498	1			T1	46		T4	5		T31	1
valid_sources[0x4e]	21835	1			T1	70		T4	3		T31	1
valid_sources[0x4f]	9644	1			T1	61		T4	3		T13	2
valid_sources[0x50]	103113	1			T1	57		T2	2		T10	4
valid_sources[0x51]	14515	1			T1	58		T4	3		T31	11
valid_sources[0x52]	9867	1			T1	53		T4	1		T31	3
valid_sources[0x53]	14128	1			T1	59		T4	1		T31	1
valid_sources[0x54]	9377	1			T1	62		T4	1		T31	10
valid_sources[0x55]	9414	1			T1	46		T4	4		T11	1
valid_sources[0x56]	8985	1			T1	65		T4	3		T31	1
valid_sources[0x57]	9582	1			T1	43		T2	3		T31	10
valid_sources[0x58]	9606	1			T1	57		T4	2		T31	10
valid_sources[0x59]	9450	1			T1	48		T4	1		T31	4
valid_sources[0x5a]	11813	1			T1	63		T4	1		T13	1
valid_sources[0x5b]	10559	1			T1	44		T4	2		T31	3
valid_sources[0x5c]	17346	1			T1	56		T4	3		T31	5
valid_sources[0x5d]	9718	1			T1	55		T4	4		T31	10
valid_sources[0x5e]	9341	1			T1	41		T4	11		T31	6
valid_sources[0x5f]	10815	1			T1	61		T4	2		T31	3
valid_sources[0x60]	9671	1			T1	47		T4	6		T31	2
valid_sources[0x61]	11218	1			T1	49		T4	5		T21	1
valid_sources[0x62]	11598	1			T1	52		T4	1		T11	1
valid_sources[0x63]	9569	1			T1	58		T4	3		T31	5
valid_sources[0x64]	9590	1			T1	52		T4	3		T31	2
valid_sources[0x65]	10723	1			T1	70		T4	7		T31	13
valid_sources[0x66]	9561	1			T1	49		T31	3		T28	9
valid_sources[0x67]	9489	1			T1	56		T4	6		T31	2
valid_sources[0x68]	11083	1			T1	56		T4	3		T11	1
valid_sources[0x69]	10199	1			T1	49		T4	4		T31	8
valid_sources[0x6a]	53216	1			T1	53		T4	5		T11	1
valid_sources[0x6b]	11589	1			T1	53		T4	6		T11	1
valid_sources[0x6c]	9811	1			T1	56		T4	4		T31	6
valid_sources[0x6d]	9443	1			T1	53		T4	5		T31	3
valid_sources[0x6e]	9364	1			T1	45		T4	11		T31	13
valid_sources[0x6f]	12038	1			T1	65		T4	4		T31	5
valid_sources[0x70]	10492	1			T1	52		T4	3		T31	1
valid_sources[0x71]	9617	1			T1	50		T4	4		T31	8
valid_sources[0x72]	9321	1			T1	51		T28	5		T26	8
valid_sources[0x73]	10874	1			T1	47		T31	1		T28	4
valid_sources[0x74]	11009	1			T1	42		T4	4		T13	2
valid_sources[0x75]	11034	1			T1	57		T4	17		T31	11
valid_sources[0x76]	49763	1			T1	58		T4	7		T13	1
valid_sources[0x77]	9907	1			T1	56		T2	9		T4	8
valid_sources[0x78]	10147	1			T1	58		T4	3		T31	8
valid_sources[0x79]	9445	1			T1	73		T4	8		T21	6
valid_sources[0x7a]	9799	1			T1	50		T4	6		T31	1
valid_sources[0x7b]	9408	1			T1	59		T4	2		T13	2
valid_sources[0x7c]	10777	1			T1	45		T4	1		T31	5
valid_sources[0x7d]	56050	1			T1	49		T4	1		T31	8
valid_sources[0x7e]	9462	1			T1	55		T4	2		T21	21
valid_sources[0x7f]	9655	1			T1	43		T4	4		T31	2
valid_sources[0x80]	11300	1			T1	82		T4	2		T31	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1325555

1

T1

6448

T2

20

T3

143

values[0x0]

all_enables

biggest_size

146830

1

T1

307

T2

3

T3

91

values[0x1]

all_enables

biggest_size

145631

1

T1

335

T2

4

T3

71