Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	102858780	13609	0	0
claim_transition_if_regwen_rd_A	102858780	1941	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102858780	13609	0	0
T8	53504	0	0	0
T9	51596	0	0	0
T14	495930	3	0	0
T17	0	1	0	0
T23	20988	0	0	0
T24	33012	0	0	0
T25	1228	0	0	0
T29	20246	0	0	0
T33	3458	0	0	0
T44	802	0	0	0
T45	31723	0	0	0
T49	0	4	0	0
T50	0	1	0	0
T56	0	1	0	0
T91	0	1	0	0
T100	0	13	0	0
T141	0	8	0	0
T142	0	1	0	0
T143	0	3	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102858780	1941	0	0
T18	35344	0	0	0
T36	51853	0	0	0
T46	32915	0	0	0
T47	17823	0	0	0
T51	0	14	0	0
T56	0	10	0	0
T76	3695	0	0	0
T91	100515	7	0	0
T108	0	12	0	0
T121	0	8	0	0
T142	0	11	0	0
T144	0	8	0	0
T145	0	8	0	0
T146	0	20	0	0
T147	0	32	0	0
T148	1716	0	0	0
T149	91072	0	0	0
T150	35900	0	0	0
T151	809	0	0	0