Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1842335	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2042432

1

T1

201

T2

244

T9

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3570952	1			T1	185		T2	178		T10	219
values[0x0]	156040	1			T1	56		T2	90		T9	17
values[0x1]	157775	1			T1	64		T2	86		T9	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1465052	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2419715

1

T1

219

T2

265

T9

14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12076	1			T19	1		T14	3		T21	15
valid_sources[0x01]	9697	1			T2	3		T19	2		T14	4
valid_sources[0x02]	11887	1			T2	2		T14	2		T21	5
valid_sources[0x03]	9599	1			T2	3		T14	4		T21	8
valid_sources[0x04]	9768	1			T1	3		T2	3		T14	5
valid_sources[0x05]	9326	1			T2	3		T13	3		T14	7
valid_sources[0x06]	12547	1			T19	1		T14	3		T26	9
valid_sources[0x07]	12126	1			T1	1		T2	1		T19	1
valid_sources[0x08]	9436	1			T2	1		T14	3		T21	13
valid_sources[0x09]	11186	1			T1	1		T2	1		T12	1
valid_sources[0x0a]	10079	1			T1	3		T14	6		T21	14
valid_sources[0x0b]	9760	1			T2	2		T14	3		T26	6
valid_sources[0x0c]	12110	1			T1	3		T2	1		T14	3
valid_sources[0x0d]	9822	1			T1	1		T19	3		T14	5
valid_sources[0x0e]	23856	1			T1	1		T19	1		T14	5
valid_sources[0x0f]	11443	1			T2	1		T19	2		T14	10
valid_sources[0x10]	209521	1			T2	4		T14	2		T21	14
valid_sources[0x11]	12812	1			T1	2		T19	2		T14	5
valid_sources[0x12]	11252	1			T19	1		T14	3		T21	12
valid_sources[0x13]	20799	1			T1	1		T2	1		T19	3
valid_sources[0x14]	9960	1			T2	2		T14	6		T21	11
valid_sources[0x15]	11186	1			T1	1		T2	3		T19	1
valid_sources[0x16]	9821	1			T1	1		T19	2		T14	3
valid_sources[0x17]	32331	1			T1	2		T2	2		T14	2
valid_sources[0x18]	10155	1			T2	1		T19	2		T14	3
valid_sources[0x19]	9690	1			T1	2		T2	3		T19	1
valid_sources[0x1a]	9522	1			T2	1		T14	5		T26	1
valid_sources[0x1b]	10897	1			T2	1		T19	1		T14	7
valid_sources[0x1c]	10959	1			T1	3		T14	13		T26	3
valid_sources[0x1d]	9804	1			T1	2		T19	1		T14	3
valid_sources[0x1e]	9753	1			T2	1		T14	7		T21	18
valid_sources[0x1f]	9641	1			T1	2		T2	2		T14	11
valid_sources[0x20]	9505	1			T2	1		T19	1		T14	4
valid_sources[0x21]	9718	1			T1	4		T2	1		T19	4
valid_sources[0x22]	9660	1			T1	1		T19	6		T14	1
valid_sources[0x23]	9624	1			T1	3		T2	1		T11	2
valid_sources[0x24]	11849	1			T1	1		T2	2		T19	1
valid_sources[0x25]	9602	1			T2	1		T19	1		T14	4
valid_sources[0x26]	70699	1			T12	1		T14	4		T26	7
valid_sources[0x27]	9839	1			T1	1		T2	1		T14	5
valid_sources[0x28]	9940	1			T1	4		T2	2		T11	1
valid_sources[0x29]	9733	1			T1	1		T2	1		T14	3
valid_sources[0x2a]	26202	1			T1	1		T2	2		T14	5
valid_sources[0x2b]	9564	1			T1	3		T2	2		T19	2
valid_sources[0x2c]	9540	1			T1	4		T2	3		T19	1
valid_sources[0x2d]	10946	1			T1	1		T2	2		T19	1
valid_sources[0x2e]	10296	1			T14	2		T21	18		T15	600
valid_sources[0x2f]	9807	1			T2	2		T14	2		T21	11
valid_sources[0x30]	47756	1			T1	1		T2	2		T19	1
valid_sources[0x31]	9762	1			T1	2		T12	1		T19	1
valid_sources[0x32]	9375	1			T2	1		T19	1		T14	4
valid_sources[0x33]	9911	1			T1	3		T2	1		T11	3
valid_sources[0x34]	9674	1			T1	4		T19	2		T14	7
valid_sources[0x35]	9634	1			T1	1		T2	2		T14	7
valid_sources[0x36]	10266	1			T1	1		T2	1		T11	2
valid_sources[0x37]	10885	1			T1	6		T2	2		T14	7
valid_sources[0x38]	11762	1			T19	2		T14	2		T26	6
valid_sources[0x39]	13034	1			T1	1		T2	1		T12	5
valid_sources[0x3a]	11474	1			T1	1		T2	4		T11	2
valid_sources[0x3b]	10433	1			T1	3		T2	2		T19	1
valid_sources[0x3c]	9865	1			T1	4		T2	1		T19	1
valid_sources[0x3d]	10002	1			T2	1		T19	2		T14	3
valid_sources[0x3e]	22542	1			T1	1		T14	11		T21	14
valid_sources[0x3f]	9202	1			T1	2		T19	2		T14	6
valid_sources[0x40]	9763	1			T1	1		T19	1		T14	3
valid_sources[0x41]	10713	1			T1	2		T2	1		T12	1
valid_sources[0x42]	10205	1			T2	3		T14	2		T26	2
valid_sources[0x43]	10279	1			T1	1		T2	3		T19	1
valid_sources[0x44]	9871	1			T1	1		T2	2		T14	7
valid_sources[0x45]	9688	1			T14	8		T21	10		T15	604
valid_sources[0x46]	23190	1			T1	1		T2	2		T14	4
valid_sources[0x47]	11072	1			T19	1		T14	1		T26	1
valid_sources[0x48]	9906	1			T1	2		T19	3		T14	8
valid_sources[0x49]	10857	1			T1	1		T2	1		T19	2
valid_sources[0x4a]	9831	1			T1	1		T2	4		T14	2
valid_sources[0x4b]	9580	1			T1	5		T2	1		T14	3
valid_sources[0x4c]	12281	1			T2	2		T14	6		T21	19
valid_sources[0x4d]	10709	1			T1	1		T14	5		T21	8
valid_sources[0x4e]	9647	1			T2	2		T19	2		T14	4
valid_sources[0x4f]	11400	1			T2	1		T14	5		T26	2
valid_sources[0x50]	13256	1			T1	3		T2	1		T14	3
valid_sources[0x51]	9812	1			T2	2		T19	2		T14	4
valid_sources[0x52]	32644	1			T1	1		T2	3		T11	1
valid_sources[0x53]	10017	1			T1	1		T2	1		T14	7
valid_sources[0x54]	14240	1			T1	2		T2	1		T14	2
valid_sources[0x55]	10413	1			T1	1		T2	1		T14	4
valid_sources[0x56]	12007	1			T1	1		T2	1		T14	8
valid_sources[0x57]	13863	1			T2	1		T14	6		T21	13
valid_sources[0x58]	10160	1			T1	2		T2	1		T19	2
valid_sources[0x59]	9672	1			T1	4		T2	1		T14	3
valid_sources[0x5a]	9407	1			T1	2		T2	1		T19	2
valid_sources[0x5b]	10172	1			T1	2		T14	5		T21	5
valid_sources[0x5c]	9529	1			T2	2		T14	4		T26	2
valid_sources[0x5d]	9767	1			T1	1		T2	1		T12	1
valid_sources[0x5e]	10315	1			T2	2		T19	4		T14	6
valid_sources[0x5f]	14552	1			T1	3		T2	2		T19	3
valid_sources[0x60]	9991	1			T1	1		T14	4		T21	10
valid_sources[0x61]	9701	1			T1	1		T2	1		T19	1
valid_sources[0x62]	135414	1			T2	3		T19	1		T14	4
valid_sources[0x63]	9829	1			T2	2		T12	2		T14	12
valid_sources[0x64]	9770	1			T1	3		T2	3		T19	5
valid_sources[0x65]	11403	1			T1	1		T2	3		T19	1
valid_sources[0x66]	57249	1			T2	2		T19	1		T14	9
valid_sources[0x67]	10719	1			T1	1		T2	3		T11	3
valid_sources[0x68]	10034	1			T1	1		T2	3		T19	1
valid_sources[0x69]	9763	1			T2	2		T11	2		T14	10
valid_sources[0x6a]	10325	1			T1	2		T2	1		T12	1
valid_sources[0x6b]	10928	1			T1	1		T2	2		T19	1
valid_sources[0x6c]	9837	1			T1	1		T2	1		T12	2
valid_sources[0x6d]	10161	1			T1	2		T2	2		T14	5
valid_sources[0x6e]	128237	1			T1	1		T11	2		T14	4
valid_sources[0x6f]	10193	1			T2	3		T19	1		T14	6
valid_sources[0x70]	11974	1			T1	2		T2	1		T14	6
valid_sources[0x71]	31834	1			T2	2		T14	8		T21	10
valid_sources[0x72]	9701	1			T2	3		T14	4		T21	23
valid_sources[0x73]	11185	1			T1	3		T2	3		T14	2
valid_sources[0x74]	9993	1			T2	5		T19	1		T69	9
valid_sources[0x75]	34502	1			T1	1		T2	1		T19	2
valid_sources[0x76]	9804	1			T1	1		T2	2		T14	2
valid_sources[0x77]	10019	1			T1	2		T2	2		T19	1
valid_sources[0x78]	9769	1			T1	1		T2	1		T19	1
valid_sources[0x79]	9167	1			T1	1		T2	1		T19	2
valid_sources[0x7a]	9493	1			T1	2		T2	2		T19	1
valid_sources[0x7b]	9720	1			T1	3		T2	1		T19	2
valid_sources[0x7c]	9543	1			T1	2		T2	1		T19	1
valid_sources[0x7d]	10049	1			T1	1		T2	2		T19	1
valid_sources[0x7e]	9997	1			T2	2		T19	1		T14	3
valid_sources[0x7f]	11824	1			T1	1		T2	1		T14	3
valid_sources[0x80]	9520	1			T1	4		T11	1		T19	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1771890

1

T1

97

T2

88

T10

107

values[0x0]

all_enables

biggest_size

135432

1

T1

51

T2

79

T9

6

values[0x1]

all_enables

biggest_size

135110

1

T1

53

T2

77

T9

1