Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	95722568	12638	0	0
claim_transition_if_regwen_rd_A	95722568	1465	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95722568	12638	0	0
T15	238275	10	0	0
T22	1565	0	0	0
T23	40899	0	0	0
T25	26517	0	0	0
T45	16635	0	0	0
T52	0	18	0	0
T53	0	1	0	0
T54	36488	0	0	0
T65	26964	0	0	0
T97	0	9	0	0
T98	0	3	0	0
T150	0	3	0	0
T151	0	1	0	0
T152	0	16	0	0
T153	0	16	0	0
T154	0	2	0	0
T155	1187	0	0	0
T156	1117	0	0	0
T157	859	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95722568	1465	0	0
T86	748201	0	0	0
T98	475637	8	0	0
T122	0	32	0	0
T130	0	5	0	0
T151	0	16	0	0
T158	0	8	0	0
T159	0	62	0	0
T160	0	14	0	0
T161	0	4	0	0
T162	0	10	0	0
T163	0	321	0	0
T164	33881	0	0	0
T165	528575	0	0	0
T166	27124	0	0	0
T167	29405	0	0	0
T168	51570	0	0	0
T169	38988	0	0	0
T170	24981	0	0	0
T171	1117	0	0	0