Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1875640	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2099391

1

T1

264

T3

116

T8

624

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3625962	1			T1	249		T3	200		T8	455
values[0x0]	173808	1			T1	112		T3	6		T8	231
values[0x1]	175261	1			T1	105		T3	10		T8	257

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1491092	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2483939

1

T1

300

T3

140

T8

701

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12115	1			T8	8		T11	1		T14	267
valid_sources[0x01]	11659	1			T1	34		T3	1		T8	6
valid_sources[0x02]	14070	1			T8	1		T17	25		T14	342
valid_sources[0x03]	11865	1			T1	2		T8	2		T17	6
valid_sources[0x04]	12651	1			T8	2		T14	230		T53	4
valid_sources[0x05]	13980	1			T3	1		T8	7		T14	247
valid_sources[0x06]	12023	1			T8	4		T14	244		T53	3
valid_sources[0x07]	11979	1			T1	1		T3	1		T8	1
valid_sources[0x08]	16105	1			T3	2		T8	3		T14	341
valid_sources[0x09]	12322	1			T3	2		T8	2		T11	2
valid_sources[0x0a]	12367	1			T8	2		T11	9		T17	18
valid_sources[0x0b]	11945	1			T8	4		T14	295		T53	2
valid_sources[0x0c]	12470	1			T3	1		T8	4		T17	26
valid_sources[0x0d]	12025	1			T8	6		T14	215		T53	4
valid_sources[0x0e]	11885	1			T3	1		T8	4		T17	1
valid_sources[0x0f]	12580	1			T8	1		T14	345		T53	3
valid_sources[0x10]	13441	1			T8	2		T14	263		T53	1
valid_sources[0x11]	15118	1			T1	4		T3	2		T8	6
valid_sources[0x12]	13817	1			T8	7		T11	3		T17	5
valid_sources[0x13]	12141	1			T3	1		T8	5		T11	1
valid_sources[0x14]	12123	1			T1	1		T8	5		T11	3
valid_sources[0x15]	12379	1			T8	4		T14	226		T53	5
valid_sources[0x16]	12176	1			T8	5		T17	3		T14	238
valid_sources[0x17]	25321	1			T8	2		T17	14		T14	234
valid_sources[0x18]	14863	1			T3	5		T8	1		T11	2
valid_sources[0x19]	14563	1			T3	1		T8	3		T17	40
valid_sources[0x1a]	12710	1			T3	1		T8	2		T11	4
valid_sources[0x1b]	12009	1			T1	6		T3	5		T8	5
valid_sources[0x1c]	12276	1			T8	4		T11	4		T17	9
valid_sources[0x1d]	12145	1			T1	1		T8	4		T11	8
valid_sources[0x1e]	12257	1			T1	9		T8	1		T17	6
valid_sources[0x1f]	13463	1			T3	3		T8	2		T17	2
valid_sources[0x20]	11971	1			T1	19		T3	2		T8	3
valid_sources[0x21]	11881	1			T8	6		T14	314		T53	2
valid_sources[0x22]	13573	1			T8	6		T11	9		T17	13
valid_sources[0x23]	12108	1			T3	1		T8	2		T17	17
valid_sources[0x24]	12246	1			T8	4		T17	20		T14	258
valid_sources[0x25]	12706	1			T3	1		T8	7		T14	321
valid_sources[0x26]	12361	1			T8	1		T17	8		T14	232
valid_sources[0x27]	12106	1			T3	1		T8	6		T11	14
valid_sources[0x28]	12326	1			T3	2		T8	10		T17	1
valid_sources[0x29]	12398	1			T8	2		T17	1		T14	318
valid_sources[0x2a]	13163	1			T3	2		T8	7		T11	3
valid_sources[0x2b]	12258	1			T3	1		T8	3		T17	32
valid_sources[0x2c]	12172	1			T3	2		T8	5		T11	3
valid_sources[0x2d]	11799	1			T8	6		T11	2		T17	6
valid_sources[0x2e]	11636	1			T8	9		T14	180		T53	2
valid_sources[0x2f]	12521	1			T8	5		T14	308		T53	4
valid_sources[0x30]	13887	1			T8	3		T17	34		T14	278
valid_sources[0x31]	12533	1			T3	2		T8	4		T11	4
valid_sources[0x32]	12405	1			T8	2		T17	13		T14	291
valid_sources[0x33]	12498	1			T8	8		T14	231		T53	7
valid_sources[0x34]	12044	1			T3	3		T8	4		T17	2
valid_sources[0x35]	13950	1			T3	2		T8	4		T14	246
valid_sources[0x36]	12260	1			T3	4		T8	2		T17	2
valid_sources[0x37]	12309	1			T8	7		T17	16		T14	264
valid_sources[0x38]	88161	1			T3	1		T8	4		T11	4
valid_sources[0x39]	13214	1			T8	2		T17	49		T14	355
valid_sources[0x3a]	11592	1			T8	4		T14	216		T53	5
valid_sources[0x3b]	13350	1			T8	6		T14	254		T53	5
valid_sources[0x3c]	12330	1			T8	4		T14	355		T53	5
valid_sources[0x3d]	30166	1			T8	6		T11	7		T17	1
valid_sources[0x3e]	13585	1			T8	5		T14	265		T53	7
valid_sources[0x3f]	13581	1			T1	9		T8	4		T11	20
valid_sources[0x40]	12456	1			T1	2		T8	7		T17	2
valid_sources[0x41]	14522	1			T8	8		T14	301		T53	7
valid_sources[0x42]	14014	1			T1	8		T8	5		T11	1
valid_sources[0x43]	12443	1			T8	1		T17	1		T14	286
valid_sources[0x44]	13732	1			T8	2		T17	10		T14	242
valid_sources[0x45]	12794	1			T3	7		T8	4		T14	244
valid_sources[0x46]	12240	1			T8	2		T11	4		T17	5
valid_sources[0x47]	11984	1			T3	2		T8	6		T17	5
valid_sources[0x48]	12952	1			T8	3		T17	15		T14	357
valid_sources[0x49]	12143	1			T3	3		T8	2		T14	247
valid_sources[0x4a]	12710	1			T1	1		T3	2		T8	1
valid_sources[0x4b]	13727	1			T1	2		T3	1		T8	1
valid_sources[0x4c]	12227	1			T8	2		T11	3		T17	1
valid_sources[0x4d]	22720	1			T1	1		T8	3		T17	2
valid_sources[0x4e]	12032	1			T3	1		T8	3		T11	3
valid_sources[0x4f]	12376	1			T1	40		T8	3		T17	78
valid_sources[0x50]	11916	1			T8	4		T17	11		T14	163
valid_sources[0x51]	12595	1			T8	10		T17	4		T14	246
valid_sources[0x52]	12313	1			T3	3		T8	9		T11	1
valid_sources[0x53]	14339	1			T3	1		T8	6		T17	14
valid_sources[0x54]	25321	1			T8	1		T11	2		T17	18
valid_sources[0x55]	13420	1			T1	25		T8	1		T17	20
valid_sources[0x56]	12002	1			T8	4		T14	437		T53	5
valid_sources[0x57]	12392	1			T3	1		T8	2		T14	205
valid_sources[0x58]	12096	1			T3	3		T8	6		T14	235
valid_sources[0x59]	12593	1			T1	1		T3	3		T8	3
valid_sources[0x5a]	13671	1			T8	5		T14	308		T53	8
valid_sources[0x5b]	12337	1			T1	1		T3	2		T8	4
valid_sources[0x5c]	12025	1			T3	1		T8	4		T11	6
valid_sources[0x5d]	12808	1			T8	6		T17	29		T14	317
valid_sources[0x5e]	14594	1			T3	5		T8	6		T10	1792
valid_sources[0x5f]	12335	1			T8	3		T17	4		T14	294
valid_sources[0x60]	12983	1			T3	4		T8	3		T11	2
valid_sources[0x61]	12045	1			T3	1		T8	1		T11	1
valid_sources[0x62]	11780	1			T8	2		T11	2		T17	53
valid_sources[0x63]	12267	1			T3	3		T17	6		T14	286
valid_sources[0x64]	12145	1			T3	1		T8	4		T11	1
valid_sources[0x65]	12522	1			T8	6		T17	11		T14	447
valid_sources[0x66]	12367	1			T8	5		T17	4		T14	321
valid_sources[0x67]	12489	1			T8	8		T14	252		T53	4
valid_sources[0x68]	12109	1			T8	1		T14	281		T53	4
valid_sources[0x69]	12734	1			T3	1		T8	5		T17	13
valid_sources[0x6a]	11963	1			T8	3		T17	25		T14	294
valid_sources[0x6b]	13546	1			T1	11		T8	4		T11	5
valid_sources[0x6c]	12129	1			T8	4		T17	11		T14	276
valid_sources[0x6d]	137488	1			T8	5		T11	8		T14	283
valid_sources[0x6e]	12083	1			T3	2		T8	8		T17	50
valid_sources[0x6f]	12849	1			T8	5		T11	2		T17	2
valid_sources[0x70]	12351	1			T3	2		T8	1		T11	1
valid_sources[0x71]	12781	1			T3	1		T8	5		T11	2
valid_sources[0x72]	12371	1			T8	2		T11	12		T14	361
valid_sources[0x73]	50656	1			T8	4		T14	221		T53	3
valid_sources[0x74]	11628	1			T3	3		T8	2		T17	8
valid_sources[0x75]	55585	1			T8	3		T14	196		T53	2
valid_sources[0x76]	17317	1			T8	6		T11	4		T14	296
valid_sources[0x77]	12325	1			T8	3		T11	4		T14	220
valid_sources[0x78]	11964	1			T1	8		T8	2		T14	204
valid_sources[0x79]	11966	1			T8	3		T14	244		T53	4
valid_sources[0x7a]	12037	1			T3	1		T8	4		T11	4
valid_sources[0x7b]	12352	1			T8	5		T17	2		T14	293
valid_sources[0x7c]	11915	1			T8	11		T14	246		T53	8
valid_sources[0x7d]	47237	1			T3	1		T8	2		T11	9
valid_sources[0x7e]	12052	1			T1	11		T8	6		T14	336
valid_sources[0x7f]	13591	1			T1	11		T3	1		T8	3
valid_sources[0x80]	12160	1			T8	4		T17	6		T14	261

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1798272

1

T1

128

T3

103

T8

202

values[0x0]

all_enables

biggest_size

150764

1

T1

65

T3

5

T8

198

values[0x1]

all_enables

biggest_size

150355

1

T1

71

T3

8

T8

224