Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	114107490	15512	0	0
claim_transition_if_regwen_rd_A	114107490	1124	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114107490	15512	0	0
T5	46871	0	0	0
T6	11480	0	0	0
T14	646911	8	0	0
T15	67982	0	0	0
T18	1619	0	0	0
T20	87917	0	0	0
T21	0	1	0	0
T35	0	1	0	0
T37	12248	0	0	0
T49	0	3	0	0
T53	30805	0	0	0
T63	1613	0	0	0
T64	1349	0	0	0
T99	0	2	0	0
T137	0	1	0	0
T138	0	11	0	0
T139	0	3	0	0
T140	0	8	0	0
T141	0	2	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114107490	1124	0	0
T39	0	8	0	0
T82	0	1	0	0
T109	0	7	0	0
T121	0	21	0	0
T139	101546	4	0	0
T140	158836	0	0	0
T142	0	10	0	0
T143	0	11	0	0
T144	0	39	0	0
T145	0	8	0	0
T146	0	31	0	0
T147	36856	0	0	0
T148	42048	0	0	0
T149	22359	0	0	0
T150	27405	0	0	0
T151	39343	0	0	0
T152	1063	0	0	0
T153	26270	0	0	0
T154	7018	0	0	0