Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2189391	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2420977

1

T1

6

T2

8

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4248107	1			T1	9		T3	35		T4	45739
values[0x0]	180147	1			T1	4		T2	15		T3	7
values[0x1]	182114	1			T1	4		T2	14		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1740203	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2870165

1

T1

9

T2

10

T3

17

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13463	1			T5	1		T17	5		T16	20
valid_sources[0x01]	17123	1			T11	1		T7	1		T17	4
valid_sources[0x02]	14073	1			T5	1		T7	2		T17	7
valid_sources[0x03]	19964	1			T11	3		T7	1		T21	14
valid_sources[0x04]	13418	1			T1	1		T7	3		T17	4
valid_sources[0x05]	13423	1			T11	1		T5	2		T7	5
valid_sources[0x06]	12594	1			T5	2		T17	7		T16	9
valid_sources[0x07]	12733	1			T7	2		T17	10		T16	4
valid_sources[0x08]	18746	1			T7	4		T17	7		T16	3
valid_sources[0x09]	13083	1			T5	1		T7	6		T17	4
valid_sources[0x0a]	13386	1			T5	10		T7	3		T17	5
valid_sources[0x0b]	13180	1			T21	2		T17	8		T16	3
valid_sources[0x0c]	12985	1			T11	2		T7	2		T17	3
valid_sources[0x0d]	12700	1			T7	1		T21	1		T17	4
valid_sources[0x0e]	12869	1			T7	3		T17	7		T16	9
valid_sources[0x0f]	13747	1			T11	1		T5	1		T21	7
valid_sources[0x10]	12986	1			T11	2		T5	6		T7	2
valid_sources[0x11]	17110	1			T2	3		T11	1		T7	2
valid_sources[0x12]	14122	1			T5	11		T7	3		T21	13
valid_sources[0x13]	12372	1			T5	1		T7	2		T21	4
valid_sources[0x14]	13631	1			T3	2		T11	1		T7	2
valid_sources[0x15]	12879	1			T5	1		T7	3		T21	9
valid_sources[0x16]	13365	1			T5	3		T7	5		T17	1
valid_sources[0x17]	13053	1			T7	7		T17	7		T16	6
valid_sources[0x18]	12780	1			T7	3		T17	10		T16	14
valid_sources[0x19]	13153	1			T11	2		T7	1		T16	4
valid_sources[0x1a]	13325	1			T5	3		T7	2		T17	5
valid_sources[0x1b]	13502	1			T11	1		T17	8		T16	7
valid_sources[0x1c]	22002	1			T5	4		T7	1		T17	6
valid_sources[0x1d]	12967	1			T3	1		T11	3		T5	1
valid_sources[0x1e]	12611	1			T7	8		T21	22		T17	6
valid_sources[0x1f]	27356	1			T3	2		T11	2		T5	5
valid_sources[0x20]	13221	1			T3	2		T7	2		T17	10
valid_sources[0x21]	14820	1			T7	2		T21	20		T17	4
valid_sources[0x22]	77273	1			T4	47251		T11	1		T21	8
valid_sources[0x23]	12846	1			T11	2		T5	2		T7	1
valid_sources[0x24]	13144	1			T11	2		T5	2		T21	1
valid_sources[0x25]	13498	1			T11	3		T7	1		T21	5
valid_sources[0x26]	12882	1			T7	3		T17	3		T16	8
valid_sources[0x27]	12857	1			T14	1		T7	5		T17	4
valid_sources[0x28]	12669	1			T3	1		T5	2		T7	2
valid_sources[0x29]	13372	1			T7	2		T21	1		T17	3
valid_sources[0x2a]	13229	1			T5	5		T21	1		T17	1
valid_sources[0x2b]	14928	1			T11	1		T7	2		T17	11
valid_sources[0x2c]	13343	1			T7	4		T21	10		T17	5
valid_sources[0x2d]	12803	1			T11	1		T5	3		T7	1
valid_sources[0x2e]	12836	1			T4	17		T5	4		T7	2
valid_sources[0x2f]	14331	1			T5	7		T7	1		T21	3
valid_sources[0x30]	12901	1			T11	1		T7	6		T17	4
valid_sources[0x31]	12785	1			T3	1		T5	4		T7	1
valid_sources[0x32]	13267	1			T11	2		T7	3		T17	4
valid_sources[0x33]	12864	1			T7	2		T21	13		T17	6
valid_sources[0x34]	12307	1			T5	3		T7	1		T17	6
valid_sources[0x35]	18608	1			T11	1		T7	5		T17	6
valid_sources[0x36]	12464	1			T11	1		T5	1		T7	3
valid_sources[0x37]	12592	1			T5	5		T7	1		T21	7
valid_sources[0x38]	13578	1			T7	1		T21	5		T17	6
valid_sources[0x39]	13186	1			T7	1		T17	2		T16	7
valid_sources[0x3a]	13093	1			T7	1		T17	3		T16	5
valid_sources[0x3b]	12670	1			T7	3		T17	2		T16	14
valid_sources[0x3c]	12876	1			T7	3		T21	18		T17	2
valid_sources[0x3d]	13131	1			T5	1		T7	6		T21	12
valid_sources[0x3e]	13539	1			T7	3		T17	2		T16	5
valid_sources[0x3f]	16641	1			T2	6		T11	1		T5	7
valid_sources[0x40]	76884	1			T3	1		T7	1		T21	2
valid_sources[0x41]	13212	1			T11	1		T5	2		T7	2
valid_sources[0x42]	13107	1			T11	3		T5	3		T7	4
valid_sources[0x43]	12902	1			T1	1		T5	15		T7	2
valid_sources[0x44]	13247	1			T3	1		T11	1		T5	1
valid_sources[0x45]	46131	1			T3	1		T11	5		T7	2
valid_sources[0x46]	56412	1			T11	4		T5	1		T7	1
valid_sources[0x47]	13140	1			T5	1		T7	3		T21	1
valid_sources[0x48]	13875	1			T5	6		T7	4		T17	5
valid_sources[0x49]	12967	1			T17	2		T16	6		T34	2
valid_sources[0x4a]	14557	1			T11	1		T5	1		T7	3
valid_sources[0x4b]	20197	1			T5	3		T7	2		T17	5
valid_sources[0x4c]	13200	1			T11	3		T7	2		T21	4
valid_sources[0x4d]	55085	1			T11	1		T5	1		T7	1
valid_sources[0x4e]	13022	1			T7	5		T17	9		T16	9
valid_sources[0x4f]	13215	1			T1	1		T7	1		T17	7
valid_sources[0x50]	13119	1			T11	2		T5	5		T7	4
valid_sources[0x51]	12764	1			T5	2		T7	3		T17	6
valid_sources[0x52]	12762	1			T11	1		T7	1		T17	4
valid_sources[0x53]	13226	1			T11	3		T7	4		T21	4
valid_sources[0x54]	12642	1			T11	1		T7	2		T17	3
valid_sources[0x55]	12738	1			T5	2		T7	3		T17	6
valid_sources[0x56]	32901	1			T7	3		T21	4		T17	9
valid_sources[0x57]	40833	1			T2	7		T5	1		T7	3
valid_sources[0x58]	13297	1			T7	3		T17	6		T16	13
valid_sources[0x59]	15603	1			T7	2		T21	12		T17	7
valid_sources[0x5a]	13961	1			T7	7		T17	7		T16	5
valid_sources[0x5b]	16530	1			T5	1		T7	3		T17	3
valid_sources[0x5c]	16977	1			T7	5		T21	6		T17	5
valid_sources[0x5d]	13501	1			T7	2		T21	13		T17	6
valid_sources[0x5e]	51171	1			T7	4		T21	3		T17	6
valid_sources[0x5f]	16937	1			T5	1		T7	2		T21	7
valid_sources[0x60]	13631	1			T11	5		T5	2		T7	3
valid_sources[0x61]	12896	1			T11	1		T7	6		T17	3
valid_sources[0x62]	13443	1			T11	1		T14	1		T7	2
valid_sources[0x63]	13829	1			T11	3		T7	2		T17	4
valid_sources[0x64]	13322	1			T11	1		T7	5		T17	2
valid_sources[0x65]	13068	1			T11	2		T7	4		T17	5
valid_sources[0x66]	33719	1			T11	1		T17	3		T16	4
valid_sources[0x67]	16465	1			T13	3106		T7	7		T21	12
valid_sources[0x68]	13031	1			T3	2		T7	2		T21	28
valid_sources[0x69]	13450	1			T7	1		T17	4		T16	8
valid_sources[0x6a]	56175	1			T5	2		T7	2		T17	2
valid_sources[0x6b]	13710	1			T21	22		T17	8		T16	5
valid_sources[0x6c]	13057	1			T4	17		T11	1		T5	2
valid_sources[0x6d]	13085	1			T11	1		T7	6		T17	3
valid_sources[0x6e]	61339	1			T1	1		T7	1		T21	7
valid_sources[0x6f]	14486	1			T4	17		T5	3		T7	1
valid_sources[0x70]	73276	1			T1	1		T17	7		T16	9
valid_sources[0x71]	13042	1			T5	1		T7	2		T21	9
valid_sources[0x72]	13248	1			T3	1		T5	7		T7	4
valid_sources[0x73]	12667	1			T7	3		T17	8		T68	10
valid_sources[0x74]	18079	1			T5	10		T7	4		T21	2
valid_sources[0x75]	77241	1			T7	4		T17	4		T16	6
valid_sources[0x76]	13434	1			T5	2		T21	8		T17	8
valid_sources[0x77]	15312	1			T5	1		T7	1		T17	3
valid_sources[0x78]	12773	1			T5	9		T21	2		T17	7
valid_sources[0x79]	13264	1			T3	2		T11	2		T7	2
valid_sources[0x7a]	38604	1			T11	1		T5	1		T7	2
valid_sources[0x7b]	34537	1			T7	2		T17	3		T16	15
valid_sources[0x7c]	12722	1			T7	2		T17	4		T16	9
valid_sources[0x7d]	13786	1			T5	1		T7	6		T17	2
valid_sources[0x7e]	13298	1			T1	1		T7	3		T17	7
valid_sources[0x7f]	25709	1			T4	17		T7	2		T17	4
valid_sources[0x80]	12765	1			T5	1		T7	3		T17	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

2108610

1

T4

22741

T5

93

T13

1244

values[0x0]

all_enables

biggest_size

156179

1

T1

3

T2

6

T3

5

values[0x1]

all_enables

biggest_size

156188

1

T1

3

T2

2

T3

1