Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	100.00	82.35	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	122403502	16365	0	0
claim_transition_if_regwen_rd_A	122403502	1405	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122403502	16365	0	0
T8	19686	0	0	0
T15	259254	3	0	0
T22	118227	0	0	0
T23	65922	0	0	0
T34	2806	0	0	0
T38	0	6	0	0
T48	24381	0	0	0
T58	0	5	0	0
T63	23844	0	0	0
T68	23420	0	0	0
T90	1694	0	0	0
T91	0	16	0	0
T92	0	1	0	0
T123	0	2	0	0
T162	0	17	0	0
T163	0	4	0	0
T164	0	7	0	0
T165	0	7	0	0
T166	31831	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	122403502	1405	0	0
T8	19686	0	0	0
T15	259254	5	0	0
T22	118227	0	0	0
T23	65922	0	0	0
T34	2806	0	0	0
T48	24381	0	0	0
T63	23844	0	0	0
T68	23420	0	0	0
T90	1694	0	0	0
T123	0	5	0	0
T125	0	38	0	0
T126	0	40	0	0
T144	0	24	0	0
T163	0	2	0	0
T166	31831	0	0	0
T167	0	1	0	0
T168	0	22	0	0
T169	0	16	0	0
T170	0	7	0	0