Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1860318	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2083240

1

T1

218

T2

2439

T3

2034

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3596621	1			T1	189		T2	2415		T3	3175
values[0x0]	173041	1			T1	82		T2	745		T3	282
values[0x1]	173896	1			T1	78		T2	711		T3	262

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1478797	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2464761

1

T1

252

T2

2781

T3

2368

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	24605	1			T2	12		T3	6		T9	40
valid_sources[0x01]	12954	1			T2	9		T3	16		T5	417
valid_sources[0x02]	12575	1			T2	14		T3	12		T5	381
valid_sources[0x03]	12666	1			T1	3		T2	12		T3	12
valid_sources[0x04]	12603	1			T2	16		T3	14		T5	356
valid_sources[0x05]	12801	1			T2	10		T3	12		T5	386
valid_sources[0x06]	12965	1			T2	12		T3	6		T5	385
valid_sources[0x07]	13490	1			T2	11		T3	14		T5	408
valid_sources[0x08]	14209	1			T2	15		T3	15		T5	359
valid_sources[0x09]	13426	1			T1	4		T2	16		T3	16
valid_sources[0x0a]	12720	1			T2	27		T3	20		T5	410
valid_sources[0x0b]	12837	1			T2	18		T3	15		T5	389
valid_sources[0x0c]	12683	1			T2	15		T3	12		T5	347
valid_sources[0x0d]	12534	1			T1	2		T2	16		T3	13
valid_sources[0x0e]	13081	1			T1	1		T2	13		T3	16
valid_sources[0x0f]	12246	1			T2	14		T3	10		T5	409
valid_sources[0x10]	12126	1			T1	1		T2	8		T3	17
valid_sources[0x11]	15545	1			T1	1		T2	14		T3	14
valid_sources[0x12]	12286	1			T1	1		T2	17		T3	19
valid_sources[0x13]	35837	1			T1	2		T2	14		T3	15
valid_sources[0x14]	17439	1			T1	1		T2	24		T3	19
valid_sources[0x15]	13923	1			T2	11		T3	13		T5	396
valid_sources[0x16]	16545	1			T2	15		T3	13		T5	410
valid_sources[0x17]	12934	1			T1	2		T2	15		T3	11
valid_sources[0x18]	12772	1			T2	16		T3	13		T5	405
valid_sources[0x19]	12994	1			T2	13		T3	12		T5	380
valid_sources[0x1a]	12935	1			T2	13		T3	17		T9	8
valid_sources[0x1b]	12885	1			T2	25		T3	19		T5	408
valid_sources[0x1c]	12514	1			T2	11		T3	21		T5	388
valid_sources[0x1d]	12199	1			T1	2		T2	15		T3	11
valid_sources[0x1e]	12646	1			T1	3		T2	23		T3	22
valid_sources[0x1f]	12429	1			T2	19		T3	18		T9	19
valid_sources[0x20]	12926	1			T1	2		T2	13		T3	15
valid_sources[0x21]	12518	1			T1	3		T2	17		T3	14
valid_sources[0x22]	12465	1			T2	10		T3	17		T5	392
valid_sources[0x23]	14505	1			T2	23		T3	18		T5	409
valid_sources[0x24]	12273	1			T1	3		T2	14		T3	19
valid_sources[0x25]	16476	1			T2	13		T3	12		T5	380
valid_sources[0x26]	13599	1			T2	13		T3	11		T5	373
valid_sources[0x27]	19794	1			T1	1		T2	12		T3	11
valid_sources[0x28]	12931	1			T1	3		T2	11		T3	20
valid_sources[0x29]	14472	1			T2	11		T3	16		T5	436
valid_sources[0x2a]	12797	1			T1	1		T2	17		T3	22
valid_sources[0x2b]	12223	1			T2	14		T3	15		T5	423
valid_sources[0x2c]	16931	1			T2	20		T3	14		T5	385
valid_sources[0x2d]	12429	1			T2	13		T3	12		T5	385
valid_sources[0x2e]	13157	1			T2	18		T3	19		T5	392
valid_sources[0x2f]	12282	1			T2	12		T3	7		T5	399
valid_sources[0x30]	12471	1			T2	9		T3	9		T5	398
valid_sources[0x31]	28452	1			T1	6		T2	15		T3	17
valid_sources[0x32]	23273	1			T2	23		T3	13		T5	417
valid_sources[0x33]	13090	1			T2	9		T3	16		T5	392
valid_sources[0x34]	13845	1			T2	14		T3	13		T5	405
valid_sources[0x35]	12945	1			T2	15		T3	17		T5	384
valid_sources[0x36]	12778	1			T1	4		T2	11		T3	15
valid_sources[0x37]	23616	1			T2	16		T3	14		T5	386
valid_sources[0x38]	12499	1			T1	3		T2	13		T3	12
valid_sources[0x39]	16744	1			T2	25		T3	14		T5	368
valid_sources[0x3a]	13754	1			T2	10		T3	16		T10	1629
valid_sources[0x3b]	12493	1			T1	4		T2	12		T3	23
valid_sources[0x3c]	12520	1			T1	6		T2	19		T3	9
valid_sources[0x3d]	13215	1			T1	2		T2	24		T3	14
valid_sources[0x3e]	12673	1			T2	20		T3	19		T5	380
valid_sources[0x3f]	14245	1			T1	5		T2	17		T3	9
valid_sources[0x40]	12862	1			T1	11		T2	11		T3	17
valid_sources[0x41]	12807	1			T2	14		T3	6		T5	402
valid_sources[0x42]	12357	1			T2	21		T3	15		T5	371
valid_sources[0x43]	11989	1			T2	15		T3	10		T5	390
valid_sources[0x44]	15005	1			T1	6		T2	10		T3	13
valid_sources[0x45]	19457	1			T2	13		T3	17		T5	396
valid_sources[0x46]	15953	1			T1	1		T2	11		T3	13
valid_sources[0x47]	12722	1			T2	17		T3	16		T5	415
valid_sources[0x48]	13982	1			T1	2		T2	18		T3	13
valid_sources[0x49]	13859	1			T2	13		T3	15		T5	365
valid_sources[0x4a]	13026	1			T1	2		T2	18		T3	14
valid_sources[0x4b]	12486	1			T2	13		T3	13		T5	369
valid_sources[0x4c]	13524	1			T2	15		T3	22		T5	401
valid_sources[0x4d]	12208	1			T2	21		T3	15		T5	395
valid_sources[0x4e]	13100	1			T2	10		T3	21		T5	417
valid_sources[0x4f]	12841	1			T1	4		T2	20		T3	15
valid_sources[0x50]	13587	1			T2	12		T3	18		T5	377
valid_sources[0x51]	12470	1			T2	14		T3	13		T5	357
valid_sources[0x52]	12743	1			T1	2		T2	21		T3	15
valid_sources[0x53]	12226	1			T2	14		T3	19		T9	26
valid_sources[0x54]	12544	1			T2	16		T3	14		T5	386
valid_sources[0x55]	12043	1			T1	4		T2	18		T3	10
valid_sources[0x56]	12632	1			T2	14		T3	9		T5	363
valid_sources[0x57]	14975	1			T2	7		T3	16		T5	390
valid_sources[0x58]	12889	1			T1	5		T2	18		T3	23
valid_sources[0x59]	13064	1			T2	24		T3	12		T5	377
valid_sources[0x5a]	12611	1			T2	26		T3	21		T5	382
valid_sources[0x5b]	13471	1			T2	12		T3	12		T9	30
valid_sources[0x5c]	13029	1			T1	5		T2	14		T3	10
valid_sources[0x5d]	12777	1			T2	18		T3	16		T5	380
valid_sources[0x5e]	12867	1			T2	17		T3	14		T5	403
valid_sources[0x5f]	16056	1			T2	14		T3	13		T5	402
valid_sources[0x60]	13200	1			T1	4		T2	6		T3	11
valid_sources[0x61]	12562	1			T2	15		T3	10		T5	409
valid_sources[0x62]	12388	1			T2	11		T3	8		T5	369
valid_sources[0x63]	12740	1			T2	16		T3	14		T5	426
valid_sources[0x64]	12773	1			T2	18		T3	19		T5	433
valid_sources[0x65]	12682	1			T2	18		T3	14		T5	350
valid_sources[0x66]	13317	1			T1	1		T2	16		T3	17
valid_sources[0x67]	14078	1			T2	8		T3	21		T5	391
valid_sources[0x68]	13510	1			T1	1		T2	18		T3	15
valid_sources[0x69]	13896	1			T1	1		T2	14		T3	15
valid_sources[0x6a]	12027	1			T2	18		T3	13		T5	374
valid_sources[0x6b]	13430	1			T2	15		T3	18		T9	35
valid_sources[0x6c]	12971	1			T1	1		T2	16		T3	11
valid_sources[0x6d]	13578	1			T2	20		T3	11		T5	370
valid_sources[0x6e]	12736	1			T1	3		T2	12		T3	18
valid_sources[0x6f]	12454	1			T1	2		T2	16		T3	15
valid_sources[0x70]	12921	1			T1	1		T2	14		T3	12
valid_sources[0x71]	12548	1			T1	3		T2	12		T3	13
valid_sources[0x72]	12761	1			T1	1		T2	14		T3	15
valid_sources[0x73]	12362	1			T1	6		T2	18		T3	15
valid_sources[0x74]	14613	1			T2	13		T3	13		T5	424
valid_sources[0x75]	12475	1			T2	16		T3	14		T5	372
valid_sources[0x76]	13472	1			T2	16		T3	7		T5	366
valid_sources[0x77]	12221	1			T2	9		T3	23		T5	382
valid_sources[0x78]	12653	1			T2	25		T3	14		T5	356
valid_sources[0x79]	12391	1			T1	7		T2	14		T3	10
valid_sources[0x7a]	12964	1			T2	25		T3	16		T5	384
valid_sources[0x7b]	38670	1			T2	15		T3	10		T5	394
valid_sources[0x7c]	13290	1			T2	7		T3	18		T5	397
valid_sources[0x7d]	12286	1			T2	19		T3	11		T5	391
valid_sources[0x7e]	12980	1			T2	10		T3	10		T5	402
valid_sources[0x7f]	36490	1			T1	2		T2	13		T3	16
valid_sources[0x80]	12606	1			T1	1		T2	19		T3	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1784224

1

T1

82

T2

1175

T3

1559

values[0x0]

all_enables

biggest_size

149990

1

T1

72

T2

653

T3

244

values[0x1]

all_enables

biggest_size

149026

1

T1

64

T2

611

T3

231