SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
94.57 | 100.00 | 82.35 | 99.89 | 100.00 | 90.62 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.62 | 98.17 | 93.06 | 100.00 | 98.53 | 93.33 | u_lc_ctrl_fsm |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.62 | 98.17 | 93.06 | 100.00 | 98.53 | 93.33 | u_lc_ctrl_fsm |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.62 | 98.17 | 93.06 | 100.00 | 98.53 | 93.33 | u_lc_ctrl_fsm |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.62 | 98.17 | 93.06 | 100.00 | 98.53 | 93.33 | u_lc_ctrl_fsm |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.62 | 98.17 | 93.06 | 100.00 | 98.53 | 93.33 | u_lc_ctrl_fsm |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.62 | 98.17 | 93.06 | 100.00 | 98.53 | 93.33 | u_lc_ctrl_fsm |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 4 | 4 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 4 | 4 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 9 | 9 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 8 | 8 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 5705 | 5705 | 0 | 0 |
OutputsKnown_A | 760976730 | 732206326 | 0 | 0 |
gen_flops.OutputDelay_A | 326025883 | 313227706 | 0 | 7233 |
gen_no_flops.OutputDelay_A | 434950847 | 418485087 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 5705 | 5705 | 0 | 0 |
T1 | 7 | 7 | 0 | 0 |
T2 | 7 | 7 | 0 | 0 |
T3 | 7 | 7 | 0 | 0 |
T4 | 7 | 7 | 0 | 0 |
T5 | 7 | 7 | 0 | 0 |
T9 | 7 | 7 | 0 | 0 |
T10 | 7 | 7 | 0 | 0 |
T11 | 7 | 7 | 0 | 0 |
T12 | 7 | 7 | 0 | 0 |
T13 | 7 | 7 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 760976730 | 732206326 | 0 | 0 |
T1 | 50680 | 39942 | 0 | 0 |
T2 | 4720933 | 4513628 | 0 | 0 |
T3 | 421316 | 385329 | 0 | 0 |
T4 | 65597 | 64722 | 0 | 0 |
T5 | 811783 | 771981 | 0 | 0 |
T9 | 55615 | 47670 | 0 | 0 |
T10 | 185262 | 137949 | 0 | 0 |
T11 | 40439 | 39823 | 0 | 0 |
T12 | 45570 | 38934 | 0 | 0 |
T13 | 183197 | 148736 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 326025883 | 313227706 | 0 | 7233 |
T1 | 21720 | 16929 | 0 | 9 |
T2 | 2023257 | 1930893 | 0 | 9 |
T3 | 180564 | 164520 | 0 | 9 |
T4 | 28113 | 27720 | 0 | 9 |
T5 | 347907 | 330165 | 0 | 9 |
T9 | 23835 | 20295 | 0 | 9 |
T10 | 79398 | 58338 | 0 | 9 |
T11 | 17331 | 17058 | 0 | 9 |
T12 | 19530 | 16578 | 0 | 9 |
T13 | 78513 | 63177 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 434950847 | 418485087 | 0 | 0 |
T1 | 28960 | 22824 | 0 | 0 |
T2 | 2697676 | 2579216 | 0 | 0 |
T3 | 240752 | 220188 | 0 | 0 |
T4 | 37484 | 36984 | 0 | 0 |
T5 | 463876 | 441132 | 0 | 0 |
T9 | 31780 | 27240 | 0 | 0 |
T10 | 105864 | 78828 | 0 | 0 |
T11 | 23108 | 22756 | 0 | 0 |
T12 | 26040 | 22248 | 0 | 0 |
T13 | 104684 | 84992 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 815 | 815 | 0 | 0 |
OutputsKnown_A | 108997612 | 104838311 | 0 | 0 |
gen_no_flops.OutputDelay_A | 108997612 | 104838311 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 815 | 815 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 108997612 | 104838311 | 0 | 0 |
T1 | 7240 | 5706 | 0 | 0 |
T2 | 674419 | 644804 | 0 | 0 |
T3 | 60188 | 55047 | 0 | 0 |
T4 | 9371 | 9246 | 0 | 0 |
T5 | 115969 | 110283 | 0 | 0 |
T9 | 7945 | 6810 | 0 | 0 |
T10 | 26466 | 19707 | 0 | 0 |
T11 | 5777 | 5689 | 0 | 0 |
T12 | 6510 | 5562 | 0 | 0 |
T13 | 26171 | 21248 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 108997612 | 104838311 | 0 | 0 |
T1 | 7240 | 5706 | 0 | 0 |
T2 | 674419 | 644804 | 0 | 0 |
T3 | 60188 | 55047 | 0 | 0 |
T4 | 9371 | 9246 | 0 | 0 |
T5 | 115969 | 110283 | 0 | 0 |
T9 | 7945 | 6810 | 0 | 0 |
T10 | 26466 | 19707 | 0 | 0 |
T11 | 5777 | 5689 | 0 | 0 |
T12 | 6510 | 5562 | 0 | 0 |
T13 | 26171 | 21248 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 815 | 815 | 0 | 0 |
OutputsKnown_A | 108707249 | 104606407 | 0 | 0 |
gen_flops.OutputDelay_A | 108707249 | 104441918 | 0 | 2415 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 815 | 815 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 108707249 | 104606407 | 0 | 0 |
T1 | 7240 | 5706 | 0 | 0 |
T2 | 674419 | 644804 | 0 | 0 |
T3 | 60188 | 55047 | 0 | 0 |
T4 | 9371 | 9246 | 0 | 0 |
T5 | 115969 | 110283 | 0 | 0 |
T9 | 7945 | 6810 | 0 | 0 |
T10 | 26466 | 19707 | 0 | 0 |
T11 | 5777 | 5689 | 0 | 0 |
T12 | 6510 | 5562 | 0 | 0 |
T13 | 26171 | 21248 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 108707249 | 104441918 | 0 | 2415 |
T1 | 7240 | 5643 | 0 | 3 |
T2 | 674419 | 643631 | 0 | 3 |
T3 | 60188 | 54840 | 0 | 3 |
T4 | 9371 | 9240 | 0 | 3 |
T5 | 115969 | 110055 | 0 | 3 |
T9 | 7945 | 6765 | 0 | 3 |
T10 | 26466 | 19446 | 0 | 3 |
T11 | 5777 | 5686 | 0 | 3 |
T12 | 6510 | 5526 | 0 | 3 |
T13 | 26171 | 21059 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 815 | 815 | 0 | 0 |
OutputsKnown_A | 108659317 | 104557416 | 0 | 0 |
gen_no_flops.OutputDelay_A | 108659317 | 104557416 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 815 | 815 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 108659317 | 104557416 | 0 | 0 |
T1 | 7240 | 5706 | 0 | 0 |
T2 | 674419 | 644804 | 0 | 0 |
T3 | 60188 | 55047 | 0 | 0 |
T4 | 9371 | 9246 | 0 | 0 |
T5 | 115969 | 110283 | 0 | 0 |
T9 | 7945 | 6810 | 0 | 0 |
T10 | 26466 | 19707 | 0 | 0 |
T11 | 5777 | 5689 | 0 | 0 |
T12 | 6510 | 5562 | 0 | 0 |
T13 | 26171 | 21248 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 108659317 | 104557416 | 0 | 0 |
T1 | 7240 | 5706 | 0 | 0 |
T2 | 674419 | 644804 | 0 | 0 |
T3 | 60188 | 55047 | 0 | 0 |
T4 | 9371 | 9246 | 0 | 0 |
T5 | 115969 | 110283 | 0 | 0 |
T9 | 7945 | 6810 | 0 | 0 |
T10 | 26466 | 19707 | 0 | 0 |
T11 | 5777 | 5689 | 0 | 0 |
T12 | 6510 | 5562 | 0 | 0 |
T13 | 26171 | 21248 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 815 | 815 | 0 | 0 |
OutputsKnown_A | 108636822 | 104535476 | 0 | 0 |
gen_no_flops.OutputDelay_A | 108636822 | 104535476 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 815 | 815 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 108636822 | 104535476 | 0 | 0 |
T1 | 7240 | 5706 | 0 | 0 |
T2 | 674419 | 644804 | 0 | 0 |
T3 | 60188 | 55047 | 0 | 0 |
T4 | 9371 | 9246 | 0 | 0 |
T5 | 115969 | 110283 | 0 | 0 |
T9 | 7945 | 6810 | 0 | 0 |
T10 | 26466 | 19707 | 0 | 0 |
T11 | 5777 | 5689 | 0 | 0 |
T12 | 6510 | 5562 | 0 | 0 |
T13 | 26171 | 21248 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 108636822 | 104535476 | 0 | 0 |
T1 | 7240 | 5706 | 0 | 0 |
T2 | 674419 | 644804 | 0 | 0 |
T3 | 60188 | 55047 | 0 | 0 |
T4 | 9371 | 9246 | 0 | 0 |
T5 | 115969 | 110283 | 0 | 0 |
T9 | 7945 | 6810 | 0 | 0 |
T10 | 26466 | 19707 | 0 | 0 |
T11 | 5777 | 5689 | 0 | 0 |
T12 | 6510 | 5562 | 0 | 0 |
T13 | 26171 | 21248 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 9 | 9 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 8 | 8 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 815 | 815 | 0 | 0 |
OutputsKnown_A | 108657096 | 104553884 | 0 | 0 |
gen_no_flops.OutputDelay_A | 108657096 | 104553884 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 815 | 815 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 108657096 | 104553884 | 0 | 0 |
T1 | 7240 | 5706 | 0 | 0 |
T2 | 674419 | 644804 | 0 | 0 |
T3 | 60188 | 55047 | 0 | 0 |
T4 | 9371 | 9246 | 0 | 0 |
T5 | 115969 | 110283 | 0 | 0 |
T9 | 7945 | 6810 | 0 | 0 |
T10 | 26466 | 19707 | 0 | 0 |
T11 | 5777 | 5689 | 0 | 0 |
T12 | 6510 | 5562 | 0 | 0 |
T13 | 26171 | 21248 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 108657096 | 104553884 | 0 | 0 |
T1 | 7240 | 5706 | 0 | 0 |
T2 | 674419 | 644804 | 0 | 0 |
T3 | 60188 | 55047 | 0 | 0 |
T4 | 9371 | 9246 | 0 | 0 |
T5 | 115969 | 110283 | 0 | 0 |
T9 | 7945 | 6810 | 0 | 0 |
T10 | 26466 | 19707 | 0 | 0 |
T11 | 5777 | 5689 | 0 | 0 |
T12 | 6510 | 5562 | 0 | 0 |
T13 | 26171 | 21248 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 815 | 815 | 0 | 0 |
OutputsKnown_A | 108659317 | 104557416 | 0 | 0 |
gen_flops.OutputDelay_A | 108659317 | 104392894 | 0 | 2409 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 815 | 815 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 108659317 | 104557416 | 0 | 0 |
T1 | 7240 | 5706 | 0 | 0 |
T2 | 674419 | 644804 | 0 | 0 |
T3 | 60188 | 55047 | 0 | 0 |
T4 | 9371 | 9246 | 0 | 0 |
T5 | 115969 | 110283 | 0 | 0 |
T9 | 7945 | 6810 | 0 | 0 |
T10 | 26466 | 19707 | 0 | 0 |
T11 | 5777 | 5689 | 0 | 0 |
T12 | 6510 | 5562 | 0 | 0 |
T13 | 26171 | 21248 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 108659317 | 104392894 | 0 | 2409 |
T1 | 7240 | 5643 | 0 | 3 |
T2 | 674419 | 643631 | 0 | 3 |
T3 | 60188 | 54840 | 0 | 3 |
T4 | 9371 | 9240 | 0 | 3 |
T5 | 115969 | 110055 | 0 | 3 |
T9 | 7945 | 6765 | 0 | 3 |
T10 | 26466 | 19446 | 0 | 3 |
T11 | 5777 | 5686 | 0 | 3 |
T12 | 6510 | 5526 | 0 | 3 |
T13 | 26171 | 21059 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 815 | 815 | 0 | 0 |
OutputsKnown_A | 108659317 | 104557416 | 0 | 0 |
gen_flops.OutputDelay_A | 108659317 | 104392894 | 0 | 2409 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 815 | 815 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 108659317 | 104557416 | 0 | 0 |
T1 | 7240 | 5706 | 0 | 0 |
T2 | 674419 | 644804 | 0 | 0 |
T3 | 60188 | 55047 | 0 | 0 |
T4 | 9371 | 9246 | 0 | 0 |
T5 | 115969 | 110283 | 0 | 0 |
T9 | 7945 | 6810 | 0 | 0 |
T10 | 26466 | 19707 | 0 | 0 |
T11 | 5777 | 5689 | 0 | 0 |
T12 | 6510 | 5562 | 0 | 0 |
T13 | 26171 | 21248 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 108659317 | 104392894 | 0 | 2409 |
T1 | 7240 | 5643 | 0 | 3 |
T2 | 674419 | 643631 | 0 | 3 |
T3 | 60188 | 54840 | 0 | 3 |
T4 | 9371 | 9240 | 0 | 3 |
T5 | 115969 | 110055 | 0 | 3 |
T9 | 7945 | 6765 | 0 | 3 |
T10 | 26466 | 19446 | 0 | 3 |
T11 | 5777 | 5686 | 0 | 3 |
T12 | 6510 | 5526 | 0 | 3 |
T13 | 26171 | 21059 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |