Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	100.00	82.35	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	111230783	13327	0	0
claim_transition_if_regwen_rd_A	111230783	1207	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111230783	13327	0	0
T5	115969	9	0	0
T11	5777	0	0	0
T12	6510	0	0	0
T13	26171	0	0	0
T18	20793	0	0	0
T19	16552	0	0	0
T37	0	7	0	0
T42	0	3	0	0
T45	0	17	0	0
T57	34797	0	0	0
T60	0	12	0	0
T64	37538	0	0	0
T70	19295	0	0	0
T85	1414	0	0	0
T88	0	4	0	0
T90	0	19	0	0
T116	0	11	0	0
T150	0	2	0	0
T151	0	11	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	111230783	1207	0	0
T47	0	2	0	0
T91	0	1	0	0
T122	0	18	0	0
T130	0	140	0	0
T152	680817	13	0	0
T153	0	5	0	0
T154	0	5	0	0
T155	0	117	0	0
T156	0	5	0	0
T157	0	13	0	0
T158	177284	0	0	0
T159	23539	0	0	0
T160	41983	0	0	0
T161	194363	0	0	0
T162	6416	0	0	0
T163	1474	0	0	0
T164	105065	0	0	0
T165	27564	0	0	0
T166	956	0	0	0