Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1279231	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1481452

1

T1

5

T2

760

T3

1052

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2448068	1			T1	5		T2	760		T3	1220
values[0x0]	156078	1			T1	2		T2	239		T3	271
values[0x1]	156537	1			T1	6		T2	241		T3	257

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1015162	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1745521

1

T1

6

T2

874

T3

1200

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10707	1			T2	11		T4	181		T10	7
valid_sources[0x01]	8861	1			T2	7		T3	39		T4	184
valid_sources[0x02]	9786	1			T2	2		T3	6		T4	163
valid_sources[0x03]	9459	1			T2	2		T3	13		T4	177
valid_sources[0x04]	11353	1			T2	1		T4	179		T10	10
valid_sources[0x05]	8594	1			T2	3		T4	180		T10	7
valid_sources[0x06]	8705	1			T2	2		T4	180		T10	6
valid_sources[0x07]	8624	1			T2	4		T3	6		T4	179
valid_sources[0x08]	8751	1			T2	2		T4	204		T10	7
valid_sources[0x09]	10231	1			T2	5		T4	187		T10	6
valid_sources[0x0a]	9225	1			T2	3		T3	34		T4	210
valid_sources[0x0b]	8874	1			T2	9		T3	8		T4	191
valid_sources[0x0c]	8502	1			T2	5		T4	190		T10	6
valid_sources[0x0d]	9609	1			T2	4		T4	171		T10	6
valid_sources[0x0e]	8729	1			T2	7		T4	165		T10	2
valid_sources[0x0f]	8310	1			T2	3		T3	25		T4	173
valid_sources[0x10]	26900	1			T2	3		T3	3		T4	176
valid_sources[0x11]	8920	1			T2	2		T3	46		T4	196
valid_sources[0x12]	12044	1			T2	1		T4	203		T10	2
valid_sources[0x13]	11139	1			T2	4		T4	175		T10	9
valid_sources[0x14]	8868	1			T2	1		T4	177		T10	5
valid_sources[0x15]	8353	1			T2	4		T4	178		T10	8
valid_sources[0x16]	10103	1			T2	4		T3	2		T4	160
valid_sources[0x17]	47732	1			T2	12		T4	167		T10	7
valid_sources[0x18]	11169	1			T3	15		T4	172		T10	6
valid_sources[0x19]	8918	1			T2	6		T3	41		T4	205
valid_sources[0x1a]	10678	1			T2	3		T4	179		T10	5
valid_sources[0x1b]	9362	1			T2	6		T4	183		T10	6
valid_sources[0x1c]	9099	1			T2	4		T3	2		T4	176
valid_sources[0x1d]	12054	1			T2	5		T3	4		T4	147
valid_sources[0x1e]	11996	1			T2	3		T3	20		T4	156
valid_sources[0x1f]	19414	1			T2	3		T3	8		T4	197
valid_sources[0x20]	9550	1			T2	5		T4	201		T10	7
valid_sources[0x21]	8946	1			T2	6		T4	175		T10	13
valid_sources[0x22]	8806	1			T1	2		T2	8		T3	3
valid_sources[0x23]	12104	1			T4	207		T10	8		T5	2
valid_sources[0x24]	9023	1			T2	5		T3	44		T4	181
valid_sources[0x25]	9072	1			T2	4		T4	146		T10	9
valid_sources[0x26]	8773	1			T2	5		T4	190		T10	5
valid_sources[0x27]	8387	1			T2	4		T4	160		T10	9
valid_sources[0x28]	9934	1			T2	7		T3	29		T4	183
valid_sources[0x29]	68741	1			T2	3		T4	172		T10	4
valid_sources[0x2a]	8716	1			T2	4		T3	11		T4	202
valid_sources[0x2b]	8443	1			T2	12		T3	7		T4	178
valid_sources[0x2c]	8888	1			T2	3		T4	170		T10	10
valid_sources[0x2d]	9783	1			T2	9		T4	177		T10	4
valid_sources[0x2e]	8422	1			T2	2		T3	4		T4	158
valid_sources[0x2f]	8725	1			T2	1		T3	9		T4	177
valid_sources[0x30]	8616	1			T2	1		T4	170		T10	6
valid_sources[0x31]	9920	1			T2	5		T4	186		T10	3
valid_sources[0x32]	9665	1			T2	10		T4	171		T10	6
valid_sources[0x33]	8786	1			T2	9		T3	10		T4	177
valid_sources[0x34]	9868	1			T2	3		T3	3		T4	164
valid_sources[0x35]	11353	1			T2	4		T3	1		T4	195
valid_sources[0x36]	29555	1			T2	6		T3	2		T4	185
valid_sources[0x37]	9758	1			T2	5		T3	22		T4	183
valid_sources[0x38]	8733	1			T2	1		T4	170		T10	5
valid_sources[0x39]	8894	1			T2	5		T4	200		T10	6
valid_sources[0x3a]	8807	1			T2	1		T3	3		T4	155
valid_sources[0x3b]	8639	1			T2	9		T4	189		T10	4
valid_sources[0x3c]	8445	1			T2	5		T4	187		T10	11
valid_sources[0x3d]	9708	1			T2	4		T4	170		T10	6
valid_sources[0x3e]	8661	1			T2	4		T4	205		T10	5
valid_sources[0x3f]	8117	1			T2	3		T4	172		T10	8
valid_sources[0x40]	10073	1			T2	3		T3	31		T4	206
valid_sources[0x41]	8532	1			T2	4		T4	185		T10	7
valid_sources[0x42]	8817	1			T2	1		T3	56		T4	184
valid_sources[0x43]	9030	1			T2	12		T4	171		T10	9
valid_sources[0x44]	13988	1			T2	3		T4	185		T10	6
valid_sources[0x45]	9616	1			T2	5		T3	13		T4	168
valid_sources[0x46]	10353	1			T2	1		T3	18		T4	168
valid_sources[0x47]	8576	1			T2	4		T3	4		T4	164
valid_sources[0x48]	8636	1			T2	15		T4	162		T10	9
valid_sources[0x49]	8746	1			T4	194		T10	3		T11	7
valid_sources[0x4a]	8406	1			T2	4		T3	5		T4	162
valid_sources[0x4b]	8420	1			T2	3		T4	191		T10	9
valid_sources[0x4c]	9052	1			T2	2		T3	9		T4	200
valid_sources[0x4d]	8703	1			T4	181		T10	7		T11	4
valid_sources[0x4e]	76505	1			T2	1		T3	2		T4	165
valid_sources[0x4f]	8461	1			T2	3		T3	19		T4	171
valid_sources[0x50]	8592	1			T3	1		T4	192		T10	10
valid_sources[0x51]	9050	1			T2	10		T4	177		T10	8
valid_sources[0x52]	8799	1			T2	6		T4	166		T10	5
valid_sources[0x53]	8828	1			T2	4		T4	171		T10	5
valid_sources[0x54]	8640	1			T2	8		T3	10		T4	163
valid_sources[0x55]	33297	1			T2	7		T4	172		T10	8
valid_sources[0x56]	8691	1			T2	5		T4	188		T10	3
valid_sources[0x57]	11146	1			T2	13		T4	210		T10	12
valid_sources[0x58]	8887	1			T2	17		T4	160		T10	9
valid_sources[0x59]	9681	1			T2	6		T3	2		T4	165
valid_sources[0x5a]	8780	1			T2	19		T3	14		T4	191
valid_sources[0x5b]	8994	1			T2	3		T3	5		T4	204
valid_sources[0x5c]	8636	1			T2	3		T3	2		T4	186
valid_sources[0x5d]	11571	1			T2	1		T4	171		T10	13
valid_sources[0x5e]	8904	1			T2	2		T3	27		T4	192
valid_sources[0x5f]	9024	1			T2	5		T4	163		T10	6
valid_sources[0x60]	9062	1			T2	5		T3	7		T4	169
valid_sources[0x61]	8451	1			T2	6		T4	213		T10	6
valid_sources[0x62]	8697	1			T2	1		T3	15		T4	178
valid_sources[0x63]	9464	1			T2	10		T3	34		T4	174
valid_sources[0x64]	8607	1			T2	10		T4	183		T10	6
valid_sources[0x65]	8683	1			T2	4		T3	11		T4	162
valid_sources[0x66]	8860	1			T2	7		T4	195		T10	12
valid_sources[0x67]	41176	1			T2	3		T3	3		T4	206
valid_sources[0x68]	10724	1			T2	3		T4	166		T10	9
valid_sources[0x69]	8656	1			T2	2		T4	162		T10	10
valid_sources[0x6a]	9065	1			T2	13		T3	9		T4	190
valid_sources[0x6b]	9984	1			T2	7		T3	44		T4	181
valid_sources[0x6c]	9013	1			T2	2		T4	180		T10	3
valid_sources[0x6d]	8669	1			T2	2		T3	1		T4	185
valid_sources[0x6e]	8735	1			T2	7		T4	188		T10	6
valid_sources[0x6f]	9633	1			T2	9		T4	179		T10	5
valid_sources[0x70]	8999	1			T2	5		T3	57		T4	183
valid_sources[0x71]	8796	1			T2	3		T3	10		T4	185
valid_sources[0x72]	8573	1			T2	3		T3	2		T4	201
valid_sources[0x73]	8506	1			T2	10		T3	25		T4	167
valid_sources[0x74]	8295	1			T2	11		T4	186		T10	9
valid_sources[0x75]	8864	1			T2	8		T3	16		T4	212
valid_sources[0x76]	8871	1			T2	2		T4	151		T10	4
valid_sources[0x77]	8536	1			T2	3		T4	174		T10	4
valid_sources[0x78]	8512	1			T2	6		T3	8		T4	178
valid_sources[0x79]	8960	1			T2	8		T4	164		T10	12
valid_sources[0x7a]	8670	1			T2	4		T4	173		T10	9
valid_sources[0x7b]	8629	1			T2	7		T3	18		T4	162
valid_sources[0x7c]	8703	1			T2	5		T4	156		T10	8
valid_sources[0x7d]	8712	1			T2	7		T4	177		T10	10
valid_sources[0x7e]	9438	1			T2	1		T4	176		T10	6
valid_sources[0x7f]	9042	1			T2	1		T3	8		T4	153
valid_sources[0x80]	9242	1			T2	5		T4	183		T10	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1212119

1

T2

342

T3

592

T4

22567

values[0x0]

all_enables

biggest_size

135317

1

T1

2

T2

208

T3

235

values[0x1]

all_enables

biggest_size

134016

1

T1

3

T2

210

T3

225