Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	86968335	13538	0	0
claim_transition_if_regwen_rd_A	86968335	1438	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	86968335	13538	0	0
T51	214676	2	0	0
T69	4333	0	0	0
T83	0	2	0	0
T93	0	1	0	0
T96	0	2	0	0
T97	0	3	0	0
T100	0	2	0	0
T135	0	8	0	0
T136	0	6	0	0
T137	0	1	0	0
T138	0	5	0	0
T139	1640	0	0	0
T140	2425	0	0	0
T141	32230	0	0	0
T142	24562	0	0	0
T143	741	0	0	0
T144	26231	0	0	0
T145	33928	0	0	0
T146	11032	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	86968335	1438	0	0
T23	18305	0	0	0
T44	17413	0	0	0
T45	39525	0	0	0
T77	856119	14	0	0
T78	318698	0	0	0
T83	0	3	0	0
T85	194348	0	0	0
T93	0	7	0	0
T100	0	2	0	0
T105	0	22	0	0
T147	0	1	0	0
T148	0	12	0	0
T149	0	11	0	0
T150	0	1	0	0
T151	0	7	0	0
T152	38571	0	0	0
T153	4636	0	0	0
T154	225656	0	0	0
T155	5402	0	0	0