Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1991110	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2210173

1

T3

5

T4

567

T10

1749

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3863380	1			T3	8		T4	519		T10	2166
values[0x0]	169007	1			T3	5		T4	212		T10	374
values[0x1]	168896	1			T3	3		T4	212		T10	418

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1584124	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2617159

1

T3

7

T4

680

T10

2011

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12651	1			T4	4		T10	11		T11	27
valid_sources[0x01]	15620	1			T10	16		T11	15		T6	14
valid_sources[0x02]	11953	1			T4	2		T10	8		T11	6
valid_sources[0x03]	11866	1			T4	2		T10	4		T11	17
valid_sources[0x04]	182397	1			T4	11		T10	8		T11	14
valid_sources[0x05]	13630	1			T4	3		T10	10		T11	12
valid_sources[0x06]	12279	1			T4	1		T10	11		T11	21
valid_sources[0x07]	12606	1			T4	5		T10	3		T11	32
valid_sources[0x08]	15827	1			T4	2		T10	6		T11	9
valid_sources[0x09]	13187	1			T4	2		T10	25		T11	7
valid_sources[0x0a]	11771	1			T4	6		T10	7		T11	15
valid_sources[0x0b]	12073	1			T4	5		T10	10		T11	17
valid_sources[0x0c]	12542	1			T4	6		T10	13		T11	12
valid_sources[0x0d]	13102	1			T4	2		T10	3		T11	16
valid_sources[0x0e]	49087	1			T4	4		T10	7		T11	15
valid_sources[0x0f]	13774	1			T10	11		T11	14		T12	178
valid_sources[0x10]	65038	1			T4	9		T10	8		T11	17
valid_sources[0x11]	12472	1			T4	3		T10	18		T11	9
valid_sources[0x12]	11875	1			T4	3		T10	19		T11	14
valid_sources[0x13]	12511	1			T4	11		T10	7		T11	11
valid_sources[0x14]	13205	1			T4	3		T10	12		T11	11
valid_sources[0x15]	12738	1			T4	5		T10	5		T11	27
valid_sources[0x16]	12282	1			T4	2		T10	9		T11	15
valid_sources[0x17]	12498	1			T10	4		T11	14		T6	7
valid_sources[0x18]	12518	1			T4	1		T10	12		T11	16
valid_sources[0x19]	12004	1			T4	9		T10	16		T11	10
valid_sources[0x1a]	12922	1			T4	1		T10	18		T11	17
valid_sources[0x1b]	12163	1			T4	6		T10	8		T11	11
valid_sources[0x1c]	12799	1			T4	2		T10	6		T11	16
valid_sources[0x1d]	11900	1			T4	5		T10	17		T11	9
valid_sources[0x1e]	14184	1			T4	1		T10	6		T11	13
valid_sources[0x1f]	12486	1			T4	6		T10	13		T11	15
valid_sources[0x20]	12672	1			T4	4		T10	18		T11	22
valid_sources[0x21]	12373	1			T4	4		T10	7		T11	9
valid_sources[0x22]	12680	1			T4	3		T10	10		T11	22
valid_sources[0x23]	12006	1			T4	4		T10	9		T11	12
valid_sources[0x24]	12481	1			T4	1		T10	11		T11	7
valid_sources[0x25]	14596	1			T10	8		T11	17		T12	182
valid_sources[0x26]	12077	1			T4	3		T10	15		T11	9
valid_sources[0x27]	27328	1			T4	4		T10	10		T11	25
valid_sources[0x28]	12616	1			T4	1		T10	9		T11	25
valid_sources[0x29]	12919	1			T4	3		T10	10		T11	15
valid_sources[0x2a]	18567	1			T4	2		T10	2		T11	20
valid_sources[0x2b]	12209	1			T4	1		T10	7		T11	22
valid_sources[0x2c]	12494	1			T4	1		T10	11		T11	13
valid_sources[0x2d]	12763	1			T4	9		T10	7		T11	19
valid_sources[0x2e]	12398	1			T4	2		T10	12		T11	13
valid_sources[0x2f]	13683	1			T4	1		T10	9		T11	15
valid_sources[0x30]	13508	1			T4	2		T10	7		T11	28
valid_sources[0x31]	11972	1			T4	3		T10	14		T11	10
valid_sources[0x32]	13138	1			T4	9		T10	9		T11	14
valid_sources[0x33]	13514	1			T4	4		T10	16		T11	15
valid_sources[0x34]	29641	1			T4	10		T10	11		T11	16
valid_sources[0x35]	12468	1			T4	3		T10	15		T11	32
valid_sources[0x36]	18245	1			T4	3		T10	8		T11	11
valid_sources[0x37]	12007	1			T4	4		T10	9		T11	26
valid_sources[0x38]	19113	1			T4	5		T10	16		T11	19
valid_sources[0x39]	48649	1			T4	7		T10	7		T11	11
valid_sources[0x3a]	12966	1			T4	2		T10	13		T11	30
valid_sources[0x3b]	12411	1			T4	3		T10	13		T11	21
valid_sources[0x3c]	13344	1			T4	2		T10	9		T11	12
valid_sources[0x3d]	13356	1			T4	8		T10	8		T11	20
valid_sources[0x3e]	12444	1			T4	1		T10	14		T11	8
valid_sources[0x3f]	15538	1			T4	1		T10	14		T11	14
valid_sources[0x40]	11677	1			T4	6		T10	11		T11	8
valid_sources[0x41]	12084	1			T4	6		T10	13		T11	18
valid_sources[0x42]	12948	1			T4	6		T10	21		T11	20
valid_sources[0x43]	12086	1			T4	5		T10	6		T11	11
valid_sources[0x44]	13785	1			T4	4		T10	7		T11	10
valid_sources[0x45]	12238	1			T4	10		T10	11		T11	27
valid_sources[0x46]	13056	1			T4	1		T10	8		T11	8
valid_sources[0x47]	12423	1			T4	1		T10	16		T11	15
valid_sources[0x48]	12958	1			T4	5		T10	14		T11	10
valid_sources[0x49]	12102	1			T4	4		T10	18		T11	17
valid_sources[0x4a]	15305	1			T4	5		T10	9		T11	16
valid_sources[0x4b]	12142	1			T4	5		T10	4		T11	10
valid_sources[0x4c]	12847	1			T4	2		T10	16		T11	15
valid_sources[0x4d]	14604	1			T10	17		T11	11		T12	172
valid_sources[0x4e]	12516	1			T4	6		T10	9		T11	15
valid_sources[0x4f]	12004	1			T4	1		T10	2		T11	13
valid_sources[0x50]	15375	1			T4	2		T10	3		T11	17
valid_sources[0x51]	13218	1			T4	7		T10	13		T11	23
valid_sources[0x52]	16420	1			T4	1		T10	10		T11	16
valid_sources[0x53]	18582	1			T4	6		T10	16		T11	21
valid_sources[0x54]	12291	1			T4	5		T10	5		T11	15
valid_sources[0x55]	13782	1			T4	5		T10	12		T11	15
valid_sources[0x56]	12257	1			T4	9		T10	13		T11	13
valid_sources[0x57]	12520	1			T4	3		T10	12		T11	20
valid_sources[0x58]	12329	1			T4	4		T10	15		T11	14
valid_sources[0x59]	13555	1			T4	2		T10	15		T11	7
valid_sources[0x5a]	11977	1			T4	3		T10	18		T11	16
valid_sources[0x5b]	15076	1			T4	2		T10	10		T11	15
valid_sources[0x5c]	60088	1			T4	8		T10	10		T11	10
valid_sources[0x5d]	12886	1			T4	5		T10	11		T11	13
valid_sources[0x5e]	12521	1			T4	3		T10	17		T11	17
valid_sources[0x5f]	13171	1			T4	1		T10	7		T11	20
valid_sources[0x60]	18801	1			T4	6		T10	21		T11	22
valid_sources[0x61]	12198	1			T4	1		T10	13		T11	26
valid_sources[0x62]	11849	1			T10	12		T11	14		T12	174
valid_sources[0x63]	12016	1			T4	1		T10	13		T11	14
valid_sources[0x64]	11953	1			T10	13		T11	12		T12	168
valid_sources[0x65]	58916	1			T4	4		T10	10		T11	16
valid_sources[0x66]	13592	1			T4	9		T10	5		T11	16
valid_sources[0x67]	13014	1			T4	3		T10	16		T11	22
valid_sources[0x68]	13929	1			T10	13		T11	10		T12	169
valid_sources[0x69]	11728	1			T4	1		T10	18		T11	26
valid_sources[0x6a]	12002	1			T4	6		T10	17		T11	24
valid_sources[0x6b]	12165	1			T4	4		T10	6		T11	13
valid_sources[0x6c]	12089	1			T4	3		T10	14		T11	14
valid_sources[0x6d]	12382	1			T4	4		T10	12		T11	9
valid_sources[0x6e]	13436	1			T4	4		T10	12		T11	24
valid_sources[0x6f]	15426	1			T10	9		T11	14		T12	182
valid_sources[0x70]	12871	1			T4	2		T10	10		T11	16
valid_sources[0x71]	12133	1			T4	4		T10	13		T11	18
valid_sources[0x72]	15799	1			T4	4		T10	11		T11	15
valid_sources[0x73]	12075	1			T4	4		T10	18		T11	20
valid_sources[0x74]	13667	1			T4	2		T10	15		T11	15
valid_sources[0x75]	12709	1			T4	6		T10	16		T11	12
valid_sources[0x76]	13294	1			T4	5		T10	13		T11	13
valid_sources[0x77]	13546	1			T4	5		T10	5		T11	10
valid_sources[0x78]	12237	1			T4	6		T10	10		T11	16
valid_sources[0x79]	12205	1			T4	3		T10	14		T11	3
valid_sources[0x7a]	21969	1			T4	1		T10	10		T11	16
valid_sources[0x7b]	11914	1			T4	5		T10	10		T11	14
valid_sources[0x7c]	13866	1			T4	3		T10	10		T11	13
valid_sources[0x7d]	12353	1			T4	5		T10	16		T11	8
valid_sources[0x7e]	12170	1			T4	5		T10	8		T11	14
valid_sources[0x7f]	12575	1			T10	16		T11	23		T12	177
valid_sources[0x80]	12391	1			T4	3		T10	12		T11	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1918759

1

T4

196

T10

1065

T11

1673

values[0x0]

all_enables

biggest_size

146728

1

T3

4

T4

187

T10

315

values[0x1]

all_enables

biggest_size

144686

1

T3

1

T4

184

T10

369