Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	105317028	15131	0	0
claim_transition_if_regwen_rd_A	105317028	1802	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105317028	15131	0	0
T7	49683	0	0	0
T12	284410	3	0	0
T13	15668	0	0	0
T14	34083	0	0	0
T15	106722	0	0	0
T16	2061	0	0	0
T18	8569	0	0	0
T19	3460	0	0	0
T20	13026	0	0	0
T30	20837	0	0	0
T38	0	4	0	0
T49	0	8	0	0
T94	0	4	0	0
T95	0	6	0	0
T105	0	8	0	0
T132	0	5	0	0
T133	0	5	0	0
T134	0	3	0	0
T135	0	2	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	105317028	1802	0	0
T36	39098	0	0	0
T38	260293	27	0	0
T44	30327	0	0	0
T48	19861	0	0	0
T93	0	10	0	0
T106	0	13	0	0
T136	0	12	0	0
T137	0	6	0	0
T138	0	5	0	0
T139	0	200	0	0
T140	0	18	0	0
T141	0	16	0	0
T142	0	5	0	0
T143	1641	0	0	0
T144	2809	0	0	0
T145	38899	0	0	0
T146	247319	0	0	0
T147	3076	0	0	0
T148	37877	0	0	0