Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1881484	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2120322

1

T2

1029

T3

123

T9

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3626733	1			T2	791		T3	110		T4	139
values[0x0]	187313	1			T2	367		T3	44		T9	20
values[0x1]	187760	1			T2	369		T3	52		T9	17

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1494302	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2507504

1

T2

1135

T3

147

T9

11

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9303	1			T2	4		T11	5		T5	24
valid_sources[0x01]	10341	1			T2	5		T11	9		T5	17
valid_sources[0x02]	18464	1			T2	9		T11	5		T5	15
valid_sources[0x03]	8760	1			T2	3		T4	2		T11	7
valid_sources[0x04]	15400	1			T2	8		T3	2		T11	4
valid_sources[0x05]	9224	1			T2	5		T3	2		T4	1
valid_sources[0x06]	9149	1			T2	4		T9	4		T4	5
valid_sources[0x07]	11401	1			T2	6		T11	7		T5	19
valid_sources[0x08]	9443	1			T2	9		T3	4		T4	1
valid_sources[0x09]	16847	1			T2	8		T3	2		T11	6
valid_sources[0x0a]	9777	1			T2	7		T4	1		T11	1
valid_sources[0x0b]	9727	1			T2	4		T3	1		T4	1
valid_sources[0x0c]	9217	1			T2	4		T3	1		T4	2
valid_sources[0x0d]	9185	1			T2	3		T11	9		T5	23
valid_sources[0x0e]	9652	1			T2	3		T3	1		T4	1
valid_sources[0x0f]	22429	1			T2	5		T4	1		T11	13
valid_sources[0x10]	9025	1			T2	7		T3	6		T11	13
valid_sources[0x11]	9962	1			T2	10		T11	10		T5	11
valid_sources[0x12]	9444	1			T2	7		T3	6		T11	6
valid_sources[0x13]	9523	1			T2	6		T3	6		T11	5
valid_sources[0x14]	55299	1			T2	7		T4	2		T11	17
valid_sources[0x15]	22817	1			T2	6		T4	1		T11	8
valid_sources[0x16]	9025	1			T2	5		T4	2		T11	9
valid_sources[0x17]	9805	1			T2	6		T3	3		T4	4
valid_sources[0x18]	9127	1			T2	11		T11	4		T5	18
valid_sources[0x19]	10707	1			T2	7		T3	2		T11	15
valid_sources[0x1a]	9006	1			T2	5		T11	4		T5	19
valid_sources[0x1b]	9618	1			T2	6		T4	3		T11	4
valid_sources[0x1c]	9411	1			T9	8		T4	1		T11	11
valid_sources[0x1d]	98204	1			T2	7		T11	11		T5	16
valid_sources[0x1e]	11018	1			T2	7		T4	1		T11	12
valid_sources[0x1f]	10927	1			T2	4		T9	1		T4	3
valid_sources[0x20]	51870	1			T2	5		T11	4		T5	15
valid_sources[0x21]	10489	1			T2	4		T4	1		T11	16
valid_sources[0x22]	10282	1			T2	5		T11	7		T5	21
valid_sources[0x23]	10250	1			T2	6		T3	1		T11	5
valid_sources[0x24]	12709	1			T2	5		T3	1		T11	7
valid_sources[0x25]	11029	1			T2	9		T4	2		T11	4
valid_sources[0x26]	12519	1			T2	4		T4	1		T11	7
valid_sources[0x27]	10529	1			T2	6		T11	9		T5	21
valid_sources[0x28]	9121	1			T2	5		T11	12		T5	12
valid_sources[0x29]	9767	1			T2	7		T3	3		T4	3
valid_sources[0x2a]	10618	1			T2	7		T3	2		T11	9
valid_sources[0x2b]	10828	1			T2	5		T3	4		T11	9
valid_sources[0x2c]	11749	1			T2	5		T11	6		T5	20
valid_sources[0x2d]	11406	1			T2	9		T3	3		T4	1
valid_sources[0x2e]	9423	1			T2	6		T4	1		T11	5
valid_sources[0x2f]	32451	1			T2	8		T4	3		T11	18
valid_sources[0x30]	14476	1			T2	2		T11	6		T5	10
valid_sources[0x31]	36800	1			T2	6		T4	2		T11	7
valid_sources[0x32]	11158	1			T2	6		T11	12		T5	24
valid_sources[0x33]	10604	1			T2	9		T3	1		T4	1
valid_sources[0x34]	11391	1			T2	8		T11	10		T5	18
valid_sources[0x35]	9524	1			T2	4		T4	2		T11	6
valid_sources[0x36]	13593	1			T2	6		T11	6		T5	15
valid_sources[0x37]	19186	1			T2	6		T3	2		T11	9
valid_sources[0x38]	9944	1			T2	9		T4	1		T11	6
valid_sources[0x39]	20006	1			T2	9		T4	2		T11	11
valid_sources[0x3a]	9385	1			T2	2		T11	6		T5	27
valid_sources[0x3b]	9334	1			T2	3		T9	1		T11	8
valid_sources[0x3c]	11275	1			T2	2		T3	6		T11	10
valid_sources[0x3d]	14397	1			T2	5		T4	1		T11	14
valid_sources[0x3e]	25591	1			T2	6		T11	8		T5	12
valid_sources[0x3f]	8762	1			T2	6		T4	1		T11	16
valid_sources[0x40]	9121	1			T2	7		T4	2		T11	13
valid_sources[0x41]	9055	1			T2	9		T4	2		T11	16
valid_sources[0x42]	9545	1			T2	4		T11	10		T5	21
valid_sources[0x43]	9298	1			T2	5		T3	3		T4	5
valid_sources[0x44]	9650	1			T2	3		T11	10		T5	14
valid_sources[0x45]	8869	1			T2	5		T4	2		T11	9
valid_sources[0x46]	9235	1			T2	2		T4	7		T11	9
valid_sources[0x47]	8884	1			T2	3		T11	9		T5	19
valid_sources[0x48]	12173	1			T2	2		T11	10		T5	18
valid_sources[0x49]	8822	1			T2	8		T11	7		T5	16
valid_sources[0x4a]	8351	1			T2	5		T11	6		T5	23
valid_sources[0x4b]	10048	1			T2	8		T4	1		T11	12
valid_sources[0x4c]	26805	1			T2	7		T3	2		T4	2
valid_sources[0x4d]	9462	1			T2	9		T4	1		T11	16
valid_sources[0x4e]	9529	1			T2	10		T11	20		T5	14
valid_sources[0x4f]	71498	1			T2	6		T3	6		T4	1
valid_sources[0x50]	32613	1			T2	9		T11	11		T5	26
valid_sources[0x51]	9795	1			T2	11		T11	10		T5	25
valid_sources[0x52]	9064	1			T2	3		T4	1		T11	7
valid_sources[0x53]	26852	1			T2	7		T3	1		T4	4
valid_sources[0x54]	11596	1			T2	13		T4	1		T11	5
valid_sources[0x55]	8701	1			T2	4		T4	1		T11	5
valid_sources[0x56]	51333	1			T2	5		T4	2		T11	7
valid_sources[0x57]	14299	1			T2	6		T3	6		T4	1
valid_sources[0x58]	9936	1			T2	2		T4	2		T11	14
valid_sources[0x59]	9242	1			T2	4		T3	9		T4	1
valid_sources[0x5a]	31942	1			T2	9		T11	8		T5	20
valid_sources[0x5b]	10054	1			T2	7		T11	10		T5	10
valid_sources[0x5c]	10665	1			T2	11		T4	5		T11	7
valid_sources[0x5d]	19195	1			T2	6		T3	22		T4	1
valid_sources[0x5e]	11715	1			T2	5		T11	12		T5	17
valid_sources[0x5f]	9335	1			T2	9		T11	17		T5	18
valid_sources[0x60]	8878	1			T2	8		T4	3		T11	5
valid_sources[0x61]	9457	1			T2	6		T11	16		T5	10
valid_sources[0x62]	10751	1			T2	5		T4	1		T11	9
valid_sources[0x63]	9735	1			T2	2		T4	2		T11	4
valid_sources[0x64]	38361	1			T2	4		T4	1		T11	10
valid_sources[0x65]	11468	1			T2	4		T9	2		T4	4
valid_sources[0x66]	8718	1			T2	13		T3	1		T11	14
valid_sources[0x67]	8956	1			T2	7		T11	8		T5	17
valid_sources[0x68]	9995	1			T2	4		T9	2		T4	3
valid_sources[0x69]	9399	1			T2	7		T4	3		T11	7
valid_sources[0x6a]	9484	1			T2	5		T4	1		T11	9
valid_sources[0x6b]	9509	1			T2	10		T3	5		T11	13
valid_sources[0x6c]	9229	1			T2	6		T4	1		T11	5
valid_sources[0x6d]	45605	1			T2	4		T3	2		T11	18
valid_sources[0x6e]	9370	1			T2	8		T4	2		T11	13
valid_sources[0x6f]	9146	1			T2	7		T11	10		T5	16
valid_sources[0x70]	9301	1			T2	4		T4	2		T11	7
valid_sources[0x71]	100044	1			T2	5		T11	7		T5	19
valid_sources[0x72]	31239	1			T2	6		T4	1		T11	7
valid_sources[0x73]	10989	1			T2	7		T4	4		T11	5
valid_sources[0x74]	9662	1			T2	5		T4	2		T11	8
valid_sources[0x75]	9273	1			T2	10		T11	5		T5	15
valid_sources[0x76]	17405	1			T2	2		T3	9		T11	6
valid_sources[0x77]	8981	1			T2	4		T11	6		T5	18
valid_sources[0x78]	12508	1			T2	9		T11	5		T5	16
valid_sources[0x79]	9182	1			T2	5		T3	6		T4	1
valid_sources[0x7a]	11088	1			T2	4		T4	1		T11	7
valid_sources[0x7b]	9291	1			T2	7		T3	4		T4	1
valid_sources[0x7c]	9106	1			T2	5		T3	1		T11	4
valid_sources[0x7d]	9626	1			T2	9		T11	3		T5	19
valid_sources[0x7e]	11664	1			T2	8		T4	2		T11	10
valid_sources[0x7f]	17426	1			T2	5		T11	8		T5	31
valid_sources[0x80]	9103	1			T2	10		T3	1		T11	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1797581

1

T2

402

T3

43

T4

67

values[0x0]

all_enables

biggest_size

162076

1

T2

316

T3

36

T9

4

values[0x1]

all_enables

biggest_size

160665

1

T2

311

T3

44

T9

5