Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	100.00	82.35	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	134601208	14748	0	0
claim_transition_if_regwen_rd_A	134601208	2615	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134601208	14748	0	0
T7	46016	0	0	0
T32	384441	1	0	0
T33	232734	0	0	0
T34	873442	0	0	0
T35	22289	0	0	0
T36	27313	0	0	0
T37	1230	0	0	0
T38	56180	0	0	0
T39	0	3	0	0
T41	0	3	0	0
T42	0	5	0	0
T43	0	2	0	0
T82	0	3	0	0
T107	0	7	0	0
T148	0	3	0	0
T149	0	1	0	0
T150	0	5	0	0
T151	1751	0	0	0
T152	2711	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134601208	2615	0	0
T7	46016	0	0	0
T32	384441	19	0	0
T33	232734	0	0	0
T34	873442	0	0	0
T35	22289	0	0	0
T36	27313	0	0	0
T37	1230	0	0	0
T38	56180	0	0	0
T39	0	22	0	0
T41	0	12	0	0
T43	0	13	0	0
T111	0	81	0	0
T149	0	7	0	0
T151	1751	0	0	0
T152	2711	0	0	0
T153	0	4	0	0
T154	0	12	0	0
T155	0	3	0	0
T156	0	21	0	0