Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1148842	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1362551

1

T1

13

T2

1

T3

622

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2178768	1			T1	11		T2	2		T3	519
values[0x0]	165803	1			T1	5		T2	1		T3	201
values[0x1]	166822	1			T1	4		T3	223		T4	43

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	910362	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1601031

1

T1

17

T2

1

T3

708

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6442	1			T3	2		T15	8		T16	2
valid_sources[0x01]	6227	1			T13	4		T15	5		T16	2
valid_sources[0x02]	6842	1			T3	10		T4	1		T15	5
valid_sources[0x03]	6588	1			T3	7		T5	2		T13	6
valid_sources[0x04]	7486	1			T13	2		T15	11		T16	5
valid_sources[0x05]	6172	1			T3	10		T4	2		T15	8
valid_sources[0x06]	6486	1			T3	5		T5	3		T15	8
valid_sources[0x07]	6503	1			T3	5		T4	1		T13	9
valid_sources[0x08]	10930	1			T3	9		T4	2		T13	5
valid_sources[0x09]	6316	1			T3	5		T4	1		T13	2
valid_sources[0x0a]	6322	1			T3	3		T4	4		T13	4
valid_sources[0x0b]	6100	1			T3	3		T13	3		T15	9
valid_sources[0x0c]	14203	1			T4	1		T13	14		T15	5
valid_sources[0x0d]	8652	1			T3	2		T13	1		T15	6
valid_sources[0x0e]	6489	1			T3	2		T13	2		T15	6
valid_sources[0x0f]	6288	1			T3	5		T13	7		T15	6
valid_sources[0x10]	6430	1			T3	4		T16	5		T11	329
valid_sources[0x11]	6945	1			T4	1		T13	2		T15	4
valid_sources[0x12]	7299	1			T3	9		T12	1		T13	2
valid_sources[0x13]	6028	1			T4	1		T12	1		T5	2
valid_sources[0x14]	6289	1			T3	1		T4	2		T15	6
valid_sources[0x15]	8006	1			T3	9		T13	3		T15	8
valid_sources[0x16]	10100	1			T3	2		T13	1		T15	6
valid_sources[0x17]	6738	1			T3	1		T5	20		T15	11
valid_sources[0x18]	7622	1			T3	2		T15	7		T16	4
valid_sources[0x19]	6068	1			T3	3		T13	2		T15	5
valid_sources[0x1a]	14385	1			T3	5		T13	9		T15	9
valid_sources[0x1b]	6562	1			T3	10		T4	2		T13	11
valid_sources[0x1c]	6314	1			T3	1		T13	7		T15	9
valid_sources[0x1d]	6444	1			T3	10		T13	7		T15	11
valid_sources[0x1e]	6473	1			T3	1		T13	9		T15	2
valid_sources[0x1f]	6916	1			T3	7		T13	5		T15	3
valid_sources[0x20]	7736	1			T4	1		T5	1		T15	8
valid_sources[0x21]	6536	1			T3	2		T13	2		T15	5
valid_sources[0x22]	6054	1			T3	1		T4	1		T15	17
valid_sources[0x23]	8171	1			T3	1		T4	1		T5	1
valid_sources[0x24]	6845	1			T3	6		T4	2		T5	1
valid_sources[0x25]	11631	1			T3	4		T13	5		T15	4
valid_sources[0x26]	21921	1			T3	2		T4	1		T12	1
valid_sources[0x27]	7421	1			T3	7		T4	2		T13	9
valid_sources[0x28]	6165	1			T3	5		T13	4		T15	5
valid_sources[0x29]	23943	1			T3	3		T4	1		T15	10
valid_sources[0x2a]	6704	1			T3	5		T4	2		T13	4
valid_sources[0x2b]	6118	1			T3	3		T4	3		T5	5
valid_sources[0x2c]	6895	1			T3	4		T5	1		T13	1
valid_sources[0x2d]	6413	1			T3	2		T4	1		T13	2
valid_sources[0x2e]	6282	1			T3	2		T4	2		T15	6
valid_sources[0x2f]	6250	1			T3	3		T4	1		T13	5
valid_sources[0x30]	22945	1			T3	4		T4	1		T13	11
valid_sources[0x31]	7493	1			T4	1		T13	6		T15	9
valid_sources[0x32]	6999	1			T3	6		T4	2		T15	7
valid_sources[0x33]	6405	1			T13	3		T15	10		T16	8
valid_sources[0x34]	6173	1			T3	5		T12	1		T5	2
valid_sources[0x35]	6621	1			T3	3		T4	2		T13	2
valid_sources[0x36]	6976	1			T3	2		T4	2		T5	1
valid_sources[0x37]	6259	1			T2	2		T3	1		T4	2
valid_sources[0x38]	83079	1			T3	2		T4	2		T13	6
valid_sources[0x39]	6671	1			T3	3		T4	3		T5	2
valid_sources[0x3a]	5966	1			T3	8		T13	3		T15	7
valid_sources[0x3b]	9836	1			T4	1		T5	7		T13	6
valid_sources[0x3c]	6582	1			T3	3		T5	3		T13	1
valid_sources[0x3d]	7415	1			T3	9		T5	1		T15	8
valid_sources[0x3e]	6463	1			T3	1		T13	22		T15	5
valid_sources[0x3f]	6491	1			T3	2		T15	8		T16	2
valid_sources[0x40]	31205	1			T3	6		T13	1		T15	12
valid_sources[0x41]	6321	1			T4	5		T5	3		T15	13
valid_sources[0x42]	6139	1			T3	5		T13	5		T15	8
valid_sources[0x43]	6697	1			T15	2		T16	7		T11	331
valid_sources[0x44]	9465	1			T3	3		T4	1		T13	11
valid_sources[0x45]	7130	1			T3	6		T12	1		T13	7
valid_sources[0x46]	6765	1			T3	2		T13	6		T15	8
valid_sources[0x47]	6465	1			T3	3		T4	1		T15	5
valid_sources[0x48]	5906	1			T3	8		T4	1		T13	3
valid_sources[0x49]	5856	1			T3	7		T4	1		T13	7
valid_sources[0x4a]	8230	1			T3	9		T4	1		T13	4
valid_sources[0x4b]	17476	1			T3	1		T4	1		T5	2
valid_sources[0x4c]	6941	1			T3	2		T4	2		T5	9
valid_sources[0x4d]	32364	1			T3	5		T13	6		T15	6
valid_sources[0x4e]	6311	1			T3	9		T4	2		T13	28
valid_sources[0x4f]	6463	1			T3	1		T4	1		T13	1
valid_sources[0x50]	6422	1			T3	5		T4	3		T15	10
valid_sources[0x51]	6514	1			T3	5		T4	1		T13	4
valid_sources[0x52]	7435	1			T4	1		T13	4		T15	7
valid_sources[0x53]	8676	1			T2	1		T3	4		T15	15
valid_sources[0x54]	5985	1			T3	3		T13	4		T15	8
valid_sources[0x55]	6430	1			T3	3		T4	1		T5	6
valid_sources[0x56]	6081	1			T3	2		T15	2		T16	3
valid_sources[0x57]	7036	1			T3	6		T13	7		T15	9
valid_sources[0x58]	16369	1			T3	3		T13	5		T15	6
valid_sources[0x59]	6410	1			T3	4		T13	17		T15	5
valid_sources[0x5a]	6275	1			T4	1		T15	6		T16	4
valid_sources[0x5b]	12083	1			T3	2		T4	1		T15	8
valid_sources[0x5c]	6326	1			T3	3		T4	6		T15	7
valid_sources[0x5d]	6220	1			T4	4		T15	6		T16	5
valid_sources[0x5e]	6556	1			T3	6		T4	2		T15	3
valid_sources[0x5f]	6421	1			T3	5		T4	1		T5	4
valid_sources[0x60]	6300	1			T15	13		T16	2		T11	338
valid_sources[0x61]	6575	1			T3	9		T4	1		T13	3
valid_sources[0x62]	8197	1			T3	9		T13	6		T15	14
valid_sources[0x63]	7206	1			T3	8		T4	4		T5	1
valid_sources[0x64]	6218	1			T3	1		T13	5		T15	7
valid_sources[0x65]	6428	1			T3	3		T4	2		T13	5
valid_sources[0x66]	6109	1			T5	2		T13	5		T15	10
valid_sources[0x67]	6469	1			T3	4		T4	1		T13	5
valid_sources[0x68]	7527	1			T3	7		T13	7		T15	9
valid_sources[0x69]	10950	1			T3	1		T4	2		T13	6
valid_sources[0x6a]	6111	1			T3	4		T13	2		T15	7
valid_sources[0x6b]	7536	1			T3	5		T13	8		T15	4
valid_sources[0x6c]	9391	1			T3	5		T15	6		T11	400
valid_sources[0x6d]	6400	1			T3	3		T4	1		T12	1
valid_sources[0x6e]	6025	1			T3	5		T4	1		T13	6
valid_sources[0x6f]	6923	1			T4	1		T5	2		T15	9
valid_sources[0x70]	6553	1			T3	3		T5	4		T15	1
valid_sources[0x71]	6151	1			T3	4		T13	2		T15	6
valid_sources[0x72]	6339	1			T3	3		T4	2		T12	1
valid_sources[0x73]	7880	1			T3	3		T4	1		T5	1
valid_sources[0x74]	8814	1			T3	5		T13	3		T15	7
valid_sources[0x75]	6192	1			T3	7		T5	5		T15	6
valid_sources[0x76]	7734	1			T3	3		T4	4		T13	3
valid_sources[0x77]	6307	1			T3	1		T13	28		T15	10
valid_sources[0x78]	6257	1			T3	8		T4	1		T13	2
valid_sources[0x79]	6255	1			T3	5		T13	1		T15	4
valid_sources[0x7a]	6348	1			T3	2		T13	3		T15	8
valid_sources[0x7b]	7459	1			T3	1		T4	1		T13	2
valid_sources[0x7c]	8334	1			T3	3		T5	7		T15	5
valid_sources[0x7d]	6493	1			T3	6		T4	1		T5	1
valid_sources[0x7e]	6292	1			T3	4		T4	2		T5	4
valid_sources[0x7f]	7191	1			T3	10		T5	3		T15	3
valid_sources[0x80]	50057	1			T3	3		T13	3		T15	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1075680

1

T1

5

T2

1

T3

252

values[0x0]

all_enables

biggest_size

143951

1

T1

4

T3

176

T4

44

values[0x1]

all_enables

biggest_size

142920

1

T1

4

T3

194

T4

37