Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	92396166	14355	0	0
claim_transition_if_regwen_rd_A	92396166	919	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92396166	14355	0	0
T7	22319	0	0	0
T8	39767	0	0	0
T11	351746	3	0	0
T17	0	2	0	0
T18	204788	0	0	0
T19	24263	0	0	0
T21	114257	0	0	0
T31	2305	0	0	0
T32	1465	0	0	0
T33	923	0	0	0
T34	33388	0	0	0
T42	0	2	0	0
T43	0	6	0	0
T86	0	1	0	0
T92	0	1	0	0
T101	0	7	0	0
T140	0	2	0	0
T141	0	2	0	0
T142	0	1	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92396166	919	0	0
T7	22319	0	0	0
T8	39767	0	0	0
T11	351746	4	0	0
T18	204788	0	0	0
T19	24263	0	0	0
T21	114257	0	0	0
T31	2305	0	0	0
T32	1465	0	0	0
T33	923	0	0	0
T34	33388	0	0	0
T42	0	7	0	0
T86	0	7	0	0
T100	0	1	0	0
T105	0	7	0	0
T111	0	4	0	0
T113	0	4	0	0
T142	0	6	0	0
T143	0	9	0	0
T144	0	14	0	0