Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

111237497

1

T1

2764

T2

34689

T3

5806

auto[1]

1463477

1

T2

1078

T3

297

T11

99

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

111255591

1

T1

2764

T2

34885

T3

5905

auto[1]

1445383

1

T2

882

T3

198

T4

594

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7485396	1			T1	736		T2	1857		T3	1313
auto[IdleSt]	21242852	1			T1	662		T2	17744		T3	1286
auto[ClkMuxSt]	35951	1			T1	6		T2	20		T3	7
auto[CntIncrSt]	35667	1			T1	6		T2	20		T3	7
auto[CntProgSt]	1472833	1			T1	64		T2	250		T3	276
auto[TransCheckSt]	28019	1			T1	6		T3	7		T4	44
auto[TokenHashSt]	49663562	1			T1	299		T3	399		T4	2882
auto[FlashRmaSt]	36889	1			T1	6		T3	7		T4	57
auto[TokenCheck0St]	12889	1			T1	6		T3	7		T4	13
auto[TokenCheck1St]	9679	1			T1	6		T3	7		T4	8
auto[TransProgSt]	390529	1			T1	57		T3	381		T4	206
auto[PostTransSt]	12479397	1			T1	731		T2	8603		T3	1135
auto[ScrapSt]	140527	1			T1	179		T5	899		T14	3
auto[EscalateSt]	7084922	1			T2	7273		T3	886		T4	5534
auto[InvalidSt]	12579673	1			T3	385		T11	1429		T5	225422

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2189	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12579673	1			T3	385		T11	1429		T5	225422
EscalateSt	7084922	1			T2	7273		T3	886		T4	5534
ScrapSt	140527	1			T1	179		T5	899		T14	3
PostTransSt	12479397	1			T1	731		T2	8603		T3	1135
TransProgSt	390529	1			T1	57		T3	381		T4	206
TokenCheck1St	9679	1			T1	6		T3	7		T4	8
TokenCheck0St	12889	1			T1	6		T3	7		T4	13
FlashRmaSt	36889	1			T1	6		T3	7		T4	57
TokenHashSt	49663562	1			T1	299		T3	399		T4	2882
TransCheckSt	28019	1			T1	6		T3	7		T4	44
CntProgSt	1472833	1			T1	64		T2	250		T3	276
CntIncrSt	35667	1			T1	6		T2	20		T3	7
ClkMuxSt	35951	1			T1	6		T2	20		T3	7
IdleSt	21242852	1			T1	662		T2	17744		T3	1286
ResetSt	7485396	1			T1	736		T2	1857		T3	1313
arcs[ResetSt=>IdleSt]	55776	1			T1	7		T2	21		T3	15
arcs[IdleSt=>ScrapSt]	293	1			T1	1		T5	1		T14	1
arcs[IdleSt=>ClkMuxSt]	35714	1			T1	6		T2	20		T3	7
arcs[ClkMuxSt=>CntIncrSt]	35667	1			T1	6		T2	20		T3	7
arcs[CntIncrSt=>PostTransSt]	1822	1			T4	8		T5	9		T16	8
arcs[CntIncrSt=>CntProgSt]	33792	1			T1	6		T2	20		T3	7
arcs[CntProgSt=>PostTransSt]	4719	1			T2	20		T4	6		T12	10
arcs[CntProgSt=>TransCheckSt]	28019	1			T1	6		T3	7		T4	44
arcs[TransCheckSt=>PostTransSt]	3840	1			T4	8		T5	11		T13	43
arcs[TransCheckSt=>TokenHashSt]	24042	1			T1	6		T3	7		T4	36
arcs[TokenHashSt=>PostTransSt]	10347	1			T4	23		T5	27		T13	14
arcs[TokenHashSt=>FlashRmaSt]	12959	1			T1	6		T3	7		T4	13
arcs[FlashRmaSt=>TokenCheck0St]	12889	1			T1	6		T3	7		T4	13
arcs[TokenCheck0St=>PostTransSt]	3187	1			T4	5		T5	12		T13	24
arcs[TokenCheck0St=>TokenCheck1St]	9679	1			T1	6		T3	7		T4	8
arcs[TokenCheck1St=>PostTransSt]	626	1			T5	2		T13	11		T17	2
arcs[TransProgSt=>PostTransSt]	8188	1			T1	6		T3	7		T4	8
arcs[IdleSt=>EscalateSt]	193	1			T14	7		T57	10		T55	13
arcs[ClkMuxSt=>EscalateSt]	47	1			T54	1		T55	2		T56	3
arcs[CntIncrSt=>EscalateSt]	53	1			T57	1		T54	3		T58	2
arcs[CntProgSt=>EscalateSt]	1054	1			T14	34		T57	30		T54	11
arcs[TransCheckSt=>EscalateSt]	137	1			T54	10		T55	9		T56	10
arcs[TokenHashSt=>EscalateSt]	736	1			T14	12		T57	4		T54	43
arcs[FlashRmaSt=>EscalateSt]	70	1			T14	1		T57	1		T54	4
arcs[TokenCheck0St=>EscalateSt]	23	1			T57	1		T55	2		T56	1
arcs[TokenCheck1St=>EscalateSt]	138	1			T14	5		T57	6		T54	1
arcs[TransProgSt=>EscalateSt]	727	1			T14	17		T57	21		T54	9
arcs[PostTransSt=>EscalateSt]	4976	1			T2	20		T4	6		T12	10
arcs[InvalidSt=>EscalateSt]	15240	1			T3	5		T11	8		T5	112

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7485199	1			T1	736		T2	1857		T3	1313
auto[0]	auto[IdleSt]	21242724	1			T1	662		T2	17744		T3	1286
auto[0]	auto[ClkMuxSt]	35917	1			T1	6		T2	20		T3	7
auto[0]	auto[CntIncrSt]	35634	1			T1	6		T2	20		T3	7
auto[0]	auto[CntProgSt]	1472113	1			T1	64		T2	250		T3	276
auto[0]	auto[TransCheckSt]	27920	1			T1	6		T3	7		T4	44
auto[0]	auto[TokenHashSt]	49663076	1			T1	299		T3	399		T4	2882
auto[0]	auto[FlashRmaSt]	36847	1			T1	6		T3	7		T4	57
auto[0]	auto[TokenCheck0St]	12877	1			T1	6		T3	7		T4	13
auto[0]	auto[TokenCheck1St]	9584	1			T1	6		T3	7		T4	8
auto[0]	auto[TransProgSt]	390029	1			T1	57		T3	381		T4	206
auto[0]	auto[PostTransSt]	12476875	1			T1	731		T2	8592		T3	1135
auto[0]	auto[ScrapSt]	140490	1			T1	179		T5	899		T14	2
auto[0]	auto[EscalateSt]	5634013	1			T2	6206		T3	592		T4	5534
auto[0]	auto[InvalidSt]	12572010	1			T3	382		T11	1428		T5	225376
auto[1]	auto[ResetSt]	197	1			T14	8		T57	8		T54	3
auto[1]	auto[IdleSt]	128	1			T14	3		T57	6		T55	6
auto[1]	auto[ClkMuxSt]	34	1			T55	2		T56	3		T220	2
auto[1]	auto[CntIncrSt]	33	1			T57	1		T54	3		T58	1
auto[1]	auto[CntProgSt]	720	1			T14	25		T57	19		T54	6
auto[1]	auto[TransCheckSt]	99	1			T54	7		T55	6		T56	9
auto[1]	auto[TokenHashSt]	486	1			T14	9		T57	3		T54	31
auto[1]	auto[FlashRmaSt]	42	1			T54	4		T58	3		T221	1
auto[1]	auto[TokenCheck0St]	12	1			T55	1		T222	1		T220	1
auto[1]	auto[TokenCheck1St]	95	1			T14	4		T57	3		T58	1
auto[1]	auto[TransProgSt]	500	1			T14	8		T57	15		T54	4
auto[1]	auto[PostTransSt]	2522	1			T2	11		T12	4		T5	4
auto[1]	auto[ScrapSt]	37	1			T14	1		T54	1		T56	1
auto[1]	auto[EscalateSt]	1450909	1			T2	1067		T3	294		T11	98
auto[1]	auto[InvalidSt]	7663	1			T3	3		T11	1		T5	46

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7485207	1			T1	736		T2	1857		T3	1313
auto[0]	auto[IdleSt]	21242718	1			T1	662		T2	17744		T3	1286
auto[0]	auto[ClkMuxSt]	35923	1			T1	6		T2	20		T3	7
auto[0]	auto[CntIncrSt]	35636	1			T1	6		T2	20		T3	7
auto[0]	auto[CntProgSt]	1472134	1			T1	64		T2	250		T3	276
auto[0]	auto[TransCheckSt]	27928	1			T1	6		T3	7		T4	44
auto[0]	auto[TokenHashSt]	49663092	1			T1	299		T3	399		T4	2882
auto[0]	auto[FlashRmaSt]	36840	1			T1	6		T3	7		T4	57
auto[0]	auto[TokenCheck0St]	12872	1			T1	6		T3	7		T4	13
auto[0]	auto[TokenCheck1St]	9581	1			T1	6		T3	7		T4	8
auto[0]	auto[TransProgSt]	390055	1			T1	57		T3	381		T4	206
auto[0]	auto[PostTransSt]	12476863	1			T1	731		T2	8594		T3	1135
auto[0]	auto[ScrapSt]	140479	1			T1	179		T5	899		T14	2
auto[0]	auto[EscalateSt]	5651978	1			T2	6400		T3	690		T4	4946
auto[0]	auto[InvalidSt]	12572096	1			T3	383		T11	1422		T5	225356
auto[1]	auto[ResetSt]	189	1			T14	5		T57	11		T54	2
auto[1]	auto[IdleSt]	134	1			T14	4		T57	4		T55	12
auto[1]	auto[ClkMuxSt]	28	1			T54	1		T56	1		T222	1
auto[1]	auto[CntIncrSt]	31	1			T54	1		T58	1		T55	1
auto[1]	auto[CntProgSt]	699	1			T14	20		T57	19		T54	8
auto[1]	auto[TransCheckSt]	91	1			T54	8		T55	6		T56	6
auto[1]	auto[TokenHashSt]	470	1			T14	7		T57	2		T54	27
auto[1]	auto[FlashRmaSt]	49	1			T14	1		T57	1		T54	2
auto[1]	auto[TokenCheck0St]	17	1			T57	1		T55	1		T56	1
auto[1]	auto[TokenCheck1St]	98	1			T14	5		T57	6		T54	1
auto[1]	auto[TransProgSt]	474	1			T14	11		T57	12		T54	5
auto[1]	auto[PostTransSt]	2534	1			T2	9		T4	6		T12	6
auto[1]	auto[ScrapSt]	48	1			T14	1		T57	1		T54	1
auto[1]	auto[EscalateSt]	1432944	1			T2	873		T3	196		T4	588
auto[1]	auto[InvalidSt]	7577	1			T3	2		T11	7		T5	66