ASSERT | PROPERTIES | SEQUENCES | |
Total | 392 | 0 | 10 |
Category 0 | 392 | 0 | 10 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 392 | 0 | 10 |
Severity 0 | 392 | 0 | 10 |
NUMBER | PERCENT | |
Total Number | 392 | 100.00 |
Uncovered | 4 | 1.02 |
Success | 388 | 98.98 |
Failure | 0 | 0.00 |
Incomplete | 7 | 1.79 |
Without Attempts | 0 | 0.00 |
NUMBER | PERCENT | |
Total Number | 10 | 100.00 |
Uncovered | 0 | 0.00 |
All Matches | 10 | 100.00 |
First Matches | 10 | 100.00 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.FpvSecCmCtrlKmacIfFsmCheck_A | 0 | 0 | 107173492 | 0 | 0 | 0 | |
tb.dut.FpvSecCmCtrlLcFsmCheck_A | 0 | 0 | 107386021 | 0 | 0 | 0 | |
tb.dut.FpvSecCmTapRegWeOnehotCheck_A | 0 | 0 | 110232904 | 0 | 0 | 0 | |
tb.dut.u_lc_ctrl_fsm.SecCmCFILinear_A | 0 | 0 | 110232904 | 0 | 0 | 2128 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.u_lc_ctrl_fsm.ClkBypStaysOnOnceAsserted_A | 0 | 0 | 110232904 | 5753532 | 0 | 64 | |
tb.dut.u_lc_ctrl_fsm.EscStaysOnOnceAsserted_A | 0 | 0 | 110232904 | 19714430 | 0 | 12 | |
tb.dut.u_lc_ctrl_fsm.FlashRmaStaysOnOnceAsserted_A | 0 | 0 | 110232904 | 564873 | 0 | 11 | |
tb.dut.u_lc_ctrl_fsm.SecCmCFILinear_A | 0 | 0 | 110232904 | 0 | 0 | 2128 | |
tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack.gen_flops.OutputDelay_A | 0 | 0 | 109859153 | 105440081 | 0 | 2391 | |
tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack.gen_flops.OutputDelay_A | 0 | 0 | 109859153 | 105440081 | 0 | 2391 | |
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_flops.OutputDelay_A | 0 | 0 | 109996807 | 105575934 | 0 | 2403 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 112701323 | 769 | 769 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 112701323 | 63 | 63 | 1 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 112701323 | 64 | 64 | 1 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 112701323 | 22 | 22 | 1 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 112701323 | 29 | 29 | 1 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 112701323 | 16 | 16 | 1 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 112701323 | 25 | 25 | 1 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 112701323 | 2871 | 2871 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 112701323 | 8780 | 8780 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 112701323 | 875540 | 875540 | 297 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 112701323 | 769 | 769 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 112701323 | 63 | 63 | 1 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 112701323 | 64 | 64 | 1 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 112701323 | 22 | 22 | 1 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 112701323 | 29 | 29 | 1 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 112701323 | 16 | 16 | 1 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 112701323 | 25 | 25 | 1 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 112701323 | 2871 | 2871 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 112701323 | 8780 | 8780 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 112701323 | 875540 | 875540 | 297 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |