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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.28 97.92 95.84 93.38 100.00 98.52 99.00 96.29


Total test records in report: 993
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T817 /workspace/coverage/default/32.lc_ctrl_sec_token_digest.477725110 Jul 03 05:04:48 PM PDT 24 Jul 03 05:04:59 PM PDT 24 1805479701 ps
T818 /workspace/coverage/default/39.lc_ctrl_sec_mubi.2466837098 Jul 03 05:05:14 PM PDT 24 Jul 03 05:05:33 PM PDT 24 2217933342 ps
T819 /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1481617843 Jul 03 05:04:35 PM PDT 24 Jul 03 05:04:36 PM PDT 24 26612738 ps
T149 /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.4266479933 Jul 03 05:04:08 PM PDT 24 Jul 03 05:11:45 PM PDT 24 58965670270 ps
T820 /workspace/coverage/default/33.lc_ctrl_jtag_access.1609693439 Jul 03 05:04:46 PM PDT 24 Jul 03 05:05:00 PM PDT 24 545705134 ps
T821 /workspace/coverage/default/24.lc_ctrl_errors.3239638223 Jul 03 05:04:26 PM PDT 24 Jul 03 05:04:40 PM PDT 24 368607737 ps
T822 /workspace/coverage/default/3.lc_ctrl_prog_failure.940600101 Jul 03 05:03:54 PM PDT 24 Jul 03 05:03:57 PM PDT 24 56879215 ps
T823 /workspace/coverage/default/40.lc_ctrl_errors.283568456 Jul 03 05:05:18 PM PDT 24 Jul 03 05:05:33 PM PDT 24 1027990523 ps
T824 /workspace/coverage/default/40.lc_ctrl_state_post_trans.1625171670 Jul 03 05:05:16 PM PDT 24 Jul 03 05:05:24 PM PDT 24 112009507 ps
T825 /workspace/coverage/default/5.lc_ctrl_state_failure.4087403529 Jul 03 05:03:50 PM PDT 24 Jul 03 05:04:27 PM PDT 24 817596480 ps
T826 /workspace/coverage/default/23.lc_ctrl_prog_failure.2315695110 Jul 03 05:04:22 PM PDT 24 Jul 03 05:04:26 PM PDT 24 74935365 ps
T90 /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.2653132270 Jul 03 05:04:35 PM PDT 24 Jul 03 05:20:45 PM PDT 24 198427947278 ps
T827 /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2319969291 Jul 03 05:04:11 PM PDT 24 Jul 03 05:04:18 PM PDT 24 621481908 ps
T828 /workspace/coverage/default/14.lc_ctrl_jtag_smoke.2748351292 Jul 03 05:04:19 PM PDT 24 Jul 03 05:04:37 PM PDT 24 9376181933 ps
T829 /workspace/coverage/default/21.lc_ctrl_errors.2223214320 Jul 03 05:04:23 PM PDT 24 Jul 03 05:04:35 PM PDT 24 188342222 ps
T830 /workspace/coverage/default/42.lc_ctrl_sec_mubi.4241795019 Jul 03 05:05:18 PM PDT 24 Jul 03 05:05:42 PM PDT 24 1987300175 ps
T831 /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.4129452339 Jul 03 05:03:48 PM PDT 24 Jul 03 05:04:09 PM PDT 24 1087802456 ps
T832 /workspace/coverage/default/37.lc_ctrl_alert_test.167798345 Jul 03 05:05:19 PM PDT 24 Jul 03 05:05:22 PM PDT 24 60149791 ps
T833 /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1136558060 Jul 03 05:04:07 PM PDT 24 Jul 03 05:04:10 PM PDT 24 322429126 ps
T834 /workspace/coverage/default/17.lc_ctrl_state_post_trans.2865419902 Jul 03 05:04:24 PM PDT 24 Jul 03 05:04:35 PM PDT 24 121950070 ps
T107 /workspace/coverage/default/1.lc_ctrl_sec_cm.925037831 Jul 03 05:03:42 PM PDT 24 Jul 03 05:04:24 PM PDT 24 229323850 ps
T835 /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3177545209 Jul 03 05:04:42 PM PDT 24 Jul 03 05:04:51 PM PDT 24 431195755 ps
T836 /workspace/coverage/default/16.lc_ctrl_smoke.3156778952 Jul 03 05:04:31 PM PDT 24 Jul 03 05:04:35 PM PDT 24 197287223 ps
T837 /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1155194413 Jul 03 05:03:45 PM PDT 24 Jul 03 05:04:03 PM PDT 24 1097538920 ps
T838 /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.4270566593 Jul 03 05:04:24 PM PDT 24 Jul 03 05:04:34 PM PDT 24 3264068900 ps
T839 /workspace/coverage/default/38.lc_ctrl_sec_mubi.3339255782 Jul 03 05:05:16 PM PDT 24 Jul 03 05:05:41 PM PDT 24 1189634615 ps
T840 /workspace/coverage/default/39.lc_ctrl_prog_failure.2957026670 Jul 03 05:05:05 PM PDT 24 Jul 03 05:05:08 PM PDT 24 104882712 ps
T841 /workspace/coverage/default/46.lc_ctrl_smoke.103872187 Jul 03 05:05:19 PM PDT 24 Jul 03 05:05:24 PM PDT 24 32420395 ps
T842 /workspace/coverage/default/25.lc_ctrl_sec_token_mux.4162604753 Jul 03 05:04:51 PM PDT 24 Jul 03 05:05:02 PM PDT 24 1304933849 ps
T843 /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2109427248 Jul 03 05:04:05 PM PDT 24 Jul 03 05:04:19 PM PDT 24 670016130 ps
T844 /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.741122401 Jul 03 05:05:11 PM PDT 24 Jul 03 05:05:13 PM PDT 24 11020022 ps
T845 /workspace/coverage/default/5.lc_ctrl_state_post_trans.2271373900 Jul 03 05:03:59 PM PDT 24 Jul 03 05:04:07 PM PDT 24 351792947 ps
T846 /workspace/coverage/default/49.lc_ctrl_stress_all.2185673354 Jul 03 05:05:16 PM PDT 24 Jul 03 05:07:28 PM PDT 24 4131376221 ps
T847 /workspace/coverage/default/22.lc_ctrl_errors.2053633960 Jul 03 05:04:48 PM PDT 24 Jul 03 05:04:58 PM PDT 24 1188696053 ps
T848 /workspace/coverage/default/5.lc_ctrl_alert_test.2372255282 Jul 03 05:04:02 PM PDT 24 Jul 03 05:04:03 PM PDT 24 33033923 ps
T849 /workspace/coverage/default/23.lc_ctrl_alert_test.3878212904 Jul 03 05:04:42 PM PDT 24 Jul 03 05:04:44 PM PDT 24 44504590 ps
T850 /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3290555460 Jul 03 05:05:12 PM PDT 24 Jul 03 05:05:23 PM PDT 24 1258263114 ps
T851 /workspace/coverage/default/15.lc_ctrl_alert_test.3465012187 Jul 03 05:04:25 PM PDT 24 Jul 03 05:04:28 PM PDT 24 35649512 ps
T852 /workspace/coverage/default/43.lc_ctrl_state_failure.3476121478 Jul 03 05:05:14 PM PDT 24 Jul 03 05:05:42 PM PDT 24 356535710 ps
T853 /workspace/coverage/default/13.lc_ctrl_alert_test.1886610471 Jul 03 05:04:20 PM PDT 24 Jul 03 05:04:23 PM PDT 24 18548398 ps
T854 /workspace/coverage/default/18.lc_ctrl_state_failure.3498368316 Jul 03 05:04:22 PM PDT 24 Jul 03 05:04:56 PM PDT 24 298174679 ps
T855 /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1225407483 Jul 03 05:05:12 PM PDT 24 Jul 03 05:05:24 PM PDT 24 346328870 ps
T856 /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1231178222 Jul 03 05:04:21 PM PDT 24 Jul 03 05:04:34 PM PDT 24 1505045300 ps
T857 /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2885131369 Jul 03 05:04:44 PM PDT 24 Jul 03 05:05:00 PM PDT 24 2985918344 ps
T858 /workspace/coverage/default/27.lc_ctrl_sec_token_digest.4221734309 Jul 03 05:04:41 PM PDT 24 Jul 03 05:04:54 PM PDT 24 318509352 ps
T859 /workspace/coverage/default/20.lc_ctrl_security_escalation.2843883932 Jul 03 05:04:28 PM PDT 24 Jul 03 05:04:40 PM PDT 24 3439420399 ps
T216 /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3825014725 Jul 03 05:03:42 PM PDT 24 Jul 03 05:03:43 PM PDT 24 18048088 ps
T860 /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.626766104 Jul 03 05:04:21 PM PDT 24 Jul 03 05:04:29 PM PDT 24 6971713957 ps
T861 /workspace/coverage/default/11.lc_ctrl_errors.3100716985 Jul 03 05:04:20 PM PDT 24 Jul 03 05:04:31 PM PDT 24 854112970 ps
T862 /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2580172405 Jul 03 05:05:17 PM PDT 24 Jul 03 05:05:20 PM PDT 24 49206610 ps
T863 /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.108388427 Jul 03 05:04:25 PM PDT 24 Jul 03 05:04:29 PM PDT 24 34781931 ps
T864 /workspace/coverage/default/17.lc_ctrl_jtag_smoke.342099167 Jul 03 05:04:32 PM PDT 24 Jul 03 05:04:42 PM PDT 24 2472751029 ps
T865 /workspace/coverage/default/15.lc_ctrl_state_post_trans.1763120868 Jul 03 05:04:21 PM PDT 24 Jul 03 05:04:30 PM PDT 24 49062189 ps
T866 /workspace/coverage/default/13.lc_ctrl_state_failure.2574469607 Jul 03 05:04:23 PM PDT 24 Jul 03 05:04:47 PM PDT 24 223118135 ps
T867 /workspace/coverage/default/47.lc_ctrl_stress_all.3825895304 Jul 03 05:05:14 PM PDT 24 Jul 03 05:06:39 PM PDT 24 6228328756 ps
T868 /workspace/coverage/default/39.lc_ctrl_alert_test.1718389709 Jul 03 05:05:11 PM PDT 24 Jul 03 05:05:13 PM PDT 24 51053689 ps
T869 /workspace/coverage/default/34.lc_ctrl_stress_all.2386010020 Jul 03 05:05:11 PM PDT 24 Jul 03 05:10:05 PM PDT 24 32465542769 ps
T870 /workspace/coverage/default/14.lc_ctrl_jtag_errors.725187413 Jul 03 05:04:20 PM PDT 24 Jul 03 05:04:47 PM PDT 24 4454034395 ps
T117 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1584031198 Jul 03 06:27:13 PM PDT 24 Jul 03 06:27:15 PM PDT 24 45289057 ps
T110 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2211110121 Jul 03 06:27:18 PM PDT 24 Jul 03 06:27:21 PM PDT 24 1006883685 ps
T143 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.350557298 Jul 03 06:26:59 PM PDT 24 Jul 03 06:27:01 PM PDT 24 168686476 ps
T122 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1783294865 Jul 03 06:26:54 PM PDT 24 Jul 03 06:26:56 PM PDT 24 57844541 ps
T118 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3878869382 Jul 03 06:26:41 PM PDT 24 Jul 03 06:26:43 PM PDT 24 95026922 ps
T142 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2789608142 Jul 03 06:26:56 PM PDT 24 Jul 03 06:26:59 PM PDT 24 791687341 ps
T140 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3128138129 Jul 03 06:26:43 PM PDT 24 Jul 03 06:26:52 PM PDT 24 1019161946 ps
T141 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3771844942 Jul 03 06:26:45 PM PDT 24 Jul 03 06:26:47 PM PDT 24 53292510 ps
T113 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2343694252 Jul 03 06:27:10 PM PDT 24 Jul 03 06:27:11 PM PDT 24 22028811 ps
T150 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3563965102 Jul 03 06:26:53 PM PDT 24 Jul 03 06:26:56 PM PDT 24 508602067 ps
T111 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.4279644627 Jul 03 06:27:09 PM PDT 24 Jul 03 06:27:13 PM PDT 24 119186364 ps
T112 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2626988284 Jul 03 06:26:48 PM PDT 24 Jul 03 06:26:50 PM PDT 24 602592141 ps
T131 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3260537790 Jul 03 06:27:04 PM PDT 24 Jul 03 06:27:10 PM PDT 24 2157731318 ps
T151 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.160368545 Jul 03 06:27:11 PM PDT 24 Jul 03 06:27:13 PM PDT 24 87967569 ps
T871 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4007075059 Jul 03 06:26:55 PM PDT 24 Jul 03 06:26:57 PM PDT 24 273804066 ps
T152 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1022504762 Jul 03 06:26:51 PM PDT 24 Jul 03 06:26:53 PM PDT 24 70081358 ps
T872 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1075895070 Jul 03 06:26:53 PM PDT 24 Jul 03 06:26:58 PM PDT 24 1105073759 ps
T115 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3878600019 Jul 03 06:27:10 PM PDT 24 Jul 03 06:27:12 PM PDT 24 161605992 ps
T204 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1880992961 Jul 03 06:26:47 PM PDT 24 Jul 03 06:26:48 PM PDT 24 46609243 ps
T873 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.4020947345 Jul 03 06:26:54 PM PDT 24 Jul 03 06:26:57 PM PDT 24 131401392 ps
T173 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.870883851 Jul 03 06:27:17 PM PDT 24 Jul 03 06:27:19 PM PDT 24 25512997 ps
T116 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4004072688 Jul 03 06:26:57 PM PDT 24 Jul 03 06:26:59 PM PDT 24 156180472 ps
T205 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2065104267 Jul 03 06:26:50 PM PDT 24 Jul 03 06:26:52 PM PDT 24 16989576 ps
T119 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1737277831 Jul 03 06:26:45 PM PDT 24 Jul 03 06:26:49 PM PDT 24 752473044 ps
T874 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.244294974 Jul 03 06:27:10 PM PDT 24 Jul 03 06:27:15 PM PDT 24 143933360 ps
T875 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2099081748 Jul 03 06:26:35 PM PDT 24 Jul 03 06:26:40 PM PDT 24 810193022 ps
T206 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1364714316 Jul 03 06:27:03 PM PDT 24 Jul 03 06:27:04 PM PDT 24 17025475 ps
T128 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.922935417 Jul 03 06:27:15 PM PDT 24 Jul 03 06:27:18 PM PDT 24 1132381920 ps
T876 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2233899851 Jul 03 06:26:54 PM PDT 24 Jul 03 06:27:01 PM PDT 24 3221693239 ps
T877 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1516619262 Jul 03 06:27:06 PM PDT 24 Jul 03 06:27:08 PM PDT 24 778608971 ps
T174 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3207924130 Jul 03 06:27:04 PM PDT 24 Jul 03 06:27:08 PM PDT 24 266247192 ps
T207 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2353761837 Jul 03 06:27:16 PM PDT 24 Jul 03 06:27:18 PM PDT 24 48137897 ps
T120 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3252696397 Jul 03 06:27:12 PM PDT 24 Jul 03 06:27:15 PM PDT 24 319191131 ps
T878 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.923995364 Jul 03 06:26:38 PM PDT 24 Jul 03 06:26:39 PM PDT 24 93833254 ps
T879 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2553669384 Jul 03 06:27:17 PM PDT 24 Jul 03 06:27:19 PM PDT 24 16933868 ps
T880 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.4044898017 Jul 03 06:27:05 PM PDT 24 Jul 03 06:27:07 PM PDT 24 72352890 ps
T208 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3981536126 Jul 03 06:27:20 PM PDT 24 Jul 03 06:27:22 PM PDT 24 482262500 ps
T129 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3777178216 Jul 03 06:27:13 PM PDT 24 Jul 03 06:27:17 PM PDT 24 193239214 ps
T133 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2844200590 Jul 03 06:26:44 PM PDT 24 Jul 03 06:26:47 PM PDT 24 72330320 ps
T881 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.4259591435 Jul 03 06:27:15 PM PDT 24 Jul 03 06:27:17 PM PDT 24 108414343 ps
T121 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2328094748 Jul 03 06:26:50 PM PDT 24 Jul 03 06:26:54 PM PDT 24 90050837 ps
T882 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1720427729 Jul 03 06:27:13 PM PDT 24 Jul 03 06:28:03 PM PDT 24 9134688879 ps
T188 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2738335532 Jul 03 06:27:22 PM PDT 24 Jul 03 06:27:24 PM PDT 24 11343242 ps
T209 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1806781087 Jul 03 06:27:17 PM PDT 24 Jul 03 06:27:19 PM PDT 24 125853191 ps
T883 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3677300221 Jul 03 06:27:06 PM PDT 24 Jul 03 06:27:08 PM PDT 24 131308184 ps
T884 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1670498858 Jul 03 06:26:40 PM PDT 24 Jul 03 06:26:42 PM PDT 24 177835824 ps
T189 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.581507249 Jul 03 06:27:03 PM PDT 24 Jul 03 06:27:04 PM PDT 24 57221287 ps
T885 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1481473878 Jul 03 06:27:21 PM PDT 24 Jul 03 06:27:23 PM PDT 24 62562858 ps
T886 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3256061311 Jul 03 06:26:35 PM PDT 24 Jul 03 06:26:38 PM PDT 24 56242452 ps
T137 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1359601863 Jul 03 06:27:20 PM PDT 24 Jul 03 06:27:23 PM PDT 24 433006363 ps
T210 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.30130742 Jul 03 06:26:52 PM PDT 24 Jul 03 06:26:54 PM PDT 24 163400701 ps
T211 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1723861795 Jul 03 06:27:21 PM PDT 24 Jul 03 06:27:23 PM PDT 24 18468960 ps
T887 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1635411088 Jul 03 06:26:43 PM PDT 24 Jul 03 06:26:44 PM PDT 24 100048524 ps
T888 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2496549243 Jul 03 06:26:56 PM PDT 24 Jul 03 06:26:58 PM PDT 24 16119980 ps
T889 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3252291240 Jul 03 06:26:38 PM PDT 24 Jul 03 06:26:40 PM PDT 24 81829212 ps
T890 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1251008423 Jul 03 06:27:17 PM PDT 24 Jul 03 06:27:21 PM PDT 24 97440959 ps
T891 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1194892279 Jul 03 06:27:02 PM PDT 24 Jul 03 06:27:04 PM PDT 24 494263104 ps
T892 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2306847678 Jul 03 06:27:14 PM PDT 24 Jul 03 06:27:20 PM PDT 24 154885301 ps
T893 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1913145654 Jul 03 06:27:19 PM PDT 24 Jul 03 06:27:20 PM PDT 24 31081122 ps
T894 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3776584878 Jul 03 06:26:52 PM PDT 24 Jul 03 06:26:53 PM PDT 24 21801821 ps
T895 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.821783418 Jul 03 06:26:41 PM PDT 24 Jul 03 06:26:42 PM PDT 24 26781726 ps
T190 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1927575913 Jul 03 06:26:54 PM PDT 24 Jul 03 06:26:56 PM PDT 24 114588289 ps
T896 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3124513375 Jul 03 06:27:00 PM PDT 24 Jul 03 06:27:02 PM PDT 24 50595567 ps
T897 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1837840697 Jul 03 06:27:24 PM PDT 24 Jul 03 06:27:28 PM PDT 24 103986475 ps
T898 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2040812899 Jul 03 06:27:02 PM PDT 24 Jul 03 06:27:03 PM PDT 24 30891607 ps
T899 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4022400150 Jul 03 06:26:45 PM PDT 24 Jul 03 06:26:55 PM PDT 24 4007030547 ps
T900 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3780227815 Jul 03 06:26:45 PM PDT 24 Jul 03 06:26:47 PM PDT 24 33458245 ps
T134 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1469258325 Jul 03 06:26:59 PM PDT 24 Jul 03 06:27:01 PM PDT 24 91825473 ps
T901 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4174077120 Jul 03 06:26:57 PM PDT 24 Jul 03 06:27:08 PM PDT 24 1604597992 ps
T902 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2377886914 Jul 03 06:26:37 PM PDT 24 Jul 03 06:26:40 PM PDT 24 49614648 ps
T126 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.341994217 Jul 03 06:27:25 PM PDT 24 Jul 03 06:27:29 PM PDT 24 119398089 ps
T903 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.649192181 Jul 03 06:26:57 PM PDT 24 Jul 03 06:27:01 PM PDT 24 523144678 ps
T904 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1352132839 Jul 03 06:26:37 PM PDT 24 Jul 03 06:26:38 PM PDT 24 36443815 ps
T905 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3678096321 Jul 03 06:26:59 PM PDT 24 Jul 03 06:27:03 PM PDT 24 139311157 ps
T906 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.4203256555 Jul 03 06:27:00 PM PDT 24 Jul 03 06:27:02 PM PDT 24 40820882 ps
T907 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.353664401 Jul 03 06:26:50 PM PDT 24 Jul 03 06:26:52 PM PDT 24 110984488 ps
T908 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.509721760 Jul 03 06:26:51 PM PDT 24 Jul 03 06:27:38 PM PDT 24 2054643417 ps
T909 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3979397243 Jul 03 06:27:07 PM PDT 24 Jul 03 06:27:18 PM PDT 24 20893262533 ps
T910 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3967892201 Jul 03 06:26:50 PM PDT 24 Jul 03 06:26:52 PM PDT 24 20840839 ps
T911 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3847852098 Jul 03 06:26:46 PM PDT 24 Jul 03 06:26:48 PM PDT 24 44758308 ps
T912 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3473664895 Jul 03 06:26:38 PM PDT 24 Jul 03 06:26:40 PM PDT 24 88202118 ps
T913 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.813784625 Jul 03 06:27:21 PM PDT 24 Jul 03 06:27:22 PM PDT 24 16998241 ps
T914 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1086253901 Jul 03 06:26:46 PM PDT 24 Jul 03 06:26:49 PM PDT 24 56121365 ps
T915 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1869794155 Jul 03 06:26:42 PM PDT 24 Jul 03 06:26:45 PM PDT 24 91060598 ps
T916 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3292291955 Jul 03 06:26:49 PM PDT 24 Jul 03 06:26:50 PM PDT 24 60537087 ps
T917 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3220446784 Jul 03 06:27:11 PM PDT 24 Jul 03 06:27:12 PM PDT 24 75642820 ps
T918 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.810573031 Jul 03 06:27:15 PM PDT 24 Jul 03 06:27:17 PM PDT 24 20199424 ps
T919 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1104320931 Jul 03 06:26:51 PM PDT 24 Jul 03 06:26:52 PM PDT 24 50468452 ps
T920 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3188011436 Jul 03 06:27:04 PM PDT 24 Jul 03 06:27:07 PM PDT 24 1248925673 ps
T921 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.272481083 Jul 03 06:27:18 PM PDT 24 Jul 03 06:27:20 PM PDT 24 25752191 ps
T922 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2720421381 Jul 03 06:27:11 PM PDT 24 Jul 03 06:27:13 PM PDT 24 52972759 ps
T923 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.880416642 Jul 03 06:27:06 PM PDT 24 Jul 03 06:27:07 PM PDT 24 41105106 ps
T191 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.265991550 Jul 03 06:26:54 PM PDT 24 Jul 03 06:26:55 PM PDT 24 15498490 ps
T924 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3491437237 Jul 03 06:27:18 PM PDT 24 Jul 03 06:27:20 PM PDT 24 46694747 ps
T123 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.4164315256 Jul 03 06:27:08 PM PDT 24 Jul 03 06:27:12 PM PDT 24 165210447 ps
T192 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1909286081 Jul 03 06:27:11 PM PDT 24 Jul 03 06:27:13 PM PDT 24 12991761 ps
T925 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3368276306 Jul 03 06:26:44 PM PDT 24 Jul 03 06:26:46 PM PDT 24 246869922 ps
T926 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2199958626 Jul 03 06:27:15 PM PDT 24 Jul 03 06:27:17 PM PDT 24 29087280 ps
T927 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1009696400 Jul 03 06:26:45 PM PDT 24 Jul 03 06:26:47 PM PDT 24 123708782 ps
T928 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1832970813 Jul 03 06:26:44 PM PDT 24 Jul 03 06:27:08 PM PDT 24 10834943861 ps
T929 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2062435590 Jul 03 06:26:47 PM PDT 24 Jul 03 06:26:50 PM PDT 24 359397017 ps
T930 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3487529901 Jul 03 06:26:55 PM PDT 24 Jul 03 06:26:58 PM PDT 24 582877467 ps
T931 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3084999265 Jul 03 06:26:59 PM PDT 24 Jul 03 06:27:05 PM PDT 24 889028759 ps
T932 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.161083160 Jul 03 06:27:14 PM PDT 24 Jul 03 06:27:16 PM PDT 24 285556764 ps
T933 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3692361813 Jul 03 06:27:25 PM PDT 24 Jul 03 06:27:26 PM PDT 24 22333143 ps
T193 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2512556462 Jul 03 06:26:53 PM PDT 24 Jul 03 06:26:54 PM PDT 24 22003300 ps
T934 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2949061604 Jul 03 06:27:14 PM PDT 24 Jul 03 06:27:22 PM PDT 24 2075364906 ps
T935 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.4251510418 Jul 03 06:27:20 PM PDT 24 Jul 03 06:27:22 PM PDT 24 25693630 ps
T936 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2949586760 Jul 03 06:26:45 PM PDT 24 Jul 03 06:26:47 PM PDT 24 21870581 ps
T937 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1338127794 Jul 03 06:27:02 PM PDT 24 Jul 03 06:27:07 PM PDT 24 445278157 ps
T938 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2947442879 Jul 03 06:26:55 PM PDT 24 Jul 03 06:27:01 PM PDT 24 192445228 ps
T939 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2372146372 Jul 03 06:27:00 PM PDT 24 Jul 03 06:27:02 PM PDT 24 114504829 ps
T940 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.4166883154 Jul 03 06:27:19 PM PDT 24 Jul 03 06:27:21 PM PDT 24 62702822 ps
T941 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.321761296 Jul 03 06:26:53 PM PDT 24 Jul 03 06:26:55 PM PDT 24 275669907 ps
T942 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3307142622 Jul 03 06:27:05 PM PDT 24 Jul 03 06:27:09 PM PDT 24 502177040 ps
T194 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2946992571 Jul 03 06:27:15 PM PDT 24 Jul 03 06:27:16 PM PDT 24 23058520 ps
T943 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2857407650 Jul 03 06:26:56 PM PDT 24 Jul 03 06:26:57 PM PDT 24 94067162 ps
T195 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2497096113 Jul 03 06:27:14 PM PDT 24 Jul 03 06:27:16 PM PDT 24 16126511 ps
T944 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3088475110 Jul 03 06:26:49 PM PDT 24 Jul 03 06:26:55 PM PDT 24 1115754999 ps
T945 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.173681198 Jul 03 06:27:03 PM PDT 24 Jul 03 06:27:05 PM PDT 24 29338014 ps
T946 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3561101503 Jul 03 06:26:40 PM PDT 24 Jul 03 06:26:41 PM PDT 24 49696092 ps
T196 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3481328257 Jul 03 06:26:44 PM PDT 24 Jul 03 06:26:45 PM PDT 24 16353955 ps
T130 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.299901656 Jul 03 06:27:16 PM PDT 24 Jul 03 06:27:21 PM PDT 24 153782335 ps
T947 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.153554723 Jul 03 06:27:20 PM PDT 24 Jul 03 06:27:22 PM PDT 24 29785802 ps
T948 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1013688643 Jul 03 06:27:01 PM PDT 24 Jul 03 06:27:04 PM PDT 24 366228201 ps
T949 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.4173550054 Jul 03 06:27:02 PM PDT 24 Jul 03 06:27:06 PM PDT 24 481043683 ps
T127 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1976344311 Jul 03 06:27:13 PM PDT 24 Jul 03 06:27:17 PM PDT 24 410635357 ps
T950 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.604864540 Jul 03 06:26:44 PM PDT 24 Jul 03 06:26:46 PM PDT 24 150991684 ps
T951 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.805563960 Jul 03 06:26:59 PM PDT 24 Jul 03 06:27:00 PM PDT 24 29705419 ps
T135 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1280987121 Jul 03 06:27:16 PM PDT 24 Jul 03 06:27:19 PM PDT 24 288592006 ps
T952 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2911842535 Jul 03 06:27:25 PM PDT 24 Jul 03 06:27:27 PM PDT 24 36503101 ps
T953 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1301981465 Jul 03 06:26:58 PM PDT 24 Jul 03 06:27:00 PM PDT 24 38743474 ps
T132 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.681553631 Jul 03 06:26:43 PM PDT 24 Jul 03 06:26:47 PM PDT 24 79734810 ps
T954 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2310885239 Jul 03 06:26:54 PM PDT 24 Jul 03 06:26:56 PM PDT 24 28328101 ps
T955 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2046597565 Jul 03 06:26:50 PM PDT 24 Jul 03 06:26:55 PM PDT 24 194739626 ps
T956 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2838706283 Jul 03 06:27:09 PM PDT 24 Jul 03 06:27:11 PM PDT 24 97082431 ps
T957 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3889745543 Jul 03 06:27:11 PM PDT 24 Jul 03 06:27:12 PM PDT 24 19590102 ps
T958 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.4184999481 Jul 03 06:26:42 PM PDT 24 Jul 03 06:26:48 PM PDT 24 511902767 ps
T197 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2166753688 Jul 03 06:27:15 PM PDT 24 Jul 03 06:27:16 PM PDT 24 23820697 ps
T959 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1849591996 Jul 03 06:26:47 PM PDT 24 Jul 03 06:26:49 PM PDT 24 599593818 ps
T138 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.835956668 Jul 03 06:27:25 PM PDT 24 Jul 03 06:27:28 PM PDT 24 76740254 ps
T960 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1928932426 Jul 03 06:27:09 PM PDT 24 Jul 03 06:27:11 PM PDT 24 196724087 ps
T961 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1998364828 Jul 03 06:27:07 PM PDT 24 Jul 03 06:27:09 PM PDT 24 29570941 ps
T962 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1705388915 Jul 03 06:27:04 PM PDT 24 Jul 03 06:27:06 PM PDT 24 29410236 ps
T963 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2855331891 Jul 03 06:27:09 PM PDT 24 Jul 03 06:27:10 PM PDT 24 98889585 ps
T964 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.764409363 Jul 03 06:26:41 PM PDT 24 Jul 03 06:26:43 PM PDT 24 108966625 ps
T965 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.385631401 Jul 03 06:27:07 PM PDT 24 Jul 03 06:27:08 PM PDT 24 46790638 ps
T966 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.826709512 Jul 03 06:27:06 PM PDT 24 Jul 03 06:27:07 PM PDT 24 32544936 ps
T967 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1975875557 Jul 03 06:26:58 PM PDT 24 Jul 03 06:27:00 PM PDT 24 46761011 ps
T968 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.4174420182 Jul 03 06:26:42 PM PDT 24 Jul 03 06:26:45 PM PDT 24 93967283 ps
T969 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2790791418 Jul 03 06:27:11 PM PDT 24 Jul 03 06:27:14 PM PDT 24 295017908 ps
T970 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1631681151 Jul 03 06:27:14 PM PDT 24 Jul 03 06:27:16 PM PDT 24 20142565 ps
T199 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.644758008 Jul 03 06:26:41 PM PDT 24 Jul 03 06:26:42 PM PDT 24 43333337 ps
T971 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1961545366 Jul 03 06:26:40 PM PDT 24 Jul 03 06:26:41 PM PDT 24 96056419 ps
T972 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3587569099 Jul 03 06:26:49 PM PDT 24 Jul 03 06:26:51 PM PDT 24 237559956 ps
T973 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3860226061 Jul 03 06:27:10 PM PDT 24 Jul 03 06:27:14 PM PDT 24 480837184 ps
T200 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.760164172 Jul 03 06:27:16 PM PDT 24 Jul 03 06:27:17 PM PDT 24 34013759 ps
T974 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.964188988 Jul 03 06:26:55 PM PDT 24 Jul 03 06:26:57 PM PDT 24 422391201 ps
T201 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1111940371 Jul 03 06:26:56 PM PDT 24 Jul 03 06:26:57 PM PDT 24 39515037 ps
T975 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2794087995 Jul 03 06:27:22 PM PDT 24 Jul 03 06:27:23 PM PDT 24 36822398 ps
T976 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1704426044 Jul 03 06:27:01 PM PDT 24 Jul 03 06:27:13 PM PDT 24 828504857 ps
T124 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2023161420 Jul 03 06:27:03 PM PDT 24 Jul 03 06:27:08 PM PDT 24 111449586 ps
T977 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3313335516 Jul 03 06:27:21 PM PDT 24 Jul 03 06:27:22 PM PDT 24 41452008 ps
T978 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3841394589 Jul 03 06:26:36 PM PDT 24 Jul 03 06:26:38 PM PDT 24 920283858 ps
T979 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3361274955 Jul 03 06:27:00 PM PDT 24 Jul 03 06:27:10 PM PDT 24 1783365013 ps
T980 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1572876198 Jul 03 06:27:20 PM PDT 24 Jul 03 06:27:23 PM PDT 24 178726000 ps
T981 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2374885634 Jul 03 06:27:18 PM PDT 24 Jul 03 06:27:20 PM PDT 24 220132815 ps
T982 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1067209461 Jul 03 06:26:58 PM PDT 24 Jul 03 06:27:00 PM PDT 24 27105312 ps
T983 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3853461073 Jul 03 06:27:11 PM PDT 24 Jul 03 06:27:16 PM PDT 24 134278010 ps
T984 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2079029166 Jul 03 06:26:49 PM PDT 24 Jul 03 06:26:51 PM PDT 24 44556457 ps
T985 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3506740049 Jul 03 06:26:41 PM PDT 24 Jul 03 06:26:44 PM PDT 24 102182754 ps
T986 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.854947074 Jul 03 06:27:13 PM PDT 24 Jul 03 06:27:14 PM PDT 24 156442503 ps
T987 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.4109315010 Jul 03 06:27:08 PM PDT 24 Jul 03 06:27:09 PM PDT 24 47266835 ps
T988 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3192658657 Jul 03 06:27:09 PM PDT 24 Jul 03 06:27:14 PM PDT 24 1542445263 ps
T989 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.792925575 Jul 03 06:27:11 PM PDT 24 Jul 03 06:27:13 PM PDT 24 176142099 ps
T202 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2330898131 Jul 03 06:26:44 PM PDT 24 Jul 03 06:26:45 PM PDT 24 22987922 ps
T990 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2692115302 Jul 03 06:27:10 PM PDT 24 Jul 03 06:27:12 PM PDT 24 135990010 ps
T136 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1472038719 Jul 03 06:27:09 PM PDT 24 Jul 03 06:27:12 PM PDT 24 159723855 ps
T139 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2981175646 Jul 03 06:27:10 PM PDT 24 Jul 03 06:27:12 PM PDT 24 51190298 ps
T991 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1214533700 Jul 03 06:27:16 PM PDT 24 Jul 03 06:27:17 PM PDT 24 28811768 ps
T198 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.4231059164 Jul 03 06:26:55 PM PDT 24 Jul 03 06:26:56 PM PDT 24 62699105 ps
T992 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1012819078 Jul 03 06:26:33 PM PDT 24 Jul 03 06:26:53 PM PDT 24 833314444 ps
T125 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.4222561841 Jul 03 06:26:38 PM PDT 24 Jul 03 06:26:41 PM PDT 24 382780099 ps
T993 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3189673717 Jul 03 06:27:23 PM PDT 24 Jul 03 06:27:28 PM PDT 24 1263305190 ps
T203 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3590326986 Jul 03 06:27:17 PM PDT 24 Jul 03 06:27:19 PM PDT 24 150522656 ps

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.383266550
Short name T5
Test name
Test status
Simulation time 29054268315 ps
CPU time 161.72 seconds
Started Jul 03 05:04:36 PM PDT 24
Finished Jul 03 05:07:19 PM PDT 24
Peak memory 283696 kb
Host smart-fa2d51be-9342-4cfd-a2e0-5e7af3d904e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383266550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.383266550
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.3432267964
Short name T57
Test name
Test status
Simulation time 601844035 ps
CPU time 12.97 seconds
Started Jul 03 05:04:54 PM PDT 24
Finished Jul 03 05:05:08 PM PDT 24
Peak memory 225948 kb
Host smart-c79120c4-0460-4f30-bac7-d22eee6152d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432267964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3432267964
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.990456964
Short name T45
Test name
Test status
Simulation time 3162212567 ps
CPU time 13.91 seconds
Started Jul 03 05:05:20 PM PDT 24
Finished Jul 03 05:05:37 PM PDT 24
Peak memory 218488 kb
Host smart-43a3946a-b611-44cb-9f84-b3bb7ad3a5ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990456964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.990456964
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.2929271058
Short name T17
Test name
Test status
Simulation time 32564836002 ps
CPU time 225.81 seconds
Started Jul 03 05:05:00 PM PDT 24
Finished Jul 03 05:08:47 PM PDT 24
Peak memory 322704 kb
Host smart-8e51c050-aa95-409a-8a88-8ebba74dd245
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2929271058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.2929271058
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.3413096111
Short name T97
Test name
Test status
Simulation time 77506105532 ps
CPU time 2616.54 seconds
Started Jul 03 05:05:17 PM PDT 24
Finished Jul 03 05:48:56 PM PDT 24
Peak memory 463828 kb
Host smart-8e3d6aa5-237c-414f-b1c4-eddf54385c15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3413096111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.3413096111
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.1704777059
Short name T54
Test name
Test status
Simulation time 624179821 ps
CPU time 9.61 seconds
Started Jul 03 05:05:03 PM PDT 24
Finished Jul 03 05:05:13 PM PDT 24
Peak memory 225988 kb
Host smart-17d2c203-1e19-4ff5-90f2-0e8d99b5d427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704777059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.1704777059
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.1207873413
Short name T35
Test name
Test status
Simulation time 2068859459 ps
CPU time 35.49 seconds
Started Jul 03 05:03:59 PM PDT 24
Finished Jul 03 05:04:35 PM PDT 24
Peak memory 269392 kb
Host smart-bd283e60-e183-45f9-a9e1-0ac622597f85
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207873413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.1207873413
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3260537790
Short name T131
Test name
Test status
Simulation time 2157731318 ps
CPU time 6.23 seconds
Started Jul 03 06:27:04 PM PDT 24
Finished Jul 03 06:27:10 PM PDT 24
Peak memory 219048 kb
Host smart-b249d2b9-2c33-4b2c-960e-7ce4bcba99cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326053
7790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3260537790
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2211110121
Short name T110
Test name
Test status
Simulation time 1006883685 ps
CPU time 3.11 seconds
Started Jul 03 06:27:18 PM PDT 24
Finished Jul 03 06:27:21 PM PDT 24
Peak memory 222472 kb
Host smart-ff954d01-d299-4dde-b1fc-06f20845ecde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211110121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2211110121
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1565018569
Short name T13
Test name
Test status
Simulation time 667672620 ps
CPU time 9.67 seconds
Started Jul 03 05:04:11 PM PDT 24
Finished Jul 03 05:04:22 PM PDT 24
Peak memory 218196 kb
Host smart-80f9243b-c7de-48c9-9423-0e4001fea939
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565018569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.1
565018569
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.1639724524
Short name T158
Test name
Test status
Simulation time 394053407 ps
CPU time 10.74 seconds
Started Jul 03 05:04:30 PM PDT 24
Finished Jul 03 05:04:42 PM PDT 24
Peak memory 225944 kb
Host smart-aec0152a-1083-46d1-9cb8-8e2c7b40a312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639724524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1639724524
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.4105575752
Short name T7
Test name
Test status
Simulation time 379439079 ps
CPU time 5.31 seconds
Started Jul 03 05:04:18 PM PDT 24
Finished Jul 03 05:04:23 PM PDT 24
Peak memory 217232 kb
Host smart-47db66bf-3458-4250-ad2b-dc3de4cb25c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105575752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.4105575752
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3481328257
Short name T196
Test name
Test status
Simulation time 16353955 ps
CPU time 1 seconds
Started Jul 03 06:26:44 PM PDT 24
Finished Jul 03 06:26:45 PM PDT 24
Peak memory 209300 kb
Host smart-fd495608-8c5d-48c0-b2a6-008cc3c1274c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481328257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.3481328257
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1000370146
Short name T93
Test name
Test status
Simulation time 151119582 ps
CPU time 1.01 seconds
Started Jul 03 05:04:53 PM PDT 24
Finished Jul 03 05:04:54 PM PDT 24
Peak memory 208920 kb
Host smart-cda431fa-6389-4377-9798-de1dff4511c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000370146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1000370146
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.89377499
Short name T22
Test name
Test status
Simulation time 61766381716 ps
CPU time 1078.69 seconds
Started Jul 03 05:04:14 PM PDT 24
Finished Jul 03 05:22:14 PM PDT 24
Peak memory 447632 kb
Host smart-91e9f90c-5f61-4216-aee0-690785e09229
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=89377499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.89377499
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2377886914
Short name T902
Test name
Test status
Simulation time 49614648 ps
CPU time 3.32 seconds
Started Jul 03 06:26:37 PM PDT 24
Finished Jul 03 06:26:40 PM PDT 24
Peak memory 217692 kb
Host smart-a19c24b4-db46-49cb-9f1f-55a89f126ce1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377886914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.2377886914
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.341994217
Short name T126
Test name
Test status
Simulation time 119398089 ps
CPU time 3.14 seconds
Started Jul 03 06:27:25 PM PDT 24
Finished Jul 03 06:27:29 PM PDT 24
Peak memory 222080 kb
Host smart-8bcb411a-8ab3-4df9-9ba5-91dddb5a4bb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341994217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.341994217
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.3573269584
Short name T23
Test name
Test status
Simulation time 269030524 ps
CPU time 10.68 seconds
Started Jul 03 05:03:31 PM PDT 24
Finished Jul 03 05:03:42 PM PDT 24
Peak memory 217636 kb
Host smart-07ce4e20-7820-4fc4-8300-7641a3138140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573269584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3573269584
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2971794606
Short name T557
Test name
Test status
Simulation time 8366913954 ps
CPU time 60.14 seconds
Started Jul 03 05:04:09 PM PDT 24
Finished Jul 03 05:05:09 PM PDT 24
Peak memory 218252 kb
Host smart-d6f0365f-57e0-4aa4-a65c-0f0b2b6d0a39
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971794606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2971794606
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.681553631
Short name T132
Test name
Test status
Simulation time 79734810 ps
CPU time 2.81 seconds
Started Jul 03 06:26:43 PM PDT 24
Finished Jul 03 06:26:47 PM PDT 24
Peak memory 222412 kb
Host smart-70a47856-2026-4fd2-807f-d43e6d7c606c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681553631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_e
rr.681553631
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.299901656
Short name T130
Test name
Test status
Simulation time 153782335 ps
CPU time 4.39 seconds
Started Jul 03 06:27:16 PM PDT 24
Finished Jul 03 06:27:21 PM PDT 24
Peak memory 217520 kb
Host smart-185213c3-395d-4291-af77-cc2fa51aab54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299901656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_
err.299901656
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2023161420
Short name T124
Test name
Test status
Simulation time 111449586 ps
CPU time 4.3 seconds
Started Jul 03 06:27:03 PM PDT 24
Finished Jul 03 06:27:08 PM PDT 24
Peak memory 217540 kb
Host smart-bea8a6a9-85ca-4513-822c-4f7b4a023a70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023161420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.2023161420
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3878869382
Short name T118
Test name
Test status
Simulation time 95026922 ps
CPU time 1.36 seconds
Started Jul 03 06:26:41 PM PDT 24
Finished Jul 03 06:26:43 PM PDT 24
Peak memory 209444 kb
Host smart-03c5b1ea-640f-4148-8b87-fd2a18d6a15b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878869382 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.3878869382
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1280987121
Short name T135
Test name
Test status
Simulation time 288592006 ps
CPU time 2.73 seconds
Started Jul 03 06:27:16 PM PDT 24
Finished Jul 03 06:27:19 PM PDT 24
Peak memory 222160 kb
Host smart-59081546-9adb-48db-a264-d3d5211337cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280987121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1280987121
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4004072688
Short name T116
Test name
Test status
Simulation time 156180472 ps
CPU time 1.67 seconds
Started Jul 03 06:26:57 PM PDT 24
Finished Jul 03 06:26:59 PM PDT 24
Peak memory 221644 kb
Host smart-55a61165-3cad-4dd1-98fd-28175377b6cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004072688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.4004072688
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3878600019
Short name T115
Test name
Test status
Simulation time 161605992 ps
CPU time 2.24 seconds
Started Jul 03 06:27:10 PM PDT 24
Finished Jul 03 06:27:12 PM PDT 24
Peak memory 217564 kb
Host smart-e2610c26-d737-410f-a204-afb7f3041e4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878600019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3878600019
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.2226423041
Short name T214
Test name
Test status
Simulation time 10940135 ps
CPU time 0.91 seconds
Started Jul 03 05:03:35 PM PDT 24
Finished Jul 03 05:03:37 PM PDT 24
Peak memory 209196 kb
Host smart-4e4441b0-e18d-4f73-8df8-cd30cdb2f3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226423041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.2226423041
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1094090452
Short name T296
Test name
Test status
Simulation time 12262518 ps
CPU time 0.87 seconds
Started Jul 03 05:03:42 PM PDT 24
Finished Jul 03 05:03:44 PM PDT 24
Peak memory 211964 kb
Host smart-4522dce3-75f7-43c8-a320-0d434a08eba5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094090452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.1094090452
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1374706200
Short name T438
Test name
Test status
Simulation time 2849897010 ps
CPU time 6.74 seconds
Started Jul 03 05:04:17 PM PDT 24
Finished Jul 03 05:04:24 PM PDT 24
Peak memory 224884 kb
Host smart-651b8b16-3b5c-4982-a4ef-6f6d44116395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374706200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1374706200
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.60687687
Short name T219
Test name
Test status
Simulation time 11722726 ps
CPU time 0.79 seconds
Started Jul 03 05:03:34 PM PDT 24
Finished Jul 03 05:03:36 PM PDT 24
Peak memory 208728 kb
Host smart-0705e657-a0f2-4dc1-ba63-38b19942d71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60687687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.60687687
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.1049798476
Short name T218
Test name
Test status
Simulation time 105931454 ps
CPU time 0.82 seconds
Started Jul 03 05:04:13 PM PDT 24
Finished Jul 03 05:04:14 PM PDT 24
Peak memory 208876 kb
Host smart-78a9b867-2717-4bb8-b0ea-6cbf082025e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049798476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.1049798476
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.877949693
Short name T217
Test name
Test status
Simulation time 14526477 ps
CPU time 0.82 seconds
Started Jul 03 05:04:17 PM PDT 24
Finished Jul 03 05:04:24 PM PDT 24
Peak memory 208692 kb
Host smart-5ebd87d5-29ac-4d43-b7d6-ea82654f63e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877949693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.877949693
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.827285564
Short name T48
Test name
Test status
Simulation time 1568212437 ps
CPU time 14.92 seconds
Started Jul 03 05:03:55 PM PDT 24
Finished Jul 03 05:04:11 PM PDT 24
Peak memory 225928 kb
Host smart-0608dc43-3cff-4dc0-83cf-1a4347930a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827285564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.827285564
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2328094748
Short name T121
Test name
Test status
Simulation time 90050837 ps
CPU time 3.07 seconds
Started Jul 03 06:26:50 PM PDT 24
Finished Jul 03 06:26:54 PM PDT 24
Peak memory 217512 kb
Host smart-f51b1baa-ebfc-4ba3-8c1b-9447f5a27225
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328094748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2328094748
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2981175646
Short name T139
Test name
Test status
Simulation time 51190298 ps
CPU time 1.93 seconds
Started Jul 03 06:27:10 PM PDT 24
Finished Jul 03 06:27:12 PM PDT 24
Peak memory 221820 kb
Host smart-baa61d69-38e5-4323-a093-be90867d4e16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981175646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2981175646
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.1421029398
Short name T50
Test name
Test status
Simulation time 5153493596 ps
CPU time 112.92 seconds
Started Jul 03 05:04:24 PM PDT 24
Finished Jul 03 05:06:23 PM PDT 24
Peak memory 267384 kb
Host smart-e4da7860-b06c-494c-8dc4-e240f8736c3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421029398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.1421029398
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.1853299960
Short name T15
Test name
Test status
Simulation time 461885272 ps
CPU time 18.61 seconds
Started Jul 03 05:05:16 PM PDT 24
Finished Jul 03 05:05:36 PM PDT 24
Peak memory 250924 kb
Host smart-612264c0-7a65-4e9e-98ae-034ed086763d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853299960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.1853299960
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.490564317
Short name T24
Test name
Test status
Simulation time 1320496296 ps
CPU time 7.17 seconds
Started Jul 03 05:03:33 PM PDT 24
Finished Jul 03 05:03:40 PM PDT 24
Peak memory 217656 kb
Host smart-cd6af6cc-81f3-4ec2-a754-a3c2f275f478
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490564317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.490564317
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.923995364
Short name T878
Test name
Test status
Simulation time 93833254 ps
CPU time 0.99 seconds
Started Jul 03 06:26:38 PM PDT 24
Finished Jul 03 06:26:39 PM PDT 24
Peak memory 209416 kb
Host smart-26d2b51a-a9aa-4e49-af0a-9a68b1ea4243
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923995364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing
.923995364
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3252291240
Short name T889
Test name
Test status
Simulation time 81829212 ps
CPU time 1.33 seconds
Started Jul 03 06:26:38 PM PDT 24
Finished Jul 03 06:26:40 PM PDT 24
Peak memory 217360 kb
Host smart-e9f29101-7980-4dbe-bf51-a1f8fe254945
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252291240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3252291240
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.644758008
Short name T199
Test name
Test status
Simulation time 43333337 ps
CPU time 0.88 seconds
Started Jul 03 06:26:41 PM PDT 24
Finished Jul 03 06:26:42 PM PDT 24
Peak memory 209772 kb
Host smart-c62831f1-960d-4a0e-bec7-bed5d0344364
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644758008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset
.644758008
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.764409363
Short name T964
Test name
Test status
Simulation time 108966625 ps
CPU time 1.25 seconds
Started Jul 03 06:26:41 PM PDT 24
Finished Jul 03 06:26:43 PM PDT 24
Peak memory 217732 kb
Host smart-8de28d60-9c4b-4d94-86c8-fb4d11a0f672
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764409363 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.764409363
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.821783418
Short name T895
Test name
Test status
Simulation time 26781726 ps
CPU time 0.84 seconds
Started Jul 03 06:26:41 PM PDT 24
Finished Jul 03 06:26:42 PM PDT 24
Peak memory 208688 kb
Host smart-07018fa5-456b-45bf-bb03-5c8de42b4cf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821783418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.821783418
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1670498858
Short name T884
Test name
Test status
Simulation time 177835824 ps
CPU time 1.9 seconds
Started Jul 03 06:26:40 PM PDT 24
Finished Jul 03 06:26:42 PM PDT 24
Peak memory 209200 kb
Host smart-0e2e7a20-a132-4446-bef9-e4d711e4a307
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670498858 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1670498858
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2099081748
Short name T875
Test name
Test status
Simulation time 810193022 ps
CPU time 4.48 seconds
Started Jul 03 06:26:35 PM PDT 24
Finished Jul 03 06:26:40 PM PDT 24
Peak memory 208884 kb
Host smart-0dbf1f12-d6a2-4809-b3e7-1569341c30f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099081748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.2099081748
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1012819078
Short name T992
Test name
Test status
Simulation time 833314444 ps
CPU time 19.68 seconds
Started Jul 03 06:26:33 PM PDT 24
Finished Jul 03 06:26:53 PM PDT 24
Peak memory 209328 kb
Host smart-cc9941f1-f6ce-47b6-9638-fb256e56d866
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012819078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1012819078
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3841394589
Short name T978
Test name
Test status
Simulation time 920283858 ps
CPU time 1.84 seconds
Started Jul 03 06:26:36 PM PDT 24
Finished Jul 03 06:26:38 PM PDT 24
Peak memory 210912 kb
Host smart-87dc3f84-285b-4b91-af3c-ce0e99f9d714
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841394589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3841394589
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3473664895
Short name T912
Test name
Test status
Simulation time 88202118 ps
CPU time 2.19 seconds
Started Jul 03 06:26:38 PM PDT 24
Finished Jul 03 06:26:40 PM PDT 24
Peak memory 217640 kb
Host smart-fcd8e23d-4158-450f-be27-e9c09a06d5ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347366
4895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3473664895
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3256061311
Short name T886
Test name
Test status
Simulation time 56242452 ps
CPU time 2 seconds
Started Jul 03 06:26:35 PM PDT 24
Finished Jul 03 06:26:38 PM PDT 24
Peak memory 209264 kb
Host smart-43c795c7-6e92-4a27-9e0e-a811c81d8a00
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256061311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3256061311
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1352132839
Short name T904
Test name
Test status
Simulation time 36443815 ps
CPU time 1.09 seconds
Started Jul 03 06:26:37 PM PDT 24
Finished Jul 03 06:26:38 PM PDT 24
Peak memory 209452 kb
Host smart-8cfd7b8d-21ce-4e87-b57b-265a6c09d05e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352132839 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.1352132839
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3561101503
Short name T946
Test name
Test status
Simulation time 49696092 ps
CPU time 1.03 seconds
Started Jul 03 06:26:40 PM PDT 24
Finished Jul 03 06:26:41 PM PDT 24
Peak memory 217572 kb
Host smart-62e27e55-f465-49ba-b38a-f52c83b84bbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561101503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3561101503
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.4222561841
Short name T125
Test name
Test status
Simulation time 382780099 ps
CPU time 2.76 seconds
Started Jul 03 06:26:38 PM PDT 24
Finished Jul 03 06:26:41 PM PDT 24
Peak memory 222160 kb
Host smart-6302c915-12c5-4643-8054-2b2d275b3d99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222561841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.4222561841
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1961545366
Short name T971
Test name
Test status
Simulation time 96056419 ps
CPU time 1.11 seconds
Started Jul 03 06:26:40 PM PDT 24
Finished Jul 03 06:26:41 PM PDT 24
Peak memory 209420 kb
Host smart-499b8e60-21f0-498b-9ce4-cfed68fdc846
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961545366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.1961545366
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2949586760
Short name T936
Test name
Test status
Simulation time 21870581 ps
CPU time 1.31 seconds
Started Jul 03 06:26:45 PM PDT 24
Finished Jul 03 06:26:47 PM PDT 24
Peak memory 208600 kb
Host smart-34b4c1b7-9a80-48fa-9d0c-1451224e51cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949586760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2949586760
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2330898131
Short name T202
Test name
Test status
Simulation time 22987922 ps
CPU time 1.15 seconds
Started Jul 03 06:26:44 PM PDT 24
Finished Jul 03 06:26:45 PM PDT 24
Peak memory 210576 kb
Host smart-e7abb8bb-45eb-4b38-80aa-e3e6c5100d92
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330898131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.2330898131
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1086253901
Short name T914
Test name
Test status
Simulation time 56121365 ps
CPU time 2.12 seconds
Started Jul 03 06:26:46 PM PDT 24
Finished Jul 03 06:26:49 PM PDT 24
Peak memory 217644 kb
Host smart-21ff72ba-7014-45d8-a895-3b4f6a5c8280
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086253901 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1086253901
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1635411088
Short name T887
Test name
Test status
Simulation time 100048524 ps
CPU time 1.22 seconds
Started Jul 03 06:26:43 PM PDT 24
Finished Jul 03 06:26:44 PM PDT 24
Peak memory 208620 kb
Host smart-c5e59664-d3ad-4b81-b55d-7da5994b20be
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635411088 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1635411088
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.4184999481
Short name T958
Test name
Test status
Simulation time 511902767 ps
CPU time 6.13 seconds
Started Jul 03 06:26:42 PM PDT 24
Finished Jul 03 06:26:48 PM PDT 24
Peak memory 208972 kb
Host smart-249a2552-61b9-4764-ad1f-4670006120ba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184999481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.4184999481
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1832970813
Short name T928
Test name
Test status
Simulation time 10834943861 ps
CPU time 22.84 seconds
Started Jul 03 06:26:44 PM PDT 24
Finished Jul 03 06:27:08 PM PDT 24
Peak memory 209380 kb
Host smart-cda2fa6b-fe5e-457e-9fce-1b066985e2b3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832970813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1832970813
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3368276306
Short name T925
Test name
Test status
Simulation time 246869922 ps
CPU time 2.29 seconds
Started Jul 03 06:26:44 PM PDT 24
Finished Jul 03 06:26:46 PM PDT 24
Peak memory 217452 kb
Host smart-de58bdec-db5d-4005-a043-1030d4fdd564
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368276306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.3368276306
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1869794155
Short name T915
Test name
Test status
Simulation time 91060598 ps
CPU time 2.86 seconds
Started Jul 03 06:26:42 PM PDT 24
Finished Jul 03 06:26:45 PM PDT 24
Peak memory 219300 kb
Host smart-bee265ad-f8ea-4788-a46f-2971d139f2e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186979
4155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1869794155
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.4174420182
Short name T968
Test name
Test status
Simulation time 93967283 ps
CPU time 2.88 seconds
Started Jul 03 06:26:42 PM PDT 24
Finished Jul 03 06:26:45 PM PDT 24
Peak memory 209288 kb
Host smart-fbda371a-f0de-4f78-b91a-e96cd03e59b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174420182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.4174420182
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3506740049
Short name T985
Test name
Test status
Simulation time 102182754 ps
CPU time 1.99 seconds
Started Jul 03 06:26:41 PM PDT 24
Finished Jul 03 06:26:44 PM PDT 24
Peak memory 209372 kb
Host smart-62a6844f-f519-49cf-9671-75f25b308549
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506740049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3506740049
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1009696400
Short name T927
Test name
Test status
Simulation time 123708782 ps
CPU time 1.65 seconds
Started Jul 03 06:26:45 PM PDT 24
Finished Jul 03 06:26:47 PM PDT 24
Peak memory 217028 kb
Host smart-3c2fa6e6-690c-4799-959a-fd08ded62e39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009696400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1009696400
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2692115302
Short name T990
Test name
Test status
Simulation time 135990010 ps
CPU time 1.32 seconds
Started Jul 03 06:27:10 PM PDT 24
Finished Jul 03 06:27:12 PM PDT 24
Peak memory 221948 kb
Host smart-d600e374-75c7-47e2-acbc-c122a40e16fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692115302 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2692115302
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2497096113
Short name T195
Test name
Test status
Simulation time 16126511 ps
CPU time 0.92 seconds
Started Jul 03 06:27:14 PM PDT 24
Finished Jul 03 06:27:16 PM PDT 24
Peak memory 209252 kb
Host smart-d4bc9802-373d-4ed3-8049-a8c2473eef01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497096113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2497096113
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3889745543
Short name T957
Test name
Test status
Simulation time 19590102 ps
CPU time 1.49 seconds
Started Jul 03 06:27:11 PM PDT 24
Finished Jul 03 06:27:12 PM PDT 24
Peak memory 209328 kb
Host smart-9f7ceda7-c63b-46c2-b6ad-4773c7ef788c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889745543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3889745543
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3777178216
Short name T129
Test name
Test status
Simulation time 193239214 ps
CPU time 3.15 seconds
Started Jul 03 06:27:13 PM PDT 24
Finished Jul 03 06:27:17 PM PDT 24
Peak memory 217384 kb
Host smart-b6f23662-83d1-4c18-bef6-415d8ef1ed93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777178216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3777178216
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1472038719
Short name T136
Test name
Test status
Simulation time 159723855 ps
CPU time 2.28 seconds
Started Jul 03 06:27:09 PM PDT 24
Finished Jul 03 06:27:12 PM PDT 24
Peak memory 222228 kb
Host smart-25ed0088-9d0b-4e6a-b8ab-7a5202e741fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472038719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1472038719
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.810573031
Short name T918
Test name
Test status
Simulation time 20199424 ps
CPU time 1.37 seconds
Started Jul 03 06:27:15 PM PDT 24
Finished Jul 03 06:27:17 PM PDT 24
Peak memory 218156 kb
Host smart-96e6ff57-339a-4544-834a-73de9c87c67e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810573031 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.810573031
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2166753688
Short name T197
Test name
Test status
Simulation time 23820697 ps
CPU time 0.97 seconds
Started Jul 03 06:27:15 PM PDT 24
Finished Jul 03 06:27:16 PM PDT 24
Peak memory 208996 kb
Host smart-c26649d6-7d93-4729-8b18-d6353ae13faf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166753688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2166753688
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1631681151
Short name T970
Test name
Test status
Simulation time 20142565 ps
CPU time 1.28 seconds
Started Jul 03 06:27:14 PM PDT 24
Finished Jul 03 06:27:16 PM PDT 24
Peak memory 209372 kb
Host smart-186c155a-80af-42c8-b1e7-06b8efacf96f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631681151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1631681151
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2790791418
Short name T969
Test name
Test status
Simulation time 295017908 ps
CPU time 2.4 seconds
Started Jul 03 06:27:11 PM PDT 24
Finished Jul 03 06:27:14 PM PDT 24
Peak memory 217456 kb
Host smart-1360dc6a-3116-41a4-9d5c-8fef92bf5292
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790791418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2790791418
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.4259591435
Short name T881
Test name
Test status
Simulation time 108414343 ps
CPU time 1.46 seconds
Started Jul 03 06:27:15 PM PDT 24
Finished Jul 03 06:27:17 PM PDT 24
Peak memory 218904 kb
Host smart-bd8f1e1c-b981-41c1-917d-9d596358a488
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259591435 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.4259591435
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.760164172
Short name T200
Test name
Test status
Simulation time 34013759 ps
CPU time 1.08 seconds
Started Jul 03 06:27:16 PM PDT 24
Finished Jul 03 06:27:17 PM PDT 24
Peak memory 209324 kb
Host smart-be30e61c-6c13-4572-8494-b5944b48e298
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760164172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.760164172
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.854947074
Short name T986
Test name
Test status
Simulation time 156442503 ps
CPU time 1.1 seconds
Started Jul 03 06:27:13 PM PDT 24
Finished Jul 03 06:27:14 PM PDT 24
Peak memory 209444 kb
Host smart-d53abd70-aef3-4d1b-bb93-d8d6c2c43146
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854947074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_same_csr_outstanding.854947074
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3252696397
Short name T120
Test name
Test status
Simulation time 319191131 ps
CPU time 2.85 seconds
Started Jul 03 06:27:12 PM PDT 24
Finished Jul 03 06:27:15 PM PDT 24
Peak memory 217504 kb
Host smart-9d99d51c-8981-4077-8ccd-de1211eec4ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252696397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3252696397
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1976344311
Short name T127
Test name
Test status
Simulation time 410635357 ps
CPU time 2.75 seconds
Started Jul 03 06:27:13 PM PDT 24
Finished Jul 03 06:27:17 PM PDT 24
Peak memory 217676 kb
Host smart-2d55927b-0b21-4d2e-9d7c-ed15080fe4e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976344311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.1976344311
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.870883851
Short name T173
Test name
Test status
Simulation time 25512997 ps
CPU time 1.19 seconds
Started Jul 03 06:27:17 PM PDT 24
Finished Jul 03 06:27:19 PM PDT 24
Peak memory 218916 kb
Host smart-587781c6-4801-40d1-a2d9-92156c6ac04b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870883851 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.870883851
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3590326986
Short name T203
Test name
Test status
Simulation time 150522656 ps
CPU time 0.99 seconds
Started Jul 03 06:27:17 PM PDT 24
Finished Jul 03 06:27:19 PM PDT 24
Peak memory 209300 kb
Host smart-1f4d5bac-65a7-46cc-8760-9891c13b0e0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590326986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3590326986
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2353761837
Short name T207
Test name
Test status
Simulation time 48137897 ps
CPU time 1.54 seconds
Started Jul 03 06:27:16 PM PDT 24
Finished Jul 03 06:27:18 PM PDT 24
Peak memory 211328 kb
Host smart-61b44991-f714-4e4c-be3c-32a6a42dce56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353761837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2353761837
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2306847678
Short name T892
Test name
Test status
Simulation time 154885301 ps
CPU time 5.59 seconds
Started Jul 03 06:27:14 PM PDT 24
Finished Jul 03 06:27:20 PM PDT 24
Peak memory 217672 kb
Host smart-fc5a901d-97b5-4e6a-befb-a4b4d56b8738
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306847678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2306847678
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.922935417
Short name T128
Test name
Test status
Simulation time 1132381920 ps
CPU time 2.85 seconds
Started Jul 03 06:27:15 PM PDT 24
Finished Jul 03 06:27:18 PM PDT 24
Peak memory 222152 kb
Host smart-9a4d21ff-b9fa-4223-962f-26f71074f292
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922935417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_
err.922935417
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.4166883154
Short name T940
Test name
Test status
Simulation time 62702822 ps
CPU time 1.11 seconds
Started Jul 03 06:27:19 PM PDT 24
Finished Jul 03 06:27:21 PM PDT 24
Peak memory 217600 kb
Host smart-64a3f7f0-da34-440f-8364-cae791e1e9e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166883154 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.4166883154
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1214533700
Short name T991
Test name
Test status
Simulation time 28811768 ps
CPU time 0.85 seconds
Started Jul 03 06:27:16 PM PDT 24
Finished Jul 03 06:27:17 PM PDT 24
Peak memory 209268 kb
Host smart-fae1079c-5e51-4f46-9c8d-c9b24757b335
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214533700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1214533700
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3491437237
Short name T924
Test name
Test status
Simulation time 46694747 ps
CPU time 1.73 seconds
Started Jul 03 06:27:18 PM PDT 24
Finished Jul 03 06:27:20 PM PDT 24
Peak memory 217564 kb
Host smart-72c11ada-14ac-4340-afb2-ec01d08f8da1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491437237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.3491437237
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2199958626
Short name T926
Test name
Test status
Simulation time 29087280 ps
CPU time 2.13 seconds
Started Jul 03 06:27:15 PM PDT 24
Finished Jul 03 06:27:17 PM PDT 24
Peak memory 217672 kb
Host smart-320cb25c-c84c-4278-9937-ff11640c95fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199958626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2199958626
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2553669384
Short name T879
Test name
Test status
Simulation time 16933868 ps
CPU time 1.21 seconds
Started Jul 03 06:27:17 PM PDT 24
Finished Jul 03 06:27:19 PM PDT 24
Peak memory 217736 kb
Host smart-192bdd1d-bdc0-4782-ba33-a3e1ac21ca9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553669384 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2553669384
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2946992571
Short name T194
Test name
Test status
Simulation time 23058520 ps
CPU time 1.02 seconds
Started Jul 03 06:27:15 PM PDT 24
Finished Jul 03 06:27:16 PM PDT 24
Peak memory 209380 kb
Host smart-48ae967e-92b4-4db1-80b7-4eb61bcf3d74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946992571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2946992571
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1806781087
Short name T209
Test name
Test status
Simulation time 125853191 ps
CPU time 1.33 seconds
Started Jul 03 06:27:17 PM PDT 24
Finished Jul 03 06:27:19 PM PDT 24
Peak memory 209396 kb
Host smart-8ddda191-91e2-455c-b98d-4ba69683c267
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806781087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.1806781087
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1251008423
Short name T890
Test name
Test status
Simulation time 97440959 ps
CPU time 4.03 seconds
Started Jul 03 06:27:17 PM PDT 24
Finished Jul 03 06:27:21 PM PDT 24
Peak memory 217476 kb
Host smart-17158991-89b0-4497-9309-41972cdd1541
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251008423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1251008423
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1481473878
Short name T885
Test name
Test status
Simulation time 62562858 ps
CPU time 1.72 seconds
Started Jul 03 06:27:21 PM PDT 24
Finished Jul 03 06:27:23 PM PDT 24
Peak memory 217756 kb
Host smart-1b99be04-a13b-452a-89ee-1f226533bdd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481473878 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.1481473878
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2738335532
Short name T188
Test name
Test status
Simulation time 11343242 ps
CPU time 0.98 seconds
Started Jul 03 06:27:22 PM PDT 24
Finished Jul 03 06:27:24 PM PDT 24
Peak memory 209376 kb
Host smart-2fe6b9f9-d163-4381-adba-7c62c6898c03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738335532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.2738335532
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1723861795
Short name T211
Test name
Test status
Simulation time 18468960 ps
CPU time 1.22 seconds
Started Jul 03 06:27:21 PM PDT 24
Finished Jul 03 06:27:23 PM PDT 24
Peak memory 209372 kb
Host smart-746fb765-3c09-4cc9-af80-5e5d958d1669
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723861795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.1723861795
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2374885634
Short name T981
Test name
Test status
Simulation time 220132815 ps
CPU time 2.32 seconds
Started Jul 03 06:27:18 PM PDT 24
Finished Jul 03 06:27:20 PM PDT 24
Peak memory 217512 kb
Host smart-12d6fd61-fbee-4b4d-8d05-7a272a5e3b3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374885634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.2374885634
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.153554723
Short name T947
Test name
Test status
Simulation time 29785802 ps
CPU time 1.69 seconds
Started Jul 03 06:27:20 PM PDT 24
Finished Jul 03 06:27:22 PM PDT 24
Peak memory 219016 kb
Host smart-6e520e88-b5be-43bb-9a5a-e9142ddc4de1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153554723 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.153554723
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2794087995
Short name T975
Test name
Test status
Simulation time 36822398 ps
CPU time 0.94 seconds
Started Jul 03 06:27:22 PM PDT 24
Finished Jul 03 06:27:23 PM PDT 24
Peak memory 209256 kb
Host smart-7e13a130-ee7a-4ab8-8212-e8f17ba28afa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794087995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2794087995
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1913145654
Short name T893
Test name
Test status
Simulation time 31081122 ps
CPU time 1.41 seconds
Started Jul 03 06:27:19 PM PDT 24
Finished Jul 03 06:27:20 PM PDT 24
Peak memory 209296 kb
Host smart-4749d7c8-c657-4f1b-977b-6cd5a6df5718
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913145654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.1913145654
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1837840697
Short name T897
Test name
Test status
Simulation time 103986475 ps
CPU time 3.41 seconds
Started Jul 03 06:27:24 PM PDT 24
Finished Jul 03 06:27:28 PM PDT 24
Peak memory 217432 kb
Host smart-d3bf3a1d-883f-408f-b56b-56e1b5112e6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837840697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.1837840697
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1359601863
Short name T137
Test name
Test status
Simulation time 433006363 ps
CPU time 1.88 seconds
Started Jul 03 06:27:20 PM PDT 24
Finished Jul 03 06:27:23 PM PDT 24
Peak memory 221912 kb
Host smart-81251d8f-88a0-4fd8-9e0c-1c2c3c86b4e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359601863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1359601863
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.272481083
Short name T921
Test name
Test status
Simulation time 25752191 ps
CPU time 1.47 seconds
Started Jul 03 06:27:18 PM PDT 24
Finished Jul 03 06:27:20 PM PDT 24
Peak memory 220996 kb
Host smart-b0abdeb0-e1f1-4b26-95cf-39935ebae6bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272481083 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.272481083
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3313335516
Short name T977
Test name
Test status
Simulation time 41452008 ps
CPU time 0.89 seconds
Started Jul 03 06:27:21 PM PDT 24
Finished Jul 03 06:27:22 PM PDT 24
Peak memory 209272 kb
Host smart-8366e678-d8a2-4a51-a72a-e201fe592ac0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313335516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3313335516
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3981536126
Short name T208
Test name
Test status
Simulation time 482262500 ps
CPU time 1.37 seconds
Started Jul 03 06:27:20 PM PDT 24
Finished Jul 03 06:27:22 PM PDT 24
Peak memory 209372 kb
Host smart-68ad0df6-dd93-475f-86cf-19242b5a9c63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981536126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3981536126
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.4251510418
Short name T935
Test name
Test status
Simulation time 25693630 ps
CPU time 1.72 seconds
Started Jul 03 06:27:20 PM PDT 24
Finished Jul 03 06:27:22 PM PDT 24
Peak memory 217512 kb
Host smart-be1011b0-cbe3-4fae-9b04-f19f214c22e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251510418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.4251510418
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1572876198
Short name T980
Test name
Test status
Simulation time 178726000 ps
CPU time 2.03 seconds
Started Jul 03 06:27:20 PM PDT 24
Finished Jul 03 06:27:23 PM PDT 24
Peak memory 212940 kb
Host smart-e022d037-40af-4f11-9a19-343bffff3219
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572876198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1572876198
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2911842535
Short name T952
Test name
Test status
Simulation time 36503101 ps
CPU time 1.77 seconds
Started Jul 03 06:27:25 PM PDT 24
Finished Jul 03 06:27:27 PM PDT 24
Peak memory 222500 kb
Host smart-844aa3ec-634a-4262-8c6b-d04920d3f4b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911842535 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2911842535
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.813784625
Short name T913
Test name
Test status
Simulation time 16998241 ps
CPU time 1.14 seconds
Started Jul 03 06:27:21 PM PDT 24
Finished Jul 03 06:27:22 PM PDT 24
Peak memory 209316 kb
Host smart-ac04c5dd-d6e3-40aa-8417-35446112794e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813784625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.813784625
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3692361813
Short name T933
Test name
Test status
Simulation time 22333143 ps
CPU time 1.23 seconds
Started Jul 03 06:27:25 PM PDT 24
Finished Jul 03 06:27:26 PM PDT 24
Peak memory 211552 kb
Host smart-1f0f42f2-2fab-4bec-be6e-19210635a845
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692361813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3692361813
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3189673717
Short name T993
Test name
Test status
Simulation time 1263305190 ps
CPU time 4.99 seconds
Started Jul 03 06:27:23 PM PDT 24
Finished Jul 03 06:27:28 PM PDT 24
Peak memory 217604 kb
Host smart-2602622c-4db9-4add-9fb1-c92039662251
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189673717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3189673717
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.835956668
Short name T138
Test name
Test status
Simulation time 76740254 ps
CPU time 1.84 seconds
Started Jul 03 06:27:25 PM PDT 24
Finished Jul 03 06:27:28 PM PDT 24
Peak memory 221660 kb
Host smart-4db83dca-933c-4c96-a2f4-51f5589a51e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835956668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_
err.835956668
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3776584878
Short name T894
Test name
Test status
Simulation time 21801821 ps
CPU time 1.07 seconds
Started Jul 03 06:26:52 PM PDT 24
Finished Jul 03 06:26:53 PM PDT 24
Peak memory 209380 kb
Host smart-2e77f7cc-75d4-4454-9f16-bb0824c09010
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776584878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.3776584878
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3967892201
Short name T910
Test name
Test status
Simulation time 20840839 ps
CPU time 1.23 seconds
Started Jul 03 06:26:50 PM PDT 24
Finished Jul 03 06:26:52 PM PDT 24
Peak memory 209220 kb
Host smart-bc744b92-67e3-40bc-995f-89194a201e5c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967892201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.3967892201
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3847852098
Short name T911
Test name
Test status
Simulation time 44758308 ps
CPU time 1.15 seconds
Started Jul 03 06:26:46 PM PDT 24
Finished Jul 03 06:26:48 PM PDT 24
Peak memory 217848 kb
Host smart-481c2116-88d8-4aff-9adb-3c06806f584f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847852098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3847852098
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.353664401
Short name T907
Test name
Test status
Simulation time 110984488 ps
CPU time 1.75 seconds
Started Jul 03 06:26:50 PM PDT 24
Finished Jul 03 06:26:52 PM PDT 24
Peak memory 217728 kb
Host smart-4163db6a-b55d-45be-a325-0a781d3d890f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353664401 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.353664401
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1104320931
Short name T919
Test name
Test status
Simulation time 50468452 ps
CPU time 0.94 seconds
Started Jul 03 06:26:51 PM PDT 24
Finished Jul 03 06:26:52 PM PDT 24
Peak memory 209352 kb
Host smart-8f60e5af-d6d5-46e1-8d61-c22fd3437a06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104320931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1104320931
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.604864540
Short name T950
Test name
Test status
Simulation time 150991684 ps
CPU time 1.08 seconds
Started Jul 03 06:26:44 PM PDT 24
Finished Jul 03 06:26:46 PM PDT 24
Peak memory 209164 kb
Host smart-198c770f-ae6e-43bb-bc82-e0795157873b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604864540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_jtag_alert_test.604864540
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3128138129
Short name T140
Test name
Test status
Simulation time 1019161946 ps
CPU time 8.19 seconds
Started Jul 03 06:26:43 PM PDT 24
Finished Jul 03 06:26:52 PM PDT 24
Peak memory 208964 kb
Host smart-dab171dc-4ac0-4772-a324-d4c717fe4528
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128138129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.3128138129
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4022400150
Short name T899
Test name
Test status
Simulation time 4007030547 ps
CPU time 10.29 seconds
Started Jul 03 06:26:45 PM PDT 24
Finished Jul 03 06:26:55 PM PDT 24
Peak memory 209424 kb
Host smart-f427da63-189b-4414-bf2b-cb8f55764abb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022400150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.4022400150
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3771844942
Short name T141
Test name
Test status
Simulation time 53292510 ps
CPU time 1.22 seconds
Started Jul 03 06:26:45 PM PDT 24
Finished Jul 03 06:26:47 PM PDT 24
Peak memory 210684 kb
Host smart-43a71d83-28e5-46a9-812c-1af79a313754
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771844942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3771844942
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2062435590
Short name T929
Test name
Test status
Simulation time 359397017 ps
CPU time 2.39 seconds
Started Jul 03 06:26:47 PM PDT 24
Finished Jul 03 06:26:50 PM PDT 24
Peak memory 222900 kb
Host smart-5f971c23-dc09-43e8-b716-02cc9a842df7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206243
5590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2062435590
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3780227815
Short name T900
Test name
Test status
Simulation time 33458245 ps
CPU time 1.61 seconds
Started Jul 03 06:26:45 PM PDT 24
Finished Jul 03 06:26:47 PM PDT 24
Peak memory 209300 kb
Host smart-6573ef44-90a1-45f3-a687-70384c139dbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780227815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3780227815
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1880992961
Short name T204
Test name
Test status
Simulation time 46609243 ps
CPU time 1.12 seconds
Started Jul 03 06:26:47 PM PDT 24
Finished Jul 03 06:26:48 PM PDT 24
Peak memory 209416 kb
Host smart-da3db7f1-617f-40cc-bae0-37effa284864
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880992961 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1880992961
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2065104267
Short name T205
Test name
Test status
Simulation time 16989576 ps
CPU time 1.03 seconds
Started Jul 03 06:26:50 PM PDT 24
Finished Jul 03 06:26:52 PM PDT 24
Peak memory 209324 kb
Host smart-ef109c5e-b8b5-47cb-a779-1edab9e9a191
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065104267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.2065104267
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1737277831
Short name T119
Test name
Test status
Simulation time 752473044 ps
CPU time 3.54 seconds
Started Jul 03 06:26:45 PM PDT 24
Finished Jul 03 06:26:49 PM PDT 24
Peak memory 217468 kb
Host smart-b4b5afd3-2e7d-4d8e-8bd2-61da02b65183
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737277831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1737277831
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2844200590
Short name T133
Test name
Test status
Simulation time 72330320 ps
CPU time 2.88 seconds
Started Jul 03 06:26:44 PM PDT 24
Finished Jul 03 06:26:47 PM PDT 24
Peak memory 222476 kb
Host smart-f278a9e2-5ded-423b-96a4-cf3c0ee20c37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844200590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2844200590
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1783294865
Short name T122
Test name
Test status
Simulation time 57844541 ps
CPU time 1.11 seconds
Started Jul 03 06:26:54 PM PDT 24
Finished Jul 03 06:26:56 PM PDT 24
Peak memory 209452 kb
Host smart-459cbbc6-b5a6-4387-a265-fa676b341b2c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783294865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.1783294865
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3563965102
Short name T150
Test name
Test status
Simulation time 508602067 ps
CPU time 2.87 seconds
Started Jul 03 06:26:53 PM PDT 24
Finished Jul 03 06:26:56 PM PDT 24
Peak memory 217384 kb
Host smart-cddec698-adfe-4ea5-b4ae-4d5c12aee735
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563965102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.3563965102
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2512556462
Short name T193
Test name
Test status
Simulation time 22003300 ps
CPU time 0.95 seconds
Started Jul 03 06:26:53 PM PDT 24
Finished Jul 03 06:26:54 PM PDT 24
Peak memory 209688 kb
Host smart-46f21cd3-b7ff-4847-b7a0-4161e4f6a6d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512556462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.2512556462
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1022504762
Short name T152
Test name
Test status
Simulation time 70081358 ps
CPU time 1.38 seconds
Started Jul 03 06:26:51 PM PDT 24
Finished Jul 03 06:26:53 PM PDT 24
Peak memory 218636 kb
Host smart-c66c8ef2-6461-4e36-b937-e95bfac641d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022504762 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.1022504762
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.265991550
Short name T191
Test name
Test status
Simulation time 15498490 ps
CPU time 0.9 seconds
Started Jul 03 06:26:54 PM PDT 24
Finished Jul 03 06:26:55 PM PDT 24
Peak memory 209012 kb
Host smart-7cb3a525-6cf4-425d-adbb-f4ad74f6fea9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265991550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.265991550
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3587569099
Short name T972
Test name
Test status
Simulation time 237559956 ps
CPU time 2.04 seconds
Started Jul 03 06:26:49 PM PDT 24
Finished Jul 03 06:26:51 PM PDT 24
Peak memory 209124 kb
Host smart-17ea09f0-d17d-404c-9413-bba2e311520b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587569099 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3587569099
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3088475110
Short name T944
Test name
Test status
Simulation time 1115754999 ps
CPU time 6.2 seconds
Started Jul 03 06:26:49 PM PDT 24
Finished Jul 03 06:26:55 PM PDT 24
Peak memory 209284 kb
Host smart-d9ac7c34-7088-43d6-81e9-27e71fe36836
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088475110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3088475110
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.509721760
Short name T908
Test name
Test status
Simulation time 2054643417 ps
CPU time 46.45 seconds
Started Jul 03 06:26:51 PM PDT 24
Finished Jul 03 06:27:38 PM PDT 24
Peak memory 209052 kb
Host smart-981ee717-d485-4b79-b913-88875b69e5e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509721760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.509721760
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1849591996
Short name T959
Test name
Test status
Simulation time 599593818 ps
CPU time 2.28 seconds
Started Jul 03 06:26:47 PM PDT 24
Finished Jul 03 06:26:49 PM PDT 24
Peak memory 217552 kb
Host smart-5d27295a-52b6-45cd-9b12-6b05f66f93fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849591996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.1849591996
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2626988284
Short name T112
Test name
Test status
Simulation time 602592141 ps
CPU time 2.4 seconds
Started Jul 03 06:26:48 PM PDT 24
Finished Jul 03 06:26:50 PM PDT 24
Peak memory 222988 kb
Host smart-fbf4cce1-7abe-4e03-b3ac-0cf57766a8ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262698
8284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2626988284
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3292291955
Short name T916
Test name
Test status
Simulation time 60537087 ps
CPU time 1.16 seconds
Started Jul 03 06:26:49 PM PDT 24
Finished Jul 03 06:26:50 PM PDT 24
Peak memory 209268 kb
Host smart-f23d8d94-422e-48a7-9b48-b680cc903a0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292291955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.3292291955
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2079029166
Short name T984
Test name
Test status
Simulation time 44556457 ps
CPU time 1.36 seconds
Started Jul 03 06:26:49 PM PDT 24
Finished Jul 03 06:26:51 PM PDT 24
Peak memory 209316 kb
Host smart-566221c7-0c66-40bc-8839-62ec38553c81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079029166 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2079029166
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.30130742
Short name T210
Test name
Test status
Simulation time 163400701 ps
CPU time 1.52 seconds
Started Jul 03 06:26:52 PM PDT 24
Finished Jul 03 06:26:54 PM PDT 24
Peak memory 217664 kb
Host smart-03158f98-1936-4fba-8960-115df2fac7a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30130742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_s
ame_csr_outstanding.30130742
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2046597565
Short name T955
Test name
Test status
Simulation time 194739626 ps
CPU time 3.84 seconds
Started Jul 03 06:26:50 PM PDT 24
Finished Jul 03 06:26:55 PM PDT 24
Peak memory 217480 kb
Host smart-7cefdf34-d3f1-4dde-a9fc-ce2dac7f5850
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046597565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.2046597565
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1111940371
Short name T201
Test name
Test status
Simulation time 39515037 ps
CPU time 1.09 seconds
Started Jul 03 06:26:56 PM PDT 24
Finished Jul 03 06:26:57 PM PDT 24
Peak memory 209320 kb
Host smart-e25b0213-dcf3-4558-9259-b28b0e27d7f5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111940371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.1111940371
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2310885239
Short name T954
Test name
Test status
Simulation time 28328101 ps
CPU time 1.63 seconds
Started Jul 03 06:26:54 PM PDT 24
Finished Jul 03 06:26:56 PM PDT 24
Peak memory 209360 kb
Host smart-103e6d6d-2f47-40be-ba7b-5d11cce5d840
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310885239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2310885239
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.4231059164
Short name T198
Test name
Test status
Simulation time 62699105 ps
CPU time 1.04 seconds
Started Jul 03 06:26:55 PM PDT 24
Finished Jul 03 06:26:56 PM PDT 24
Peak memory 218084 kb
Host smart-00375601-b41d-4c32-a6c2-4d20931e2723
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231059164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.4231059164
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1975875557
Short name T967
Test name
Test status
Simulation time 46761011 ps
CPU time 1.05 seconds
Started Jul 03 06:26:58 PM PDT 24
Finished Jul 03 06:27:00 PM PDT 24
Peak memory 217644 kb
Host smart-1cfc7726-775e-4672-8ce3-5566bdef38aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975875557 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1975875557
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1927575913
Short name T190
Test name
Test status
Simulation time 114588289 ps
CPU time 0.86 seconds
Started Jul 03 06:26:54 PM PDT 24
Finished Jul 03 06:26:56 PM PDT 24
Peak memory 209288 kb
Host smart-e6affe27-6ebd-4fbf-831e-cf6b1a0af580
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927575913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.1927575913
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.964188988
Short name T974
Test name
Test status
Simulation time 422391201 ps
CPU time 1.44 seconds
Started Jul 03 06:26:55 PM PDT 24
Finished Jul 03 06:26:57 PM PDT 24
Peak memory 208656 kb
Host smart-656b1d76-8f75-466f-9a0c-15df0d501c0a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964188988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_alert_test.964188988
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1075895070
Short name T872
Test name
Test status
Simulation time 1105073759 ps
CPU time 4.99 seconds
Started Jul 03 06:26:53 PM PDT 24
Finished Jul 03 06:26:58 PM PDT 24
Peak memory 208924 kb
Host smart-4df63e61-0079-44f7-8347-a955eb93a0c4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075895070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.1075895070
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2233899851
Short name T876
Test name
Test status
Simulation time 3221693239 ps
CPU time 7.1 seconds
Started Jul 03 06:26:54 PM PDT 24
Finished Jul 03 06:27:01 PM PDT 24
Peak memory 209308 kb
Host smart-cf686b46-84e0-44a7-9cea-fc349b1ed809
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233899851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.2233899851
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2789608142
Short name T142
Test name
Test status
Simulation time 791687341 ps
CPU time 2.92 seconds
Started Jul 03 06:26:56 PM PDT 24
Finished Jul 03 06:26:59 PM PDT 24
Peak memory 217492 kb
Host smart-3250c219-2348-4977-9404-02d442846175
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789608142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2789608142
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.649192181
Short name T903
Test name
Test status
Simulation time 523144678 ps
CPU time 3.6 seconds
Started Jul 03 06:26:57 PM PDT 24
Finished Jul 03 06:27:01 PM PDT 24
Peak memory 217712 kb
Host smart-3fe021d6-4652-4a04-9687-add4be294b2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649192
181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.649192181
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.321761296
Short name T941
Test name
Test status
Simulation time 275669907 ps
CPU time 1.71 seconds
Started Jul 03 06:26:53 PM PDT 24
Finished Jul 03 06:26:55 PM PDT 24
Peak memory 209364 kb
Host smart-01939939-cf73-4e14-b24b-12089b530198
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321761296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.321761296
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2857407650
Short name T943
Test name
Test status
Simulation time 94067162 ps
CPU time 1.39 seconds
Started Jul 03 06:26:56 PM PDT 24
Finished Jul 03 06:26:57 PM PDT 24
Peak memory 209376 kb
Host smart-37f87db6-e7e9-4086-9a34-361d8fd776ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857407650 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2857407650
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2496549243
Short name T888
Test name
Test status
Simulation time 16119980 ps
CPU time 1.06 seconds
Started Jul 03 06:26:56 PM PDT 24
Finished Jul 03 06:26:58 PM PDT 24
Peak memory 217584 kb
Host smart-7a80b5b4-c80a-4d8e-8b67-6430758aee06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496549243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.2496549243
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3487529901
Short name T930
Test name
Test status
Simulation time 582877467 ps
CPU time 3.27 seconds
Started Jul 03 06:26:55 PM PDT 24
Finished Jul 03 06:26:58 PM PDT 24
Peak memory 218604 kb
Host smart-f0b4b6d4-69ca-4c00-bea9-a80d1a42ff88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487529901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.3487529901
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1067209461
Short name T982
Test name
Test status
Simulation time 27105312 ps
CPU time 1.18 seconds
Started Jul 03 06:26:58 PM PDT 24
Finished Jul 03 06:27:00 PM PDT 24
Peak memory 217644 kb
Host smart-16dcba79-1032-449b-b8df-626642752cb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067209461 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1067209461
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.805563960
Short name T951
Test name
Test status
Simulation time 29705419 ps
CPU time 0.81 seconds
Started Jul 03 06:26:59 PM PDT 24
Finished Jul 03 06:27:00 PM PDT 24
Peak memory 209292 kb
Host smart-ba64f091-6d3d-4f7c-a8ab-3404a89382b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805563960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.805563960
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.350557298
Short name T143
Test name
Test status
Simulation time 168686476 ps
CPU time 1.7 seconds
Started Jul 03 06:26:59 PM PDT 24
Finished Jul 03 06:27:01 PM PDT 24
Peak memory 209184 kb
Host smart-ae28d159-93d3-4457-962f-d63681050b23
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350557298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.lc_ctrl_jtag_alert_test.350557298
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2947442879
Short name T938
Test name
Test status
Simulation time 192445228 ps
CPU time 5.34 seconds
Started Jul 03 06:26:55 PM PDT 24
Finished Jul 03 06:27:01 PM PDT 24
Peak memory 209120 kb
Host smart-fd6c3eb9-d664-4e3e-82f8-9dd7e2b75689
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947442879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2947442879
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.4174077120
Short name T901
Test name
Test status
Simulation time 1604597992 ps
CPU time 10.08 seconds
Started Jul 03 06:26:57 PM PDT 24
Finished Jul 03 06:27:08 PM PDT 24
Peak memory 217148 kb
Host smart-d37b9389-d52f-46cc-890c-e93407df6a28
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174077120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.4174077120
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4007075059
Short name T871
Test name
Test status
Simulation time 273804066 ps
CPU time 1.39 seconds
Started Jul 03 06:26:55 PM PDT 24
Finished Jul 03 06:26:57 PM PDT 24
Peak memory 210700 kb
Host smart-624f3cc4-88d6-4098-9ebd-225e40f58d40
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007075059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.4007075059
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3124513375
Short name T896
Test name
Test status
Simulation time 50595567 ps
CPU time 1.91 seconds
Started Jul 03 06:27:00 PM PDT 24
Finished Jul 03 06:27:02 PM PDT 24
Peak memory 218672 kb
Host smart-856544ed-a5d4-4493-bfa4-4893c86dd66b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312451
3375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3124513375
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.4020947345
Short name T873
Test name
Test status
Simulation time 131401392 ps
CPU time 2.13 seconds
Started Jul 03 06:26:54 PM PDT 24
Finished Jul 03 06:26:57 PM PDT 24
Peak memory 209204 kb
Host smart-1bc1cbcb-ec04-42b9-b33a-eb82f779b05a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020947345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.4020947345
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.4203256555
Short name T906
Test name
Test status
Simulation time 40820882 ps
CPU time 2.04 seconds
Started Jul 03 06:27:00 PM PDT 24
Finished Jul 03 06:27:02 PM PDT 24
Peak memory 217572 kb
Host smart-7a7c5fde-f967-4728-9c9a-891b6e434c8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203256555 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.4203256555
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1301981465
Short name T953
Test name
Test status
Simulation time 38743474 ps
CPU time 1.68 seconds
Started Jul 03 06:26:58 PM PDT 24
Finished Jul 03 06:27:00 PM PDT 24
Peak memory 209392 kb
Host smart-4bcb479c-ddd0-47fb-b0d4-ec592305a072
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301981465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.1301981465
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3678096321
Short name T905
Test name
Test status
Simulation time 139311157 ps
CPU time 3.31 seconds
Started Jul 03 06:26:59 PM PDT 24
Finished Jul 03 06:27:03 PM PDT 24
Peak memory 217500 kb
Host smart-3a5d7e26-b8d8-4a97-9312-08969bee0b80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678096321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3678096321
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1469258325
Short name T134
Test name
Test status
Simulation time 91825473 ps
CPU time 1.96 seconds
Started Jul 03 06:26:59 PM PDT 24
Finished Jul 03 06:27:01 PM PDT 24
Peak memory 222008 kb
Host smart-0002fc09-962f-4f70-a07a-12cf295b7917
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469258325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1469258325
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.880416642
Short name T923
Test name
Test status
Simulation time 41105106 ps
CPU time 1.55 seconds
Started Jul 03 06:27:06 PM PDT 24
Finished Jul 03 06:27:07 PM PDT 24
Peak memory 221036 kb
Host smart-5abdb63d-6f06-46b8-9948-fe41296d920c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880416642 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.880416642
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.581507249
Short name T189
Test name
Test status
Simulation time 57221287 ps
CPU time 0.89 seconds
Started Jul 03 06:27:03 PM PDT 24
Finished Jul 03 06:27:04 PM PDT 24
Peak memory 209312 kb
Host smart-4ea7557c-a20f-45cc-a2be-d79fd0e6482f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581507249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.581507249
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2040812899
Short name T898
Test name
Test status
Simulation time 30891607 ps
CPU time 1.43 seconds
Started Jul 03 06:27:02 PM PDT 24
Finished Jul 03 06:27:03 PM PDT 24
Peak memory 209176 kb
Host smart-465e6163-b333-4c6f-8355-b4282ae4d8ff
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040812899 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2040812899
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3084999265
Short name T931
Test name
Test status
Simulation time 889028759 ps
CPU time 5.37 seconds
Started Jul 03 06:26:59 PM PDT 24
Finished Jul 03 06:27:05 PM PDT 24
Peak memory 217076 kb
Host smart-2ae13139-93d1-490a-a644-0970541d98e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084999265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.3084999265
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3361274955
Short name T979
Test name
Test status
Simulation time 1783365013 ps
CPU time 10.29 seconds
Started Jul 03 06:27:00 PM PDT 24
Finished Jul 03 06:27:10 PM PDT 24
Peak memory 209008 kb
Host smart-9053d70a-05af-4723-8d35-9d39848d690f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361274955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.3361274955
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1013688643
Short name T948
Test name
Test status
Simulation time 366228201 ps
CPU time 2.06 seconds
Started Jul 03 06:27:01 PM PDT 24
Finished Jul 03 06:27:04 PM PDT 24
Peak memory 210952 kb
Host smart-6d7d450e-0a6e-4e2f-8830-9af8a826e79c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013688643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1013688643
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2372146372
Short name T939
Test name
Test status
Simulation time 114504829 ps
CPU time 1.51 seconds
Started Jul 03 06:27:00 PM PDT 24
Finished Jul 03 06:27:02 PM PDT 24
Peak memory 209200 kb
Host smart-aadb0ce6-e4a8-4a97-a9d6-1093a378eaf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372146372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.2372146372
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.173681198
Short name T945
Test name
Test status
Simulation time 29338014 ps
CPU time 1.56 seconds
Started Jul 03 06:27:03 PM PDT 24
Finished Jul 03 06:27:05 PM PDT 24
Peak memory 209272 kb
Host smart-2b832375-8747-45d1-af39-99bdc0a233df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173681198 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.173681198
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1364714316
Short name T206
Test name
Test status
Simulation time 17025475 ps
CPU time 1.26 seconds
Started Jul 03 06:27:03 PM PDT 24
Finished Jul 03 06:27:04 PM PDT 24
Peak memory 209388 kb
Host smart-0a6f0e70-9485-4d8d-bb60-8e17bb59a836
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364714316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.1364714316
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.4173550054
Short name T949
Test name
Test status
Simulation time 481043683 ps
CPU time 3.29 seconds
Started Jul 03 06:27:02 PM PDT 24
Finished Jul 03 06:27:06 PM PDT 24
Peak memory 217452 kb
Host smart-de8f5d41-2c52-4fe8-85b7-0166c4ccf0cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173550054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.4173550054
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.4044898017
Short name T880
Test name
Test status
Simulation time 72352890 ps
CPU time 1.23 seconds
Started Jul 03 06:27:05 PM PDT 24
Finished Jul 03 06:27:07 PM PDT 24
Peak memory 222196 kb
Host smart-459587ed-1e62-4d10-84cb-b68282f5ccb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044898017 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.4044898017
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.826709512
Short name T966
Test name
Test status
Simulation time 32544936 ps
CPU time 1.11 seconds
Started Jul 03 06:27:06 PM PDT 24
Finished Jul 03 06:27:07 PM PDT 24
Peak memory 209292 kb
Host smart-4d19769c-0a9e-4062-b1b5-5490293cefcc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826709512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.826709512
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.244294974
Short name T874
Test name
Test status
Simulation time 143933360 ps
CPU time 4.06 seconds
Started Jul 03 06:27:10 PM PDT 24
Finished Jul 03 06:27:15 PM PDT 24
Peak memory 209164 kb
Host smart-b171784b-6613-4dd3-8fdb-207fd4ddad05
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244294974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.lc_ctrl_jtag_alert_test.244294974
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1338127794
Short name T937
Test name
Test status
Simulation time 445278157 ps
CPU time 4.85 seconds
Started Jul 03 06:27:02 PM PDT 24
Finished Jul 03 06:27:07 PM PDT 24
Peak memory 209220 kb
Host smart-ecd54714-a695-4ece-8db3-1f91c0c208f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338127794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1338127794
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1704426044
Short name T976
Test name
Test status
Simulation time 828504857 ps
CPU time 11.83 seconds
Started Jul 03 06:27:01 PM PDT 24
Finished Jul 03 06:27:13 PM PDT 24
Peak memory 209268 kb
Host smart-6d924451-1422-42f3-ba44-0d3e1b6b3fdb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704426044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1704426044
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3307142622
Short name T942
Test name
Test status
Simulation time 502177040 ps
CPU time 3 seconds
Started Jul 03 06:27:05 PM PDT 24
Finished Jul 03 06:27:09 PM PDT 24
Peak memory 210892 kb
Host smart-983b67b6-1da0-4261-8acd-ff82f82069bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307142622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3307142622
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3188011436
Short name T920
Test name
Test status
Simulation time 1248925673 ps
CPU time 2.14 seconds
Started Jul 03 06:27:04 PM PDT 24
Finished Jul 03 06:27:07 PM PDT 24
Peak memory 219276 kb
Host smart-ef31c072-ecc3-40b8-a9be-b6ac7bdb0ffc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318801
1436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3188011436
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1194892279
Short name T891
Test name
Test status
Simulation time 494263104 ps
CPU time 1.83 seconds
Started Jul 03 06:27:02 PM PDT 24
Finished Jul 03 06:27:04 PM PDT 24
Peak memory 217248 kb
Host smart-9745fa5c-67fb-4c7f-b62a-ed4c223bb6b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194892279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.1194892279
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1705388915
Short name T962
Test name
Test status
Simulation time 29410236 ps
CPU time 1.48 seconds
Started Jul 03 06:27:04 PM PDT 24
Finished Jul 03 06:27:06 PM PDT 24
Peak memory 209356 kb
Host smart-710e897c-1e68-4c71-8c46-02864e5748b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705388915 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1705388915
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.4109315010
Short name T987
Test name
Test status
Simulation time 47266835 ps
CPU time 0.96 seconds
Started Jul 03 06:27:08 PM PDT 24
Finished Jul 03 06:27:09 PM PDT 24
Peak memory 209128 kb
Host smart-d3e88356-fb27-4153-afb2-1c5b79938ab9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109315010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.4109315010
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1998364828
Short name T961
Test name
Test status
Simulation time 29570941 ps
CPU time 2.22 seconds
Started Jul 03 06:27:07 PM PDT 24
Finished Jul 03 06:27:09 PM PDT 24
Peak memory 217596 kb
Host smart-44d5ac7b-cb35-45e0-88c5-a08d7762e391
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998364828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1998364828
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.4164315256
Short name T123
Test name
Test status
Simulation time 165210447 ps
CPU time 3.65 seconds
Started Jul 03 06:27:08 PM PDT 24
Finished Jul 03 06:27:12 PM PDT 24
Peak memory 222444 kb
Host smart-437eadca-6ce5-43de-b890-3ffd9a03e230
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164315256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.4164315256
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2343694252
Short name T113
Test name
Test status
Simulation time 22028811 ps
CPU time 1.22 seconds
Started Jul 03 06:27:10 PM PDT 24
Finished Jul 03 06:27:11 PM PDT 24
Peak memory 217572 kb
Host smart-0c3b4eab-3ea0-4ad6-91ca-ca1be6a39174
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343694252 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.2343694252
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1584031198
Short name T117
Test name
Test status
Simulation time 45289057 ps
CPU time 1.02 seconds
Started Jul 03 06:27:13 PM PDT 24
Finished Jul 03 06:27:15 PM PDT 24
Peak memory 209232 kb
Host smart-2f9c2245-2728-4fb7-b565-733dd8819da1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584031198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.1584031198
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.385631401
Short name T965
Test name
Test status
Simulation time 46790638 ps
CPU time 1.17 seconds
Started Jul 03 06:27:07 PM PDT 24
Finished Jul 03 06:27:08 PM PDT 24
Peak memory 208676 kb
Host smart-3faed4fa-03a3-4e3e-b9d8-3db337c6748f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385631401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.lc_ctrl_jtag_alert_test.385631401
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2949061604
Short name T934
Test name
Test status
Simulation time 2075364906 ps
CPU time 7.57 seconds
Started Jul 03 06:27:14 PM PDT 24
Finished Jul 03 06:27:22 PM PDT 24
Peak memory 209012 kb
Host smart-12f0ea68-e16a-4093-b6a9-4993e79438d7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949061604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2949061604
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3979397243
Short name T909
Test name
Test status
Simulation time 20893262533 ps
CPU time 10.37 seconds
Started Jul 03 06:27:07 PM PDT 24
Finished Jul 03 06:27:18 PM PDT 24
Peak memory 209384 kb
Host smart-d9d78754-b8c1-4cef-9560-7975f124210f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979397243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3979397243
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1516619262
Short name T877
Test name
Test status
Simulation time 778608971 ps
CPU time 1.88 seconds
Started Jul 03 06:27:06 PM PDT 24
Finished Jul 03 06:27:08 PM PDT 24
Peak memory 211040 kb
Host smart-03b2ff49-c39c-4419-9d91-2d45d9db272f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516619262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.1516619262
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3207924130
Short name T174
Test name
Test status
Simulation time 266247192 ps
CPU time 4.15 seconds
Started Jul 03 06:27:04 PM PDT 24
Finished Jul 03 06:27:08 PM PDT 24
Peak memory 219044 kb
Host smart-14ce01a1-cf42-46e1-ba7a-3d44a7461b3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320792
4130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3207924130
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3677300221
Short name T883
Test name
Test status
Simulation time 131308184 ps
CPU time 1.12 seconds
Started Jul 03 06:27:06 PM PDT 24
Finished Jul 03 06:27:08 PM PDT 24
Peak memory 217284 kb
Host smart-cd6b13a8-7ac2-44ed-8b87-04fe62303554
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677300221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.3677300221
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2855331891
Short name T963
Test name
Test status
Simulation time 98889585 ps
CPU time 1.48 seconds
Started Jul 03 06:27:09 PM PDT 24
Finished Jul 03 06:27:10 PM PDT 24
Peak memory 217580 kb
Host smart-be18b277-e73d-4aa6-bafb-bc42d6d15224
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855331891 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2855331891
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.161083160
Short name T932
Test name
Test status
Simulation time 285556764 ps
CPU time 1.98 seconds
Started Jul 03 06:27:14 PM PDT 24
Finished Jul 03 06:27:16 PM PDT 24
Peak memory 217452 kb
Host smart-5adee3b5-5477-44b8-a902-163133b0e263
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161083160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
same_csr_outstanding.161083160
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.4279644627
Short name T111
Test name
Test status
Simulation time 119186364 ps
CPU time 3.58 seconds
Started Jul 03 06:27:09 PM PDT 24
Finished Jul 03 06:27:13 PM PDT 24
Peak memory 217592 kb
Host smart-032704ec-46b8-44d8-b2eb-d80086709faf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279644627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.4279644627
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3220446784
Short name T917
Test name
Test status
Simulation time 75642820 ps
CPU time 1.39 seconds
Started Jul 03 06:27:11 PM PDT 24
Finished Jul 03 06:27:12 PM PDT 24
Peak memory 218212 kb
Host smart-d04ee935-e669-4984-b251-e38c51c71e5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220446784 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3220446784
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1909286081
Short name T192
Test name
Test status
Simulation time 12991761 ps
CPU time 0.93 seconds
Started Jul 03 06:27:11 PM PDT 24
Finished Jul 03 06:27:13 PM PDT 24
Peak memory 208984 kb
Host smart-41a26b8f-3d9c-44a6-9049-7c06ac656806
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909286081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1909286081
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2838706283
Short name T956
Test name
Test status
Simulation time 97082431 ps
CPU time 0.91 seconds
Started Jul 03 06:27:09 PM PDT 24
Finished Jul 03 06:27:11 PM PDT 24
Peak memory 208656 kb
Host smart-b5b5f8b2-dc3d-46ad-9567-b9d4299d9439
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838706283 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2838706283
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3192658657
Short name T988
Test name
Test status
Simulation time 1542445263 ps
CPU time 4.82 seconds
Started Jul 03 06:27:09 PM PDT 24
Finished Jul 03 06:27:14 PM PDT 24
Peak memory 217008 kb
Host smart-a57463ab-a13b-44eb-9818-6ad92bb055c0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192658657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3192658657
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1720427729
Short name T882
Test name
Test status
Simulation time 9134688879 ps
CPU time 49.18 seconds
Started Jul 03 06:27:13 PM PDT 24
Finished Jul 03 06:28:03 PM PDT 24
Peak memory 209356 kb
Host smart-15149e4f-81ba-48c4-b6bb-770746dbb9f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720427729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1720427729
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2720421381
Short name T922
Test name
Test status
Simulation time 52972759 ps
CPU time 1.26 seconds
Started Jul 03 06:27:11 PM PDT 24
Finished Jul 03 06:27:13 PM PDT 24
Peak memory 217452 kb
Host smart-91cf7952-acd9-4d94-bce8-b2152b2f5651
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720421381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2720421381
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3853461073
Short name T983
Test name
Test status
Simulation time 134278010 ps
CPU time 4.18 seconds
Started Jul 03 06:27:11 PM PDT 24
Finished Jul 03 06:27:16 PM PDT 24
Peak memory 219408 kb
Host smart-0cdbee7e-947e-4923-be5c-686eccb36f75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385346
1073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3853461073
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1928932426
Short name T960
Test name
Test status
Simulation time 196724087 ps
CPU time 1.46 seconds
Started Jul 03 06:27:09 PM PDT 24
Finished Jul 03 06:27:11 PM PDT 24
Peak memory 209284 kb
Host smart-43e4b80b-2490-477a-b8c0-873819c99deb
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928932426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1928932426
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.792925575
Short name T989
Test name
Test status
Simulation time 176142099 ps
CPU time 1.53 seconds
Started Jul 03 06:27:11 PM PDT 24
Finished Jul 03 06:27:13 PM PDT 24
Peak memory 209376 kb
Host smart-8ce08195-e01b-4d9e-a130-1041f5b0e869
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792925575 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.792925575
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.160368545
Short name T151
Test name
Test status
Simulation time 87967569 ps
CPU time 1.31 seconds
Started Jul 03 06:27:11 PM PDT 24
Finished Jul 03 06:27:13 PM PDT 24
Peak memory 209384 kb
Host smart-be51cbb4-1d9b-4feb-9c36-973ff7c62249
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160368545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
same_csr_outstanding.160368545
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3860226061
Short name T973
Test name
Test status
Simulation time 480837184 ps
CPU time 3.49 seconds
Started Jul 03 06:27:10 PM PDT 24
Finished Jul 03 06:27:14 PM PDT 24
Peak memory 217580 kb
Host smart-5df18821-bcf5-43f0-817e-c7e3f19edf13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860226061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.3860226061
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3683093789
Short name T737
Test name
Test status
Simulation time 16615584 ps
CPU time 1.08 seconds
Started Jul 03 05:03:54 PM PDT 24
Finished Jul 03 05:03:56 PM PDT 24
Peak memory 208904 kb
Host smart-61a07d36-51d3-4260-9760-92f7d7fbdcc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683093789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3683093789
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.758323002
Short name T630
Test name
Test status
Simulation time 537803479 ps
CPU time 11.68 seconds
Started Jul 03 05:03:37 PM PDT 24
Finished Jul 03 05:03:49 PM PDT 24
Peak memory 225976 kb
Host smart-16d0def7-8e09-4363-ada1-c6196a22b81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758323002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.758323002
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2196725235
Short name T669
Test name
Test status
Simulation time 340741443 ps
CPU time 4.41 seconds
Started Jul 03 05:03:34 PM PDT 24
Finished Jul 03 05:03:39 PM PDT 24
Peak memory 217008 kb
Host smart-9f40c051-ad2b-41d4-bc88-3bf85616d159
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196725235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2196725235
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.4213880862
Short name T603
Test name
Test status
Simulation time 1451919966 ps
CPU time 26.15 seconds
Started Jul 03 05:03:34 PM PDT 24
Finished Jul 03 05:04:00 PM PDT 24
Peak memory 218156 kb
Host smart-14c9f420-8024-4adf-9056-caf4f6067a31
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213880862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.4213880862
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1661551150
Short name T680
Test name
Test status
Simulation time 3959812325 ps
CPU time 9.03 seconds
Started Jul 03 05:03:36 PM PDT 24
Finished Jul 03 05:03:45 PM PDT 24
Peak memory 218072 kb
Host smart-0219078d-79b4-428d-b07c-7ca5381dd039
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661551150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
661551150
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2086579984
Short name T417
Test name
Test status
Simulation time 617909513 ps
CPU time 2.89 seconds
Started Jul 03 05:03:27 PM PDT 24
Finished Jul 03 05:03:30 PM PDT 24
Peak memory 218448 kb
Host smart-459a2e97-865a-4046-a276-240318b0f576
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086579984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.2086579984
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3475853989
Short name T487
Test name
Test status
Simulation time 1248820640 ps
CPU time 18.44 seconds
Started Jul 03 05:03:32 PM PDT 24
Finished Jul 03 05:03:51 PM PDT 24
Peak memory 217652 kb
Host smart-ffdc242a-0e5c-4d92-9f74-ff77cbd2e835
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475853989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.3475853989
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.785857487
Short name T757
Test name
Test status
Simulation time 680758426 ps
CPU time 5 seconds
Started Jul 03 05:03:36 PM PDT 24
Finished Jul 03 05:03:41 PM PDT 24
Peak memory 217664 kb
Host smart-f48c6138-7ffc-4bcb-94cf-68d9c5fb412b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785857487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.785857487
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.3013492513
Short name T581
Test name
Test status
Simulation time 1818708369 ps
CPU time 42.62 seconds
Started Jul 03 05:03:27 PM PDT 24
Finished Jul 03 05:04:10 PM PDT 24
Peak memory 276452 kb
Host smart-c648f0a8-22ce-4ce7-a1d5-7297bc4bca5c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013492513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.3013492513
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.882614452
Short name T391
Test name
Test status
Simulation time 1279691318 ps
CPU time 7.52 seconds
Started Jul 03 05:03:50 PM PDT 24
Finished Jul 03 05:03:59 PM PDT 24
Peak memory 223600 kb
Host smart-9a0fa87d-7b6b-490d-aa66-78a648e4284a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882614452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.882614452
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1819885876
Short name T522
Test name
Test status
Simulation time 84499105 ps
CPU time 2.94 seconds
Started Jul 03 05:03:47 PM PDT 24
Finished Jul 03 05:03:51 PM PDT 24
Peak memory 218172 kb
Host smart-045ada20-6141-4b5c-bea6-3f433e518859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819885876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1819885876
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.2235816073
Short name T525
Test name
Test status
Simulation time 1188717471 ps
CPU time 16.39 seconds
Started Jul 03 05:04:00 PM PDT 24
Finished Jul 03 05:04:17 PM PDT 24
Peak memory 217660 kb
Host smart-7349a4fe-35da-47e4-bbd0-6db22be40066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235816073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2235816073
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.4159487233
Short name T293
Test name
Test status
Simulation time 709377899 ps
CPU time 16.26 seconds
Started Jul 03 05:03:43 PM PDT 24
Finished Jul 03 05:03:59 PM PDT 24
Peak memory 225952 kb
Host smart-0ad71ecd-7cfa-4b90-ac9f-1245ced5ce96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159487233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.4159487233
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3089561984
Short name T473
Test name
Test status
Simulation time 3932816635 ps
CPU time 21.99 seconds
Started Jul 03 05:03:31 PM PDT 24
Finished Jul 03 05:03:53 PM PDT 24
Peak memory 218868 kb
Host smart-45d5b22b-2477-452d-84de-c3598ce37f16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089561984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.3089561984
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.3630938513
Short name T446
Test name
Test status
Simulation time 303742237 ps
CPU time 8.48 seconds
Started Jul 03 05:03:34 PM PDT 24
Finished Jul 03 05:03:43 PM PDT 24
Peak memory 218152 kb
Host smart-5c2ae41a-6b04-4f73-80bd-24ed73cac4a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630938513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.3
630938513
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.470198637
Short name T476
Test name
Test status
Simulation time 414212330 ps
CPU time 9.76 seconds
Started Jul 03 05:03:35 PM PDT 24
Finished Jul 03 05:03:45 PM PDT 24
Peak memory 225968 kb
Host smart-696889b8-35c3-4ad1-9d5a-e9d48170137b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470198637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.470198637
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.3487979001
Short name T344
Test name
Test status
Simulation time 163374022 ps
CPU time 2.91 seconds
Started Jul 03 05:03:33 PM PDT 24
Finished Jul 03 05:03:36 PM PDT 24
Peak memory 214792 kb
Host smart-18daadc8-0d98-4021-8792-7b587a7b6385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487979001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3487979001
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.1979074505
Short name T458
Test name
Test status
Simulation time 543006709 ps
CPU time 27.09 seconds
Started Jul 03 05:03:42 PM PDT 24
Finished Jul 03 05:04:10 PM PDT 24
Peak memory 250940 kb
Host smart-c7f1bb36-2e9f-46d7-953e-96137396c834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979074505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1979074505
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1455731693
Short name T178
Test name
Test status
Simulation time 302182253 ps
CPU time 7.25 seconds
Started Jul 03 05:03:52 PM PDT 24
Finished Jul 03 05:04:00 PM PDT 24
Peak memory 250932 kb
Host smart-3d49175a-ea0a-47ec-963d-392ab6664bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455731693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1455731693
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.765255807
Short name T258
Test name
Test status
Simulation time 714272423 ps
CPU time 13.87 seconds
Started Jul 03 05:03:33 PM PDT 24
Finished Jul 03 05:03:48 PM PDT 24
Peak memory 225976 kb
Host smart-044ee773-e098-4537-88dd-33f5b35ad4ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765255807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.765255807
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.400011317
Short name T145
Test name
Test status
Simulation time 32946290325 ps
CPU time 291.08 seconds
Started Jul 03 05:03:31 PM PDT 24
Finished Jul 03 05:08:22 PM PDT 24
Peak memory 275132 kb
Host smart-27e9be6d-9fbe-450d-a53a-bcad2fdbe6a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=400011317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.400011317
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.2883136647
Short name T596
Test name
Test status
Simulation time 63523295 ps
CPU time 0.82 seconds
Started Jul 03 05:03:44 PM PDT 24
Finished Jul 03 05:03:45 PM PDT 24
Peak memory 208756 kb
Host smart-d1cc64eb-62d9-47fd-8c8e-d4ab330a6246
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883136647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.2883136647
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1130611935
Short name T310
Test name
Test status
Simulation time 12719289 ps
CPU time 0.82 seconds
Started Jul 03 05:03:32 PM PDT 24
Finished Jul 03 05:03:33 PM PDT 24
Peak memory 208704 kb
Host smart-c2aa8c3e-20b4-43cf-a512-30f256766d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130611935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.1130611935
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.90695212
Short name T795
Test name
Test status
Simulation time 1359332479 ps
CPU time 12.28 seconds
Started Jul 03 05:03:29 PM PDT 24
Finished Jul 03 05:03:41 PM PDT 24
Peak memory 218100 kb
Host smart-f57d274f-4482-4cdb-bd90-8e0fa0df8828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90695212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.90695212
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1910309973
Short name T385
Test name
Test status
Simulation time 547535103 ps
CPU time 4.98 seconds
Started Jul 03 05:03:48 PM PDT 24
Finished Jul 03 05:03:54 PM PDT 24
Peak memory 217128 kb
Host smart-ec8c5f31-eddf-4306-b7c7-1991d05e0148
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910309973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1910309973
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2683543375
Short name T616
Test name
Test status
Simulation time 1462257808 ps
CPU time 40.01 seconds
Started Jul 03 05:03:37 PM PDT 24
Finished Jul 03 05:04:17 PM PDT 24
Peak memory 218208 kb
Host smart-33baa366-9067-4392-8986-dd510d3430f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683543375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2683543375
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2726860101
Short name T570
Test name
Test status
Simulation time 634078579 ps
CPU time 8.14 seconds
Started Jul 03 05:03:31 PM PDT 24
Finished Jul 03 05:03:40 PM PDT 24
Peak memory 217728 kb
Host smart-0e7f92c3-3106-4cf5-8617-49331e430aa8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726860101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
726860101
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3960465193
Short name T252
Test name
Test status
Simulation time 1643253520 ps
CPU time 11.8 seconds
Started Jul 03 05:03:53 PM PDT 24
Finished Jul 03 05:04:05 PM PDT 24
Peak memory 218088 kb
Host smart-15872ffc-bd08-4537-b9ed-f17db1a9a07e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960465193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.3960465193
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.385015629
Short name T40
Test name
Test status
Simulation time 7074801308 ps
CPU time 18.19 seconds
Started Jul 03 05:03:31 PM PDT 24
Finished Jul 03 05:03:50 PM PDT 24
Peak memory 217580 kb
Host smart-ad26780a-7c96-4a0c-87bf-78f5638ec19a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385015629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_regwen_during_op.385015629
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.1862598690
Short name T98
Test name
Test status
Simulation time 19500965416 ps
CPU time 50.57 seconds
Started Jul 03 05:03:40 PM PDT 24
Finished Jul 03 05:04:32 PM PDT 24
Peak memory 267376 kb
Host smart-99d8977f-03ec-446a-8cd1-dec22b57af6d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862598690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.1862598690
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3073706591
Short name T451
Test name
Test status
Simulation time 2213445181 ps
CPU time 11.77 seconds
Started Jul 03 05:03:35 PM PDT 24
Finished Jul 03 05:03:47 PM PDT 24
Peak memory 250408 kb
Host smart-260ddc3c-8f5a-4b07-abd4-80696756b915
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073706591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.3073706591
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.138223562
Short name T692
Test name
Test status
Simulation time 65794560 ps
CPU time 2.64 seconds
Started Jul 03 05:03:41 PM PDT 24
Finished Jul 03 05:03:44 PM PDT 24
Peak memory 222128 kb
Host smart-9a5fddd6-3666-4feb-9770-049204d7499c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138223562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.138223562
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.3941522878
Short name T813
Test name
Test status
Simulation time 327296912 ps
CPU time 12.28 seconds
Started Jul 03 05:03:28 PM PDT 24
Finished Jul 03 05:03:41 PM PDT 24
Peak memory 217640 kb
Host smart-975db0d7-15d9-434b-a4fa-68d827a607d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941522878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3941522878
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.925037831
Short name T107
Test name
Test status
Simulation time 229323850 ps
CPU time 41.79 seconds
Started Jul 03 05:03:42 PM PDT 24
Finished Jul 03 05:04:24 PM PDT 24
Peak memory 270280 kb
Host smart-5b1a654a-0006-4fb7-be6e-58266f247f3c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925037831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.925037831
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1801900857
Short name T697
Test name
Test status
Simulation time 320615365 ps
CPU time 16.25 seconds
Started Jul 03 05:03:53 PM PDT 24
Finished Jul 03 05:04:09 PM PDT 24
Peak memory 219824 kb
Host smart-c3cb71b6-f25f-42cb-8e07-bfcec36f39b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801900857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1801900857
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.904746318
Short name T441
Test name
Test status
Simulation time 325945092 ps
CPU time 13.32 seconds
Started Jul 03 05:03:56 PM PDT 24
Finished Jul 03 05:04:10 PM PDT 24
Peak memory 225912 kb
Host smart-55f37239-b6e4-4c91-a8a6-6831733778c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904746318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dig
est.904746318
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.1402206462
Short name T278
Test name
Test status
Simulation time 3549793208 ps
CPU time 11.76 seconds
Started Jul 03 05:03:34 PM PDT 24
Finished Jul 03 05:03:47 PM PDT 24
Peak memory 226032 kb
Host smart-c467c122-ae6c-46a5-a8b4-e69e5a2d3c7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402206462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.1
402206462
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3787063446
Short name T334
Test name
Test status
Simulation time 704624459 ps
CPU time 9.03 seconds
Started Jul 03 05:03:33 PM PDT 24
Finished Jul 03 05:03:42 PM PDT 24
Peak memory 225104 kb
Host smart-09986e3c-68aa-445f-ab5e-52e782aac375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787063446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3787063446
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.1563638025
Short name T613
Test name
Test status
Simulation time 198725441 ps
CPU time 11.01 seconds
Started Jul 03 05:03:44 PM PDT 24
Finished Jul 03 05:03:56 PM PDT 24
Peak memory 217552 kb
Host smart-1dd45dc7-ed6a-4ca3-b340-f63fafd7c2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563638025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1563638025
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.158047019
Short name T725
Test name
Test status
Simulation time 186788576 ps
CPU time 21.89 seconds
Started Jul 03 05:03:31 PM PDT 24
Finished Jul 03 05:03:53 PM PDT 24
Peak memory 250940 kb
Host smart-5bbe25f6-6f1f-4d01-a417-c6d8257ef68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158047019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.158047019
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1426092106
Short name T106
Test name
Test status
Simulation time 94366548 ps
CPU time 6.87 seconds
Started Jul 03 05:03:41 PM PDT 24
Finished Jul 03 05:03:48 PM PDT 24
Peak memory 251208 kb
Host smart-27a1ec9f-110d-483f-83e6-388eb0030917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426092106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1426092106
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.1183641304
Short name T460
Test name
Test status
Simulation time 14658805983 ps
CPU time 158.1 seconds
Started Jul 03 05:03:54 PM PDT 24
Finished Jul 03 05:06:32 PM PDT 24
Peak memory 267468 kb
Host smart-8b75159d-14e1-4ce6-b97d-669e04ce428d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183641304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.1183641304
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.389051970
Short name T481
Test name
Test status
Simulation time 28028323 ps
CPU time 0.96 seconds
Started Jul 03 05:03:48 PM PDT 24
Finished Jul 03 05:03:50 PM PDT 24
Peak memory 213496 kb
Host smart-3ec5054a-94e4-4954-981a-723062489750
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389051970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctr
l_volatile_unlock_smoke.389051970
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.3203428741
Short name T547
Test name
Test status
Simulation time 123874871 ps
CPU time 0.94 seconds
Started Jul 03 05:04:03 PM PDT 24
Finished Jul 03 05:04:05 PM PDT 24
Peak memory 208892 kb
Host smart-f8551e4c-c656-4b03-8ccd-f37acdf428a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203428741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3203428741
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.3631142927
Short name T623
Test name
Test status
Simulation time 452401453 ps
CPU time 11.85 seconds
Started Jul 03 05:04:07 PM PDT 24
Finished Jul 03 05:04:19 PM PDT 24
Peak memory 225952 kb
Host smart-800a02e9-9c50-4367-b96e-4ea96e78770b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631142927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.3631142927
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1483799981
Short name T663
Test name
Test status
Simulation time 334152244 ps
CPU time 2.63 seconds
Started Jul 03 05:04:21 PM PDT 24
Finished Jul 03 05:04:25 PM PDT 24
Peak memory 217072 kb
Host smart-6d488706-ad5f-490e-a262-9149ea755daf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483799981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1483799981
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2670740010
Short name T619
Test name
Test status
Simulation time 1018694983 ps
CPU time 31.99 seconds
Started Jul 03 05:04:13 PM PDT 24
Finished Jul 03 05:04:46 PM PDT 24
Peak memory 218184 kb
Host smart-1fd1cccd-7bf8-4dc8-b061-7c649d304978
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670740010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2670740010
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1845102556
Short name T100
Test name
Test status
Simulation time 739193779 ps
CPU time 3.29 seconds
Started Jul 03 05:04:17 PM PDT 24
Finished Jul 03 05:04:21 PM PDT 24
Peak memory 218176 kb
Host smart-94180029-ecdd-4f5a-8d4d-cab836153278
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845102556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1845102556
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3259530994
Short name T408
Test name
Test status
Simulation time 695596272 ps
CPU time 3.72 seconds
Started Jul 03 05:04:14 PM PDT 24
Finished Jul 03 05:04:18 PM PDT 24
Peak memory 217664 kb
Host smart-bf0bc48f-1ccc-4599-b3d4-bd73934c7250
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259530994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.3259530994
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3376929415
Short name T272
Test name
Test status
Simulation time 6697520921 ps
CPU time 64 seconds
Started Jul 03 05:04:06 PM PDT 24
Finished Jul 03 05:05:11 PM PDT 24
Peak memory 283676 kb
Host smart-badfbe5b-93c3-4c57-a6af-4458ad6c738b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376929415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.3376929415
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2013790928
Short name T571
Test name
Test status
Simulation time 5431403962 ps
CPU time 20.04 seconds
Started Jul 03 05:04:21 PM PDT 24
Finished Jul 03 05:04:43 PM PDT 24
Peak memory 236668 kb
Host smart-e2f3c415-dea5-4475-a696-a9d6a0790361
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013790928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.2013790928
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.152419610
Short name T337
Test name
Test status
Simulation time 144323898 ps
CPU time 2.72 seconds
Started Jul 03 05:04:07 PM PDT 24
Finished Jul 03 05:04:10 PM PDT 24
Peak memory 218128 kb
Host smart-a4e35197-706e-4df7-97a4-e58dce1ec78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152419610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.152419610
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.711809731
Short name T46
Test name
Test status
Simulation time 541641833 ps
CPU time 11.43 seconds
Started Jul 03 05:04:18 PM PDT 24
Finished Jul 03 05:04:30 PM PDT 24
Peak memory 225936 kb
Host smart-f71919cd-e1ea-40b4-bf7a-e1bb46bae4ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711809731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.711809731
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3986188517
Short name T728
Test name
Test status
Simulation time 380602871 ps
CPU time 14.73 seconds
Started Jul 03 05:04:22 PM PDT 24
Finished Jul 03 05:04:39 PM PDT 24
Peak memory 225896 kb
Host smart-97c8db89-9975-4b7f-9f8a-3cf6e1121389
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986188517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3986188517
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2282016841
Short name T698
Test name
Test status
Simulation time 451705266 ps
CPU time 9.37 seconds
Started Jul 03 05:04:19 PM PDT 24
Finished Jul 03 05:04:29 PM PDT 24
Peak memory 225972 kb
Host smart-1a6020b4-8291-4934-9c36-72bf3c74d9fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282016841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
2282016841
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.4165541831
Short name T528
Test name
Test status
Simulation time 65096702 ps
CPU time 1.32 seconds
Started Jul 03 05:04:18 PM PDT 24
Finished Jul 03 05:04:20 PM PDT 24
Peak memory 217632 kb
Host smart-c4fd13c4-ebea-4e1c-acf4-81a9bec83401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165541831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.4165541831
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.1580949555
Short name T179
Test name
Test status
Simulation time 556170284 ps
CPU time 29.98 seconds
Started Jul 03 05:04:12 PM PDT 24
Finished Jul 03 05:04:42 PM PDT 24
Peak memory 250808 kb
Host smart-ee1aac4d-7133-49c8-9a92-640eb993f3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580949555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1580949555
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.467334299
Short name T380
Test name
Test status
Simulation time 118160273 ps
CPU time 6.27 seconds
Started Jul 03 05:04:22 PM PDT 24
Finished Jul 03 05:04:29 PM PDT 24
Peak memory 250484 kb
Host smart-4585f5de-9f3c-4a91-8db0-4d839872c98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467334299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.467334299
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.3762828207
Short name T732
Test name
Test status
Simulation time 3020786838 ps
CPU time 47.9 seconds
Started Jul 03 05:04:09 PM PDT 24
Finished Jul 03 05:04:57 PM PDT 24
Peak memory 251000 kb
Host smart-4fe3e3f7-7261-4e7e-90e4-1d2a84e00252
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762828207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.3762828207
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.4289255659
Short name T545
Test name
Test status
Simulation time 18269734 ps
CPU time 0.87 seconds
Started Jul 03 05:04:03 PM PDT 24
Finished Jul 03 05:04:04 PM PDT 24
Peak memory 211932 kb
Host smart-296e95d2-0e77-4553-87d5-2b1217506203
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289255659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.4289255659
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.1334027246
Short name T384
Test name
Test status
Simulation time 27626661 ps
CPU time 1.11 seconds
Started Jul 03 05:04:21 PM PDT 24
Finished Jul 03 05:04:23 PM PDT 24
Peak memory 208948 kb
Host smart-60672266-1f84-4d12-9214-dc5c02264886
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334027246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.1334027246
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3100716985
Short name T861
Test name
Test status
Simulation time 854112970 ps
CPU time 10.52 seconds
Started Jul 03 05:04:20 PM PDT 24
Finished Jul 03 05:04:31 PM PDT 24
Peak memory 218180 kb
Host smart-c7f8cc94-2ffe-443c-b1e8-7f8b0c16b889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100716985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3100716985
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.910203752
Short name T6
Test name
Test status
Simulation time 43012150 ps
CPU time 1.25 seconds
Started Jul 03 05:04:14 PM PDT 24
Finished Jul 03 05:04:17 PM PDT 24
Peak memory 217012 kb
Host smart-d7786881-7b6f-493b-9eff-45abf01ab5c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910203752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.910203752
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.3922632388
Short name T36
Test name
Test status
Simulation time 1319639773 ps
CPU time 7.8 seconds
Started Jul 03 05:04:19 PM PDT 24
Finished Jul 03 05:04:27 PM PDT 24
Peak memory 224200 kb
Host smart-83cc6cc6-96cd-424c-b4a1-bb1d0bee40cc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922632388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.3922632388
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2230306970
Short name T729
Test name
Test status
Simulation time 156255952 ps
CPU time 2.37 seconds
Started Jul 03 05:04:13 PM PDT 24
Finished Jul 03 05:04:16 PM PDT 24
Peak memory 217656 kb
Host smart-bfc06279-752a-42b7-84a3-5d4e6902bd00
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230306970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2230306970
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.439170771
Short name T361
Test name
Test status
Simulation time 1289158778 ps
CPU time 41.62 seconds
Started Jul 03 05:04:06 PM PDT 24
Finished Jul 03 05:04:48 PM PDT 24
Peak memory 267992 kb
Host smart-c63d9d8b-36fd-45e8-882e-9bac7b1898fb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439170771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_state_failure.439170771
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.2193123285
Short name T799
Test name
Test status
Simulation time 434522846 ps
CPU time 10.95 seconds
Started Jul 03 05:04:23 PM PDT 24
Finished Jul 03 05:04:36 PM PDT 24
Peak memory 247488 kb
Host smart-0779eb50-4374-4697-95f3-aa86bc2477de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193123285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.2193123285
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.1242719353
Short name T769
Test name
Test status
Simulation time 46008500 ps
CPU time 2.81 seconds
Started Jul 03 05:04:23 PM PDT 24
Finished Jul 03 05:04:27 PM PDT 24
Peak memory 218092 kb
Host smart-96a91bdb-6148-48e6-ad2f-d31ca0242c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242719353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1242719353
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2470182232
Short name T428
Test name
Test status
Simulation time 480235791 ps
CPU time 10.86 seconds
Started Jul 03 05:04:16 PM PDT 24
Finished Jul 03 05:04:27 PM PDT 24
Peak memory 225968 kb
Host smart-b722d7e8-8037-4bd7-a544-d52c1e7dcbeb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470182232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2470182232
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3495794795
Short name T617
Test name
Test status
Simulation time 279151171 ps
CPU time 7.87 seconds
Started Jul 03 05:04:19 PM PDT 24
Finished Jul 03 05:04:29 PM PDT 24
Peak memory 225960 kb
Host smart-fd0f0b7d-62a9-4cfb-a77c-41e3367143ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495794795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.3495794795
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3946842526
Short name T345
Test name
Test status
Simulation time 253260965 ps
CPU time 9.83 seconds
Started Jul 03 05:04:17 PM PDT 24
Finished Jul 03 05:04:28 PM PDT 24
Peak memory 218128 kb
Host smart-ebe9c7ca-f895-44bd-8de5-4094c1dc457c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946842526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3946842526
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.39824583
Short name T464
Test name
Test status
Simulation time 700128990 ps
CPU time 9.32 seconds
Started Jul 03 05:04:11 PM PDT 24
Finished Jul 03 05:04:21 PM PDT 24
Peak memory 225888 kb
Host smart-b884463e-db52-4870-9a64-7683f862e95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39824583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.39824583
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.762908989
Short name T326
Test name
Test status
Simulation time 66247647 ps
CPU time 2.37 seconds
Started Jul 03 05:04:20 PM PDT 24
Finished Jul 03 05:04:23 PM PDT 24
Peak memory 223700 kb
Host smart-ba8cab02-6cc2-44aa-9e3f-74d91eb0fa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762908989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.762908989
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.2139956015
Short name T367
Test name
Test status
Simulation time 4918195131 ps
CPU time 20.55 seconds
Started Jul 03 05:04:06 PM PDT 24
Finished Jul 03 05:04:27 PM PDT 24
Peak memory 251052 kb
Host smart-c682848a-a46f-4aeb-85ab-544d43d7eae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139956015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.2139956015
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.449600664
Short name T632
Test name
Test status
Simulation time 172855804 ps
CPU time 7.55 seconds
Started Jul 03 05:04:06 PM PDT 24
Finished Jul 03 05:04:14 PM PDT 24
Peak memory 250916 kb
Host smart-4d38b0fa-fe46-41ae-95d1-55a092bdf78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449600664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.449600664
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.3397116861
Short name T636
Test name
Test status
Simulation time 12207272260 ps
CPU time 395.71 seconds
Started Jul 03 05:04:15 PM PDT 24
Finished Jul 03 05:10:51 PM PDT 24
Peak memory 278044 kb
Host smart-eae64fdd-3e7f-4046-ab73-cd806d73fa37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397116861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.3397116861
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.4174538784
Short name T212
Test name
Test status
Simulation time 55157226 ps
CPU time 0.91 seconds
Started Jul 03 05:04:06 PM PDT 24
Finished Jul 03 05:04:07 PM PDT 24
Peak memory 211768 kb
Host smart-ac9030bc-6c04-4898-a657-c183c764185c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174538784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.4174538784
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.399218987
Short name T76
Test name
Test status
Simulation time 40361338 ps
CPU time 1.17 seconds
Started Jul 03 05:04:10 PM PDT 24
Finished Jul 03 05:04:12 PM PDT 24
Peak memory 209000 kb
Host smart-48e671af-ff87-4665-ba7b-6f48d2802529
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399218987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.399218987
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.3414620947
Short name T638
Test name
Test status
Simulation time 1059550899 ps
CPU time 11.53 seconds
Started Jul 03 05:04:07 PM PDT 24
Finished Jul 03 05:04:19 PM PDT 24
Peak memory 218184 kb
Host smart-c7b19c75-604f-414c-9886-852f85eb88e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414620947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3414620947
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.2183281063
Short name T805
Test name
Test status
Simulation time 290489742 ps
CPU time 4.21 seconds
Started Jul 03 05:04:03 PM PDT 24
Finished Jul 03 05:04:07 PM PDT 24
Peak memory 216984 kb
Host smart-eb0d1f2b-b5b2-4484-814f-2e2718c8f3cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183281063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.2183281063
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.110518234
Short name T16
Test name
Test status
Simulation time 5994173426 ps
CPU time 22.84 seconds
Started Jul 03 05:04:10 PM PDT 24
Finished Jul 03 05:04:33 PM PDT 24
Peak memory 218916 kb
Host smart-7caae040-1553-441e-b0f1-88a4d520f95e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110518234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_er
rors.110518234
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.4270566593
Short name T838
Test name
Test status
Simulation time 3264068900 ps
CPU time 6.5 seconds
Started Jul 03 05:04:24 PM PDT 24
Finished Jul 03 05:04:34 PM PDT 24
Peak memory 223524 kb
Host smart-e7749181-22fe-4831-a7fb-71e29750143a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270566593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.4270566593
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2319969291
Short name T827
Test name
Test status
Simulation time 621481908 ps
CPU time 5.47 seconds
Started Jul 03 05:04:11 PM PDT 24
Finished Jul 03 05:04:18 PM PDT 24
Peak memory 217724 kb
Host smart-2639f6fb-2f61-493b-89a4-9d04cdd1fec4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319969291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2319969291
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1353197439
Short name T155
Test name
Test status
Simulation time 2535200307 ps
CPU time 52.05 seconds
Started Jul 03 05:04:04 PM PDT 24
Finished Jul 03 05:04:56 PM PDT 24
Peak memory 279476 kb
Host smart-9a34f803-c818-4b3a-aee9-8582172f6576
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353197439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1353197439
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3965471535
Short name T469
Test name
Test status
Simulation time 449157455 ps
CPU time 17.98 seconds
Started Jul 03 05:04:22 PM PDT 24
Finished Jul 03 05:04:41 PM PDT 24
Peak memory 250928 kb
Host smart-be62eb68-1eb2-46e7-aed1-2902b3ed77a8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965471535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3965471535
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.636703392
Short name T535
Test name
Test status
Simulation time 24876297 ps
CPU time 1.71 seconds
Started Jul 03 05:04:15 PM PDT 24
Finished Jul 03 05:04:17 PM PDT 24
Peak memory 218132 kb
Host smart-f589b00d-365d-4240-b96d-5fdff2fbe85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636703392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.636703392
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2734010589
Short name T287
Test name
Test status
Simulation time 221861713 ps
CPU time 8.41 seconds
Started Jul 03 05:04:23 PM PDT 24
Finished Jul 03 05:04:33 PM PDT 24
Peak memory 218136 kb
Host smart-363bd689-016c-4796-9fbc-11cfd0d02365
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734010589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2734010589
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.105002027
Short name T519
Test name
Test status
Simulation time 358550025 ps
CPU time 8.9 seconds
Started Jul 03 05:04:10 PM PDT 24
Finished Jul 03 05:04:20 PM PDT 24
Peak memory 225976 kb
Host smart-b4cfb4c1-09c5-4dad-bd6f-fbbf677f0915
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105002027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_di
gest.105002027
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.1088512891
Short name T724
Test name
Test status
Simulation time 364901645 ps
CPU time 12.26 seconds
Started Jul 03 05:04:18 PM PDT 24
Finished Jul 03 05:04:32 PM PDT 24
Peak memory 225976 kb
Host smart-c2946501-d944-40c6-b8d1-eb012efdba9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088512891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
1088512891
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.1416335199
Short name T626
Test name
Test status
Simulation time 1942052148 ps
CPU time 11.05 seconds
Started Jul 03 05:04:22 PM PDT 24
Finished Jul 03 05:04:35 PM PDT 24
Peak memory 218072 kb
Host smart-2d27a481-4a8f-4078-b7dd-f0e12d82f732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416335199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.1416335199
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.3661349855
Short name T682
Test name
Test status
Simulation time 23014546 ps
CPU time 1.55 seconds
Started Jul 03 05:04:09 PM PDT 24
Finished Jul 03 05:04:11 PM PDT 24
Peak memory 217664 kb
Host smart-28ce810f-69a7-4bb6-99ae-2968bf4a4e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661349855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.3661349855
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2325416752
Short name T689
Test name
Test status
Simulation time 1305989403 ps
CPU time 32.9 seconds
Started Jul 03 05:04:13 PM PDT 24
Finished Jul 03 05:04:47 PM PDT 24
Peak memory 250880 kb
Host smart-1d4017ee-d441-4a91-b344-02eb1140bc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325416752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2325416752
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.3415235596
Short name T3
Test name
Test status
Simulation time 63610162 ps
CPU time 8.33 seconds
Started Jul 03 05:04:21 PM PDT 24
Finished Jul 03 05:04:31 PM PDT 24
Peak memory 244200 kb
Host smart-0bbf2f86-64be-4b8c-8b6f-ff4e9c96c2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415235596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3415235596
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2858324174
Short name T414
Test name
Test status
Simulation time 27663494708 ps
CPU time 77.79 seconds
Started Jul 03 05:04:20 PM PDT 24
Finished Jul 03 05:05:39 PM PDT 24
Peak memory 277416 kb
Host smart-c8ff0e78-6184-4fe1-94e8-9a378b075751
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858324174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2858324174
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3062134694
Short name T745
Test name
Test status
Simulation time 15449003 ps
CPU time 0.89 seconds
Started Jul 03 05:04:14 PM PDT 24
Finished Jul 03 05:04:16 PM PDT 24
Peak memory 211820 kb
Host smart-39de769b-0031-43ca-93bc-83b49b7a4086
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062134694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3062134694
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.1886610471
Short name T853
Test name
Test status
Simulation time 18548398 ps
CPU time 1.17 seconds
Started Jul 03 05:04:20 PM PDT 24
Finished Jul 03 05:04:23 PM PDT 24
Peak memory 208992 kb
Host smart-43254357-4551-436a-b96d-303d15b4e548
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886610471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.1886610471
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1120600979
Short name T280
Test name
Test status
Simulation time 556075640 ps
CPU time 16.64 seconds
Started Jul 03 05:04:14 PM PDT 24
Finished Jul 03 05:04:32 PM PDT 24
Peak memory 218148 kb
Host smart-1497c07c-1d33-43b7-8e3a-b683e20e07e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120600979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1120600979
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.2376379879
Short name T776
Test name
Test status
Simulation time 693825523 ps
CPU time 5.17 seconds
Started Jul 03 05:04:17 PM PDT 24
Finished Jul 03 05:04:22 PM PDT 24
Peak memory 216992 kb
Host smart-2d8566f7-019e-4414-b947-ae54dd573a13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376379879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.2376379879
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.2154099179
Short name T775
Test name
Test status
Simulation time 8737390006 ps
CPU time 63.43 seconds
Started Jul 03 05:04:17 PM PDT 24
Finished Jul 03 05:05:22 PM PDT 24
Peak memory 218252 kb
Host smart-314699ff-5d85-4464-bdb1-6fc1843b250f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154099179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.2154099179
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.626766104
Short name T860
Test name
Test status
Simulation time 6971713957 ps
CPU time 6.91 seconds
Started Jul 03 05:04:21 PM PDT 24
Finished Jul 03 05:04:29 PM PDT 24
Peak memory 224600 kb
Host smart-134f45d5-77a5-46f6-a066-f82a684e2f41
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626766104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag
_prog_failure.626766104
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.3245001031
Short name T543
Test name
Test status
Simulation time 893163500 ps
CPU time 4.3 seconds
Started Jul 03 05:04:08 PM PDT 24
Finished Jul 03 05:04:12 PM PDT 24
Peak memory 217668 kb
Host smart-b9a7a4fc-ff4a-4276-b7b4-5735ab404069
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245001031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.3245001031
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3331543522
Short name T355
Test name
Test status
Simulation time 1810502427 ps
CPU time 48.77 seconds
Started Jul 03 05:04:18 PM PDT 24
Finished Jul 03 05:05:08 PM PDT 24
Peak memory 267256 kb
Host smart-c80464ab-7b01-4c17-b502-dc63ebc496c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331543522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3331543522
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.269101202
Short name T229
Test name
Test status
Simulation time 3465227068 ps
CPU time 5.01 seconds
Started Jul 03 05:04:21 PM PDT 24
Finished Jul 03 05:04:28 PM PDT 24
Peak memory 223492 kb
Host smart-3d34da1c-8a66-4220-b7f0-ed1babab8d41
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269101202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_
jtag_state_post_trans.269101202
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.2679400130
Short name T608
Test name
Test status
Simulation time 61564290 ps
CPU time 3.2 seconds
Started Jul 03 05:04:22 PM PDT 24
Finished Jul 03 05:04:27 PM PDT 24
Peak memory 218128 kb
Host smart-5ce40f8f-7295-4e71-ac3f-38ed89bea44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679400130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.2679400130
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.2060401920
Short name T556
Test name
Test status
Simulation time 1384941875 ps
CPU time 13.88 seconds
Started Jul 03 05:04:21 PM PDT 24
Finished Jul 03 05:04:36 PM PDT 24
Peak memory 218796 kb
Host smart-aaf68298-7223-4cb0-b33f-e60a85773898
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060401920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.2060401920
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.1282847770
Short name T227
Test name
Test status
Simulation time 1590033448 ps
CPU time 16.05 seconds
Started Jul 03 05:04:18 PM PDT 24
Finished Jul 03 05:04:35 PM PDT 24
Peak memory 225936 kb
Host smart-f004df44-fddc-4d40-8459-6b0c99c5a4a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282847770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.1282847770
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1269156955
Short name T360
Test name
Test status
Simulation time 300942097 ps
CPU time 10.82 seconds
Started Jul 03 05:04:21 PM PDT 24
Finished Jul 03 05:04:33 PM PDT 24
Peak memory 218192 kb
Host smart-88072caa-2da8-4b8a-849c-7ff603c4e1ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269156955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1269156955
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.278896835
Short name T574
Test name
Test status
Simulation time 377555472 ps
CPU time 10.2 seconds
Started Jul 03 05:04:23 PM PDT 24
Finished Jul 03 05:04:35 PM PDT 24
Peak memory 218244 kb
Host smart-67f81e59-7b2f-4606-b60b-bae176622182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278896835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.278896835
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2505693408
Short name T298
Test name
Test status
Simulation time 31606770 ps
CPU time 1.04 seconds
Started Jul 03 05:04:12 PM PDT 24
Finished Jul 03 05:04:14 PM PDT 24
Peak memory 212096 kb
Host smart-192a0d90-abe4-4fae-b72d-ef8d9b7aef57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505693408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2505693408
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2574469607
Short name T866
Test name
Test status
Simulation time 223118135 ps
CPU time 22.96 seconds
Started Jul 03 05:04:23 PM PDT 24
Finished Jul 03 05:04:47 PM PDT 24
Peak memory 250992 kb
Host smart-1dd9920d-3d96-42ee-a2e9-07c08a13d12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574469607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2574469607
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.36913122
Short name T432
Test name
Test status
Simulation time 88677784 ps
CPU time 8.24 seconds
Started Jul 03 05:04:25 PM PDT 24
Finished Jul 03 05:04:35 PM PDT 24
Peak memory 250924 kb
Host smart-bcd9b292-e284-4010-b347-c7b203a4267a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36913122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.36913122
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.4153683807
Short name T313
Test name
Test status
Simulation time 3613993271 ps
CPU time 48.68 seconds
Started Jul 03 05:04:24 PM PDT 24
Finished Jul 03 05:05:15 PM PDT 24
Peak memory 236736 kb
Host smart-c59fe2c3-9c2a-4f47-8f5c-e1857fa2f2c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153683807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.4153683807
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.2023510157
Short name T51
Test name
Test status
Simulation time 29022958930 ps
CPU time 180.59 seconds
Started Jul 03 05:04:20 PM PDT 24
Finished Jul 03 05:07:22 PM PDT 24
Peak memory 267512 kb
Host smart-d60225d4-e455-4a39-9efa-bede3ce3c61b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2023510157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.2023510157
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2427242491
Short name T639
Test name
Test status
Simulation time 112822126 ps
CPU time 0.88 seconds
Started Jul 03 05:04:15 PM PDT 24
Finished Jul 03 05:04:17 PM PDT 24
Peak memory 212764 kb
Host smart-4df381aa-6e40-4b6f-b05d-842a05c0473d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427242491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2427242491
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2501888048
Short name T644
Test name
Test status
Simulation time 230952070 ps
CPU time 1.26 seconds
Started Jul 03 05:04:11 PM PDT 24
Finished Jul 03 05:04:13 PM PDT 24
Peak memory 208968 kb
Host smart-0b4a230c-3ca1-4559-b0ea-ed335a35b1a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501888048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2501888048
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.1801651133
Short name T554
Test name
Test status
Simulation time 404551649 ps
CPU time 17.56 seconds
Started Jul 03 05:04:21 PM PDT 24
Finished Jul 03 05:04:40 PM PDT 24
Peak memory 225980 kb
Host smart-4f0e63b4-398f-46d1-9840-3bc205fc1b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801651133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1801651133
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.725187413
Short name T870
Test name
Test status
Simulation time 4454034395 ps
CPU time 25.93 seconds
Started Jul 03 05:04:20 PM PDT 24
Finished Jul 03 05:04:47 PM PDT 24
Peak memory 218848 kb
Host smart-fd53c4cf-4225-4ffa-a8ba-7dcd0fcfdb81
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725187413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_er
rors.725187413
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.621187486
Short name T416
Test name
Test status
Simulation time 152295128 ps
CPU time 4.88 seconds
Started Jul 03 05:04:21 PM PDT 24
Finished Jul 03 05:04:27 PM PDT 24
Peak memory 218144 kb
Host smart-4a9d4f1e-cd2c-476c-9d20-7f09c80faa3b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621187486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag
_prog_failure.621187486
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.2748351292
Short name T828
Test name
Test status
Simulation time 9376181933 ps
CPU time 16.86 seconds
Started Jul 03 05:04:19 PM PDT 24
Finished Jul 03 05:04:37 PM PDT 24
Peak memory 217716 kb
Host smart-f424bd4e-79b0-4855-b53a-702ce3808f03
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748351292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.2748351292
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.212800686
Short name T715
Test name
Test status
Simulation time 5125050274 ps
CPU time 45.6 seconds
Started Jul 03 05:04:11 PM PDT 24
Finished Jul 03 05:04:57 PM PDT 24
Peak memory 270816 kb
Host smart-a19ba2a2-b3d8-4a7b-8da2-688670ce2957
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212800686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_state_failure.212800686
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.874957148
Short name T312
Test name
Test status
Simulation time 665215992 ps
CPU time 18.51 seconds
Started Jul 03 05:04:08 PM PDT 24
Finished Jul 03 05:04:27 PM PDT 24
Peak memory 250948 kb
Host smart-08f0045d-fef6-437b-8808-35c345e0aa50
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874957148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.874957148
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.3935594545
Short name T410
Test name
Test status
Simulation time 294120826 ps
CPU time 2.83 seconds
Started Jul 03 05:04:17 PM PDT 24
Finished Jul 03 05:04:20 PM PDT 24
Peak memory 222500 kb
Host smart-92d080c2-c825-4c3b-b59c-2ed82d4bc6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935594545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.3935594545
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.1069013155
Short name T328
Test name
Test status
Simulation time 777091293 ps
CPU time 11.82 seconds
Started Jul 03 05:04:20 PM PDT 24
Finished Jul 03 05:04:33 PM PDT 24
Peak memory 225956 kb
Host smart-1ca4a24a-5dcc-4a70-af23-09ac5b58b049
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069013155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1069013155
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.1053211849
Short name T666
Test name
Test status
Simulation time 2264080839 ps
CPU time 11.15 seconds
Started Jul 03 05:04:20 PM PDT 24
Finished Jul 03 05:04:32 PM PDT 24
Peak memory 225948 kb
Host smart-5da25e4c-c28a-4734-ac0d-ee453530f6b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053211849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.1053211849
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1231178222
Short name T856
Test name
Test status
Simulation time 1505045300 ps
CPU time 12.12 seconds
Started Jul 03 05:04:21 PM PDT 24
Finished Jul 03 05:04:34 PM PDT 24
Peak memory 218176 kb
Host smart-2f960e23-0266-4dbd-90f2-524991d631d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231178222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
1231178222
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.3185328706
Short name T594
Test name
Test status
Simulation time 678954257 ps
CPU time 7.94 seconds
Started Jul 03 05:04:18 PM PDT 24
Finished Jul 03 05:04:27 PM PDT 24
Peak memory 225300 kb
Host smart-7f503518-c6ad-4e6f-843d-0e03749b43eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185328706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.3185328706
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.2864406685
Short name T762
Test name
Test status
Simulation time 48559097 ps
CPU time 1.55 seconds
Started Jul 03 05:04:11 PM PDT 24
Finished Jul 03 05:04:13 PM PDT 24
Peak memory 217676 kb
Host smart-ec6ca349-b5df-40ae-97b5-1ef91e734b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864406685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2864406685
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.3159458504
Short name T468
Test name
Test status
Simulation time 392021162 ps
CPU time 30.76 seconds
Started Jul 03 05:04:21 PM PDT 24
Finished Jul 03 05:04:53 PM PDT 24
Peak memory 250860 kb
Host smart-f1d9f1ae-6c1b-4a13-8d86-e99f1efaa8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159458504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3159458504
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.3478579714
Short name T657
Test name
Test status
Simulation time 71751718 ps
CPU time 6.96 seconds
Started Jul 03 05:04:24 PM PDT 24
Finished Jul 03 05:04:33 PM PDT 24
Peak memory 250448 kb
Host smart-bcc1ef4d-9bf8-4d48-9603-418d51edb2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478579714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3478579714
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.885628452
Short name T351
Test name
Test status
Simulation time 19323268281 ps
CPU time 163.63 seconds
Started Jul 03 05:04:31 PM PDT 24
Finished Jul 03 05:07:15 PM PDT 24
Peak memory 283736 kb
Host smart-1a96d7c4-b8e2-4c58-8046-7069c36286bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885628452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.885628452
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.717344726
Short name T213
Test name
Test status
Simulation time 32390370 ps
CPU time 0.86 seconds
Started Jul 03 05:04:07 PM PDT 24
Finished Jul 03 05:04:09 PM PDT 24
Peak memory 211860 kb
Host smart-2d32ba79-c9c5-4e16-968f-56aac7a76f6e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717344726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ct
rl_volatile_unlock_smoke.717344726
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3465012187
Short name T851
Test name
Test status
Simulation time 35649512 ps
CPU time 1.02 seconds
Started Jul 03 05:04:25 PM PDT 24
Finished Jul 03 05:04:28 PM PDT 24
Peak memory 208964 kb
Host smart-b725b58e-2a47-411f-973b-745af16bf9e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465012187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3465012187
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.1900030474
Short name T270
Test name
Test status
Simulation time 610693394 ps
CPU time 14.56 seconds
Started Jul 03 05:04:13 PM PDT 24
Finished Jul 03 05:04:29 PM PDT 24
Peak memory 218096 kb
Host smart-e21af753-053c-445a-b2ba-899e3dde3eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900030474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.1900030474
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1876040803
Short name T33
Test name
Test status
Simulation time 430481255 ps
CPU time 10.29 seconds
Started Jul 03 05:04:27 PM PDT 24
Finished Jul 03 05:04:40 PM PDT 24
Peak memory 217152 kb
Host smart-0fee1a65-1a0f-43ec-841e-defef17f9203
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876040803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1876040803
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.4120049512
Short name T18
Test name
Test status
Simulation time 9168912092 ps
CPU time 67.02 seconds
Started Jul 03 05:04:26 PM PDT 24
Finished Jul 03 05:05:36 PM PDT 24
Peak memory 218904 kb
Host smart-acfe1d08-a64c-49a4-9c80-8c62d0060d1a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120049512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.4120049512
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2526410409
Short name T735
Test name
Test status
Simulation time 1746355913 ps
CPU time 6.37 seconds
Started Jul 03 05:04:26 PM PDT 24
Finished Jul 03 05:04:35 PM PDT 24
Peak memory 218192 kb
Host smart-3b419754-6214-4e80-bb7f-b6366a8cc7a2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526410409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.2526410409
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.2300317966
Short name T68
Test name
Test status
Simulation time 353504137 ps
CPU time 2.08 seconds
Started Jul 03 05:04:25 PM PDT 24
Finished Jul 03 05:04:29 PM PDT 24
Peak memory 217604 kb
Host smart-423900fb-461a-4a48-b96f-9d6caaac5266
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300317966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.2300317966
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1932282707
Short name T614
Test name
Test status
Simulation time 13009457241 ps
CPU time 102.55 seconds
Started Jul 03 05:04:14 PM PDT 24
Finished Jul 03 05:05:58 PM PDT 24
Peak memory 282732 kb
Host smart-df61e884-9bff-4148-88b5-d801f1763b2e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932282707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.1932282707
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1292595283
Short name T369
Test name
Test status
Simulation time 1930393093 ps
CPU time 32.39 seconds
Started Jul 03 05:04:19 PM PDT 24
Finished Jul 03 05:04:52 PM PDT 24
Peak memory 250840 kb
Host smart-18f427d5-4cdf-436d-af20-12fd7b888b6f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292595283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.1292595283
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.959050914
Short name T563
Test name
Test status
Simulation time 32977786 ps
CPU time 2.3 seconds
Started Jul 03 05:04:17 PM PDT 24
Finished Jul 03 05:04:20 PM PDT 24
Peak memory 222128 kb
Host smart-0d4a8b02-a8a8-4f5c-8bd6-a1e9b6ff3ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959050914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.959050914
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.1088055159
Short name T742
Test name
Test status
Simulation time 2031568880 ps
CPU time 15.03 seconds
Started Jul 03 05:04:19 PM PDT 24
Finished Jul 03 05:04:35 PM PDT 24
Peak memory 225940 kb
Host smart-70f59dfb-00b3-411a-accd-8ca131e47ead
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088055159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1088055159
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.901985001
Short name T240
Test name
Test status
Simulation time 2166418703 ps
CPU time 14.93 seconds
Started Jul 03 05:04:20 PM PDT 24
Finished Jul 03 05:04:36 PM PDT 24
Peak memory 226016 kb
Host smart-2d1397a7-5140-4dfb-a180-525aa1b3d066
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901985001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di
gest.901985001
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.2567714960
Short name T726
Test name
Test status
Simulation time 1224951111 ps
CPU time 12.21 seconds
Started Jul 03 05:04:18 PM PDT 24
Finished Jul 03 05:04:32 PM PDT 24
Peak memory 218148 kb
Host smart-4cac0ee6-e0ce-420f-8bb6-51f9a7fc62e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567714960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
2567714960
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.318467053
Short name T676
Test name
Test status
Simulation time 476006675 ps
CPU time 8.75 seconds
Started Jul 03 05:04:17 PM PDT 24
Finished Jul 03 05:04:27 PM PDT 24
Peak memory 225976 kb
Host smart-bef780af-ac05-46b6-ab76-6f47fb2f6853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318467053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.318467053
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.3258153576
Short name T277
Test name
Test status
Simulation time 44745053 ps
CPU time 1.71 seconds
Started Jul 03 05:04:18 PM PDT 24
Finished Jul 03 05:04:21 PM PDT 24
Peak memory 217580 kb
Host smart-e98e03eb-ab81-4355-b1c3-c8a432d61b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258153576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.3258153576
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.2200078987
Short name T691
Test name
Test status
Simulation time 1571584213 ps
CPU time 30.59 seconds
Started Jul 03 05:04:23 PM PDT 24
Finished Jul 03 05:04:55 PM PDT 24
Peak memory 250928 kb
Host smart-7fa48087-72b2-4782-8a28-594a9d5df3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200078987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2200078987
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1763120868
Short name T865
Test name
Test status
Simulation time 49062189 ps
CPU time 7.47 seconds
Started Jul 03 05:04:21 PM PDT 24
Finished Jul 03 05:04:30 PM PDT 24
Peak memory 250548 kb
Host smart-724689d0-68e8-496b-8137-f2ebfa481204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763120868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1763120868
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2256814960
Short name T177
Test name
Test status
Simulation time 33149985 ps
CPU time 0.87 seconds
Started Jul 03 05:04:22 PM PDT 24
Finished Jul 03 05:04:24 PM PDT 24
Peak memory 211784 kb
Host smart-072f076b-09a1-415a-a03d-1f97a36d96ea
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256814960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2256814960
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.872731388
Short name T540
Test name
Test status
Simulation time 59150825 ps
CPU time 0.86 seconds
Started Jul 03 05:04:24 PM PDT 24
Finished Jul 03 05:04:27 PM PDT 24
Peak memory 208904 kb
Host smart-795234d9-85a5-44cb-996c-9f6f67dd34cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872731388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.872731388
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.1519208125
Short name T96
Test name
Test status
Simulation time 985123798 ps
CPU time 8.21 seconds
Started Jul 03 05:04:22 PM PDT 24
Finished Jul 03 05:04:32 PM PDT 24
Peak memory 225968 kb
Host smart-d32d6484-86bf-47b6-b08b-97ee9c6b749c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519208125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1519208125
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.624239616
Short name T634
Test name
Test status
Simulation time 1043397825 ps
CPU time 3.44 seconds
Started Jul 03 05:04:18 PM PDT 24
Finished Jul 03 05:04:22 PM PDT 24
Peak memory 217100 kb
Host smart-75e08bbd-59ae-4b6c-935d-a965fd50cd92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624239616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.624239616
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3524925529
Short name T752
Test name
Test status
Simulation time 1719929092 ps
CPU time 33.09 seconds
Started Jul 03 05:04:26 PM PDT 24
Finished Jul 03 05:05:02 PM PDT 24
Peak memory 218200 kb
Host smart-781d365b-7aaa-4682-bc64-814e276faf01
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524925529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3524925529
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.586276218
Short name T447
Test name
Test status
Simulation time 6980210437 ps
CPU time 11.23 seconds
Started Jul 03 05:04:23 PM PDT 24
Finished Jul 03 05:04:37 PM PDT 24
Peak memory 223820 kb
Host smart-ac406818-c92e-4d90-93b0-03182db16ac1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586276218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag
_prog_failure.586276218
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.801994358
Short name T512
Test name
Test status
Simulation time 408240896 ps
CPU time 2.12 seconds
Started Jul 03 05:04:22 PM PDT 24
Finished Jul 03 05:04:25 PM PDT 24
Peak memory 217648 kb
Host smart-ca7c2aad-282a-418c-9674-60b4c9e91bfe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801994358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke.
801994358
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2167322609
Short name T374
Test name
Test status
Simulation time 4537846032 ps
CPU time 52.9 seconds
Started Jul 03 05:04:25 PM PDT 24
Finished Jul 03 05:05:21 PM PDT 24
Peak memory 268936 kb
Host smart-c1bee547-5d02-4871-8178-e1f7aa11d3bc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167322609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2167322609
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.456396805
Short name T720
Test name
Test status
Simulation time 777406218 ps
CPU time 26.17 seconds
Started Jul 03 05:04:24 PM PDT 24
Finished Jul 03 05:04:52 PM PDT 24
Peak memory 250168 kb
Host smart-0cb0ad37-6cd9-48a1-aa84-8c9fdced28be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456396805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
jtag_state_post_trans.456396805
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2180037882
Short name T358
Test name
Test status
Simulation time 159135232 ps
CPU time 1.9 seconds
Started Jul 03 05:04:22 PM PDT 24
Finished Jul 03 05:04:26 PM PDT 24
Peak memory 221908 kb
Host smart-6cca1c73-6176-4d00-9597-12604957881b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180037882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2180037882
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.2632899721
Short name T395
Test name
Test status
Simulation time 2019202047 ps
CPU time 12.25 seconds
Started Jul 03 05:04:32 PM PDT 24
Finished Jul 03 05:04:45 PM PDT 24
Peak memory 218136 kb
Host smart-1e248360-9e49-4d41-b50c-bac2cce1858b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632899721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.2632899721
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.3630549080
Short name T665
Test name
Test status
Simulation time 1180571834 ps
CPU time 8.62 seconds
Started Jul 03 05:04:26 PM PDT 24
Finished Jul 03 05:04:37 PM PDT 24
Peak memory 225940 kb
Host smart-38cc3234-217a-43a2-adb9-23f24750b57a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630549080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.3630549080
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2173279337
Short name T420
Test name
Test status
Simulation time 2298492898 ps
CPU time 16.71 seconds
Started Jul 03 05:04:32 PM PDT 24
Finished Jul 03 05:04:49 PM PDT 24
Peak memory 226036 kb
Host smart-3648c443-48b8-4ba9-ac9c-f8f807c47fb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173279337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2173279337
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.613076451
Short name T569
Test name
Test status
Simulation time 244290566 ps
CPU time 6.9 seconds
Started Jul 03 05:04:26 PM PDT 24
Finished Jul 03 05:04:35 PM PDT 24
Peak memory 224720 kb
Host smart-771cb1c9-236c-4c93-9a9e-76c65e44f28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613076451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.613076451
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3156778952
Short name T836
Test name
Test status
Simulation time 197287223 ps
CPU time 3.14 seconds
Started Jul 03 05:04:31 PM PDT 24
Finished Jul 03 05:04:35 PM PDT 24
Peak memory 214832 kb
Host smart-9a6816f6-5029-452c-be0f-29f7cd650cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156778952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3156778952
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.785166556
Short name T297
Test name
Test status
Simulation time 687399406 ps
CPU time 31.51 seconds
Started Jul 03 05:04:26 PM PDT 24
Finished Jul 03 05:05:00 PM PDT 24
Peak memory 250936 kb
Host smart-6b169171-d86d-4b89-82e5-a20b83f92226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785166556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.785166556
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.528406637
Short name T38
Test name
Test status
Simulation time 428884720 ps
CPU time 2.76 seconds
Started Jul 03 05:04:23 PM PDT 24
Finished Jul 03 05:04:27 PM PDT 24
Peak memory 226344 kb
Host smart-111937a4-0107-4c2c-9dce-84f54a49efda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528406637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.528406637
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2078753522
Short name T628
Test name
Test status
Simulation time 38783559614 ps
CPU time 153.06 seconds
Started Jul 03 05:04:23 PM PDT 24
Finished Jul 03 05:06:58 PM PDT 24
Peak memory 298900 kb
Host smart-6007d338-569d-45ec-83b1-43567e3109eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078753522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2078753522
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.820781754
Short name T660
Test name
Test status
Simulation time 28910840522 ps
CPU time 625.67 seconds
Started Jul 03 05:04:25 PM PDT 24
Finished Jul 03 05:14:53 PM PDT 24
Peak memory 480512 kb
Host smart-4e529573-8774-4399-ad16-c66091f027a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=820781754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.820781754
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1481617843
Short name T819
Test name
Test status
Simulation time 26612738 ps
CPU time 0.95 seconds
Started Jul 03 05:04:35 PM PDT 24
Finished Jul 03 05:04:36 PM PDT 24
Peak memory 217684 kb
Host smart-576495b0-2a52-4c0c-81f4-5780de89cddd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481617843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.1481617843
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.167301112
Short name T565
Test name
Test status
Simulation time 151804177 ps
CPU time 0.82 seconds
Started Jul 03 05:04:22 PM PDT 24
Finished Jul 03 05:04:25 PM PDT 24
Peak memory 208752 kb
Host smart-77ba2948-cf4d-4f55-97cc-552ee4e5c1e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167301112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.167301112
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.2800959111
Short name T359
Test name
Test status
Simulation time 1166937143 ps
CPU time 11.57 seconds
Started Jul 03 05:04:25 PM PDT 24
Finished Jul 03 05:04:39 PM PDT 24
Peak memory 218172 kb
Host smart-f70bdcd6-5961-4263-a40b-2be7e257f5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800959111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.2800959111
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.1869703577
Short name T582
Test name
Test status
Simulation time 5658187354 ps
CPU time 14.66 seconds
Started Jul 03 05:04:21 PM PDT 24
Finished Jul 03 05:04:37 PM PDT 24
Peak memory 217660 kb
Host smart-eaf9b340-61df-43d7-b18b-680c7e176b3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869703577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.1869703577
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3526057581
Short name T513
Test name
Test status
Simulation time 5568649212 ps
CPU time 18.98 seconds
Started Jul 03 05:04:27 PM PDT 24
Finished Jul 03 05:04:48 PM PDT 24
Peak memory 218276 kb
Host smart-adb65b7d-c507-44e6-9b39-3f6634e8baf1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526057581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3526057581
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2354301409
Short name T382
Test name
Test status
Simulation time 1105293469 ps
CPU time 8.99 seconds
Started Jul 03 05:04:24 PM PDT 24
Finished Jul 03 05:04:36 PM PDT 24
Peak memory 218196 kb
Host smart-aec8c067-aaca-4bb8-a5e6-430775ef4c24
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354301409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.2354301409
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.342099167
Short name T864
Test name
Test status
Simulation time 2472751029 ps
CPU time 9.12 seconds
Started Jul 03 05:04:32 PM PDT 24
Finished Jul 03 05:04:42 PM PDT 24
Peak memory 217720 kb
Host smart-d156992d-3e18-49fa-9d74-b9df42cd25b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342099167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
342099167
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.825427736
Short name T322
Test name
Test status
Simulation time 1752080679 ps
CPU time 73.32 seconds
Started Jul 03 05:04:28 PM PDT 24
Finished Jul 03 05:05:43 PM PDT 24
Peak memory 274008 kb
Host smart-471809ac-b0cc-4068-ab93-5ab7a103bfd9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825427736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_state_failure.825427736
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2303752009
Short name T400
Test name
Test status
Simulation time 7875422758 ps
CPU time 18.78 seconds
Started Jul 03 05:04:35 PM PDT 24
Finished Jul 03 05:04:54 PM PDT 24
Peak memory 250536 kb
Host smart-5db3ff15-bb47-405f-b3df-2ecc62f9e0e0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303752009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.2303752009
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2318941501
Short name T267
Test name
Test status
Simulation time 279618469 ps
CPU time 3.12 seconds
Started Jul 03 05:04:26 PM PDT 24
Finished Jul 03 05:04:32 PM PDT 24
Peak memory 218140 kb
Host smart-aa65c4e8-6a38-475e-8ce6-936615e151df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318941501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2318941501
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1845989201
Short name T225
Test name
Test status
Simulation time 627458139 ps
CPU time 15 seconds
Started Jul 03 05:04:25 PM PDT 24
Finished Jul 03 05:04:42 PM PDT 24
Peak memory 225988 kb
Host smart-b773492d-1b5d-41a6-9a80-4c8536378c08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845989201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1845989201
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.1563758816
Short name T275
Test name
Test status
Simulation time 693598066 ps
CPU time 7.73 seconds
Started Jul 03 05:04:20 PM PDT 24
Finished Jul 03 05:04:29 PM PDT 24
Peak memory 218100 kb
Host smart-4169239e-0a34-418a-8c04-6fb6bfc0e3a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563758816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
1563758816
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.1633515579
Short name T497
Test name
Test status
Simulation time 348403902 ps
CPU time 12.97 seconds
Started Jul 03 05:04:43 PM PDT 24
Finished Jul 03 05:04:57 PM PDT 24
Peak memory 225952 kb
Host smart-77e5df7d-2f3d-452c-a4d7-0de23ece453f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633515579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.1633515579
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.1385214606
Short name T772
Test name
Test status
Simulation time 243405626 ps
CPU time 2.72 seconds
Started Jul 03 05:04:25 PM PDT 24
Finished Jul 03 05:04:30 PM PDT 24
Peak memory 214644 kb
Host smart-2c41fbcb-2878-4f94-abf2-05c8543c4b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385214606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1385214606
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.1673818025
Short name T471
Test name
Test status
Simulation time 967398035 ps
CPU time 28.77 seconds
Started Jul 03 05:04:24 PM PDT 24
Finished Jul 03 05:04:55 PM PDT 24
Peak memory 250928 kb
Host smart-37c3dc87-7a65-47a8-887c-7bf6aacf024b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673818025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1673818025
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.2865419902
Short name T834
Test name
Test status
Simulation time 121950070 ps
CPU time 8.53 seconds
Started Jul 03 05:04:24 PM PDT 24
Finished Jul 03 05:04:35 PM PDT 24
Peak memory 250880 kb
Host smart-bd10e0de-fffb-4b48-9354-69858bb3cb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865419902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2865419902
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.1316600215
Short name T377
Test name
Test status
Simulation time 50133048 ps
CPU time 0.86 seconds
Started Jul 03 05:04:26 PM PDT 24
Finished Jul 03 05:04:30 PM PDT 24
Peak memory 212908 kb
Host smart-9aa12185-8a26-4c0e-9d32-fedd90b4bef3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316600215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.1316600215
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.1397998001
Short name T743
Test name
Test status
Simulation time 24866453 ps
CPU time 1.19 seconds
Started Jul 03 05:04:25 PM PDT 24
Finished Jul 03 05:04:28 PM PDT 24
Peak memory 208960 kb
Host smart-2e086e36-ff1f-4c35-ada5-f44f37731761
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397998001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1397998001
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.1673119485
Short name T336
Test name
Test status
Simulation time 1323927581 ps
CPU time 14.9 seconds
Started Jul 03 05:04:26 PM PDT 24
Finished Jul 03 05:04:44 PM PDT 24
Peak memory 218176 kb
Host smart-c731ccbf-2581-4c7e-85c9-19e9be1a8873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673119485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.1673119485
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.516849536
Short name T53
Test name
Test status
Simulation time 113030685 ps
CPU time 1.78 seconds
Started Jul 03 05:04:49 PM PDT 24
Finished Jul 03 05:05:01 PM PDT 24
Peak memory 217016 kb
Host smart-bcd9ce65-4d36-4e54-abb9-00b244b60b83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516849536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.516849536
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.3586165650
Short name T765
Test name
Test status
Simulation time 4066557831 ps
CPU time 32.97 seconds
Started Jul 03 05:04:26 PM PDT 24
Finished Jul 03 05:05:02 PM PDT 24
Peak memory 218648 kb
Host smart-b334484e-8329-48eb-abc2-fb0a06649618
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586165650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.3586165650
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.1234436980
Short name T759
Test name
Test status
Simulation time 208748928 ps
CPU time 3.83 seconds
Started Jul 03 05:04:30 PM PDT 24
Finished Jul 03 05:04:35 PM PDT 24
Peak memory 218184 kb
Host smart-204571d6-72d9-430b-876c-6686eb08690a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234436980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.1234436980
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.140310415
Short name T26
Test name
Test status
Simulation time 277525295 ps
CPU time 8.17 seconds
Started Jul 03 05:04:24 PM PDT 24
Finished Jul 03 05:04:35 PM PDT 24
Peak memory 217676 kb
Host smart-f7008a87-e55a-4818-9bf2-8cbe20a12099
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140310415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.
140310415
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.153023465
Short name T731
Test name
Test status
Simulation time 3928902744 ps
CPU time 77.73 seconds
Started Jul 03 05:04:26 PM PDT 24
Finished Jul 03 05:05:47 PM PDT 24
Peak memory 250992 kb
Host smart-47ad94f7-fb72-42ed-a285-e027350d60e7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153023465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_state_failure.153023465
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3263278680
Short name T284
Test name
Test status
Simulation time 8843613426 ps
CPU time 34.04 seconds
Started Jul 03 05:04:25 PM PDT 24
Finished Jul 03 05:05:01 PM PDT 24
Peak memory 250592 kb
Host smart-634e9739-4b2c-4f6e-a7cb-e73b1b0e9910
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263278680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.3263278680
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.43116146
Short name T797
Test name
Test status
Simulation time 237832560 ps
CPU time 3.54 seconds
Started Jul 03 05:04:39 PM PDT 24
Finished Jul 03 05:04:44 PM PDT 24
Peak memory 218168 kb
Host smart-63eb2cd5-4f02-48b0-ad97-be4a70f0f0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43116146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.43116146
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.2046501583
Short name T474
Test name
Test status
Simulation time 2029645858 ps
CPU time 15.75 seconds
Started Jul 03 05:04:22 PM PDT 24
Finished Jul 03 05:04:39 PM PDT 24
Peak memory 226264 kb
Host smart-53b7980b-0b4f-4385-b5a1-3eb9bd771254
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046501583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2046501583
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.4191746971
Short name T611
Test name
Test status
Simulation time 840815392 ps
CPU time 12.07 seconds
Started Jul 03 05:04:27 PM PDT 24
Finished Jul 03 05:04:41 PM PDT 24
Peak memory 225964 kb
Host smart-33cb98fa-5514-4a43-910d-50e1725ffa91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191746971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.4191746971
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3327594188
Short name T274
Test name
Test status
Simulation time 3038802905 ps
CPU time 9.76 seconds
Started Jul 03 05:04:32 PM PDT 24
Finished Jul 03 05:04:43 PM PDT 24
Peak memory 218928 kb
Host smart-06ab64dc-19dc-4edd-9e7a-3e1c5a456dd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327594188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
3327594188
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2941184074
Short name T411
Test name
Test status
Simulation time 1866910525 ps
CPU time 8.9 seconds
Started Jul 03 05:04:25 PM PDT 24
Finished Jul 03 05:04:36 PM PDT 24
Peak memory 218236 kb
Host smart-43868b81-eeb7-4892-9ec5-5330627ef134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941184074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2941184074
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.3184578626
Short name T740
Test name
Test status
Simulation time 88885691 ps
CPU time 2.09 seconds
Started Jul 03 05:04:34 PM PDT 24
Finished Jul 03 05:04:37 PM PDT 24
Peak memory 214060 kb
Host smart-1deb6c8e-e081-49fe-a349-ac9841928d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184578626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.3184578626
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.3498368316
Short name T854
Test name
Test status
Simulation time 298174679 ps
CPU time 32.85 seconds
Started Jul 03 05:04:22 PM PDT 24
Finished Jul 03 05:04:56 PM PDT 24
Peak memory 250892 kb
Host smart-d1c0ce71-3793-4343-860e-36ba98528dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498368316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.3498368316
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2606871848
Short name T424
Test name
Test status
Simulation time 66942648 ps
CPU time 8.24 seconds
Started Jul 03 05:04:16 PM PDT 24
Finished Jul 03 05:04:25 PM PDT 24
Peak memory 250828 kb
Host smart-f00453eb-05ae-4b9f-a190-70d8c90dc4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606871848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2606871848
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.4104859097
Short name T450
Test name
Test status
Simulation time 4199478374 ps
CPU time 50.96 seconds
Started Jul 03 05:04:27 PM PDT 24
Finished Jul 03 05:05:20 PM PDT 24
Peak memory 259204 kb
Host smart-b36a21c6-c36d-42ea-ad5b-e27d42fb84f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104859097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.4104859097
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.108388427
Short name T863
Test name
Test status
Simulation time 34781931 ps
CPU time 0.99 seconds
Started Jul 03 05:04:25 PM PDT 24
Finished Jul 03 05:04:29 PM PDT 24
Peak memory 212852 kb
Host smart-9f4f1628-7568-41dd-af86-1fc252d2354c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108388427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.108388427
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2184590257
Short name T577
Test name
Test status
Simulation time 37891705 ps
CPU time 0.93 seconds
Started Jul 03 05:04:23 PM PDT 24
Finished Jul 03 05:04:25 PM PDT 24
Peak memory 208864 kb
Host smart-0f948d29-9650-4d44-b796-2cd44c831969
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184590257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2184590257
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1552965145
Short name T521
Test name
Test status
Simulation time 5930818751 ps
CPU time 10.4 seconds
Started Jul 03 05:04:26 PM PDT 24
Finished Jul 03 05:04:39 PM PDT 24
Peak memory 218232 kb
Host smart-aac1a025-00cf-48d5-b623-62cd4efe427b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552965145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1552965145
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.171000590
Short name T436
Test name
Test status
Simulation time 313960570 ps
CPU time 1.43 seconds
Started Jul 03 05:04:25 PM PDT 24
Finished Jul 03 05:04:29 PM PDT 24
Peak memory 217072 kb
Host smart-ca27ae81-43f6-4a78-9452-558992c05e93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171000590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.171000590
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.1583290410
Short name T62
Test name
Test status
Simulation time 3045064040 ps
CPU time 76.46 seconds
Started Jul 03 05:04:25 PM PDT 24
Finished Jul 03 05:05:44 PM PDT 24
Peak memory 218340 kb
Host smart-b61ada04-6fb8-4f76-83b1-e9849ee1f0f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583290410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.1583290410
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1785604711
Short name T2
Test name
Test status
Simulation time 1430697448 ps
CPU time 11.72 seconds
Started Jul 03 05:04:24 PM PDT 24
Finished Jul 03 05:04:38 PM PDT 24
Peak memory 223348 kb
Host smart-5dec9874-4e73-4b20-9685-52fecde2f6f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785604711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.1785604711
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.3616809739
Short name T352
Test name
Test status
Simulation time 777848975 ps
CPU time 4.42 seconds
Started Jul 03 05:04:43 PM PDT 24
Finished Jul 03 05:04:48 PM PDT 24
Peak memory 217612 kb
Host smart-6e38251a-57de-4136-aa93-0221ff41e584
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616809739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.3616809739
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.1016100493
Short name T694
Test name
Test status
Simulation time 1243373926 ps
CPU time 56.84 seconds
Started Jul 03 05:04:27 PM PDT 24
Finished Jul 03 05:05:26 PM PDT 24
Peak memory 267328 kb
Host smart-0e31d1d9-61e6-4112-9962-29f76a2ca822
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016100493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.1016100493
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2963230415
Short name T372
Test name
Test status
Simulation time 717444919 ps
CPU time 26.32 seconds
Started Jul 03 05:04:23 PM PDT 24
Finished Jul 03 05:04:51 PM PDT 24
Peak memory 250884 kb
Host smart-632e8e17-779d-49dc-b789-663377a74e8e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963230415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.2963230415
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3532714254
Short name T804
Test name
Test status
Simulation time 72832625 ps
CPU time 3.12 seconds
Started Jul 03 05:04:33 PM PDT 24
Finished Jul 03 05:04:36 PM PDT 24
Peak memory 222456 kb
Host smart-cdf9b864-ec82-46d7-8eab-6eff6e8e33dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532714254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3532714254
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3208400778
Short name T304
Test name
Test status
Simulation time 1450426532 ps
CPU time 21.11 seconds
Started Jul 03 05:04:22 PM PDT 24
Finished Jul 03 05:04:50 PM PDT 24
Peak memory 225940 kb
Host smart-d2504112-eddc-458e-988a-d49f51b14a2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208400778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3208400778
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3237361193
Short name T534
Test name
Test status
Simulation time 236480946 ps
CPU time 11.63 seconds
Started Jul 03 05:04:19 PM PDT 24
Finished Jul 03 05:04:32 PM PDT 24
Peak memory 225988 kb
Host smart-98011c3e-1ddd-43e5-bb22-ea75296f2aa3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237361193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.3237361193
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.155089071
Short name T224
Test name
Test status
Simulation time 3072912997 ps
CPU time 10.26 seconds
Started Jul 03 05:04:36 PM PDT 24
Finished Jul 03 05:04:46 PM PDT 24
Peak memory 218200 kb
Host smart-e25888c1-aec8-4a68-b8cd-fce8573a8e47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155089071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.155089071
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.1383331644
Short name T758
Test name
Test status
Simulation time 955208192 ps
CPU time 7.78 seconds
Started Jul 03 05:04:55 PM PDT 24
Finished Jul 03 05:05:03 PM PDT 24
Peak memory 225324 kb
Host smart-37b73aa7-5e45-43bf-bb5b-27fccd0b98cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383331644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.1383331644
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.665897660
Short name T156
Test name
Test status
Simulation time 98136927 ps
CPU time 2.18 seconds
Started Jul 03 05:04:28 PM PDT 24
Finished Jul 03 05:04:32 PM PDT 24
Peak memory 217504 kb
Host smart-5270c06a-c514-43fb-b65d-b7bb0cdd86e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665897660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.665897660
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.625184754
Short name T588
Test name
Test status
Simulation time 966247969 ps
CPU time 22.78 seconds
Started Jul 03 05:04:26 PM PDT 24
Finished Jul 03 05:04:51 PM PDT 24
Peak memory 250936 kb
Host smart-f24ac92b-b44e-410d-a44e-e5ec516ab013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625184754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.625184754
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2804332747
Short name T333
Test name
Test status
Simulation time 49939482 ps
CPU time 7.3 seconds
Started Jul 03 05:04:25 PM PDT 24
Finished Jul 03 05:04:35 PM PDT 24
Peak memory 250912 kb
Host smart-4999562a-cd04-48ae-8c34-c521c6113eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804332747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2804332747
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.2566601941
Short name T366
Test name
Test status
Simulation time 34149561843 ps
CPU time 282.62 seconds
Started Jul 03 05:04:30 PM PDT 24
Finished Jul 03 05:09:14 PM PDT 24
Peak memory 275728 kb
Host smart-1fec84d1-e130-452c-91a7-70bbfc003099
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566601941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.2566601941
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2218570505
Short name T305
Test name
Test status
Simulation time 30186185 ps
CPU time 0.84 seconds
Started Jul 03 05:04:45 PM PDT 24
Finished Jul 03 05:04:47 PM PDT 24
Peak memory 211732 kb
Host smart-66c0f809-e617-4c11-8f5a-90c8da6955a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218570505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.2218570505
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.2014646784
Short name T600
Test name
Test status
Simulation time 79325012 ps
CPU time 1.05 seconds
Started Jul 03 05:03:38 PM PDT 24
Finished Jul 03 05:03:40 PM PDT 24
Peak memory 208872 kb
Host smart-42669024-03e7-4560-a635-9731b929764a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014646784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2014646784
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1695250198
Short name T590
Test name
Test status
Simulation time 25942708 ps
CPU time 0.76 seconds
Started Jul 03 05:03:32 PM PDT 24
Finished Jul 03 05:03:34 PM PDT 24
Peak memory 208876 kb
Host smart-c4f0606e-3b28-468c-b2ad-0c013aa4daa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695250198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1695250198
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2218642
Short name T530
Test name
Test status
Simulation time 2657403157 ps
CPU time 16.71 seconds
Started Jul 03 05:04:04 PM PDT 24
Finished Jul 03 05:04:21 PM PDT 24
Peak memory 218904 kb
Host smart-997694ef-c71f-4cb7-af99-7619276a7701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2218642
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.2535350451
Short name T505
Test name
Test status
Simulation time 2739474730 ps
CPU time 4.62 seconds
Started Jul 03 05:04:03 PM PDT 24
Finished Jul 03 05:04:08 PM PDT 24
Peak memory 217412 kb
Host smart-f2e440e7-d275-469f-b6a8-698deb36dd09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535350451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.2535350451
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.3365810764
Short name T597
Test name
Test status
Simulation time 7212697308 ps
CPU time 27.71 seconds
Started Jul 03 05:03:46 PM PDT 24
Finished Jul 03 05:04:14 PM PDT 24
Peak memory 218900 kb
Host smart-f0982f77-b601-4a13-adae-6d2e838cca81
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365810764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.3365810764
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.3913124288
Short name T183
Test name
Test status
Simulation time 323215038 ps
CPU time 5.08 seconds
Started Jul 03 05:03:59 PM PDT 24
Finished Jul 03 05:04:05 PM PDT 24
Peak memory 217788 kb
Host smart-546a5f03-d34b-4a89-8454-db473306bbf8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913124288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.3
913124288
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.1078673072
Short name T572
Test name
Test status
Simulation time 147101521 ps
CPU time 3.13 seconds
Started Jul 03 05:04:10 PM PDT 24
Finished Jul 03 05:04:14 PM PDT 24
Peak memory 218164 kb
Host smart-3d5b53d0-fdb2-4b65-82dd-28c6be181927
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078673072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.1078673072
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.2734501926
Short name T271
Test name
Test status
Simulation time 2974962587 ps
CPU time 14.71 seconds
Started Jul 03 05:03:43 PM PDT 24
Finished Jul 03 05:03:58 PM PDT 24
Peak memory 217716 kb
Host smart-5020c83f-47a9-4ae7-b1a8-c39dc7b16fc2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734501926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.2734501926
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.2156296511
Short name T80
Test name
Test status
Simulation time 1228634260 ps
CPU time 3.93 seconds
Started Jul 03 05:03:46 PM PDT 24
Finished Jul 03 05:03:50 PM PDT 24
Peak memory 217668 kb
Host smart-0459fc09-82aa-4f3b-8077-aadf0268f0f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156296511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
2156296511
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.3994280795
Short name T245
Test name
Test status
Simulation time 3467994962 ps
CPU time 50.25 seconds
Started Jul 03 05:03:33 PM PDT 24
Finished Jul 03 05:04:23 PM PDT 24
Peak memory 275520 kb
Host smart-2326ab5e-6d62-4248-a03f-a37b87ed7c49
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994280795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.3994280795
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.126675572
Short name T457
Test name
Test status
Simulation time 469939741 ps
CPU time 13.59 seconds
Started Jul 03 05:03:43 PM PDT 24
Finished Jul 03 05:03:57 PM PDT 24
Peak memory 250916 kb
Host smart-c0d8fb29-2115-46fb-a9bb-add90a185956
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126675572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.126675572
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2383067878
Short name T12
Test name
Test status
Simulation time 238306207 ps
CPU time 3.02 seconds
Started Jul 03 05:04:08 PM PDT 24
Finished Jul 03 05:04:12 PM PDT 24
Peak memory 218120 kb
Host smart-54f2553f-f95a-4917-8736-9ff78ce1a9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383067878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2383067878
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3246248844
Short name T92
Test name
Test status
Simulation time 2216215974 ps
CPU time 21.5 seconds
Started Jul 03 05:03:35 PM PDT 24
Finished Jul 03 05:03:57 PM PDT 24
Peak memory 284364 kb
Host smart-9bc2e0c9-99ae-4699-8713-1ee98dd62b90
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246248844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3246248844
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.663333910
Short name T670
Test name
Test status
Simulation time 505917882 ps
CPU time 11.02 seconds
Started Jul 03 05:03:48 PM PDT 24
Finished Jul 03 05:04:00 PM PDT 24
Peak memory 225768 kb
Host smart-962082c9-9b98-4075-b0fa-06978ee9e32d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663333910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_dig
est.663333910
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.467696872
Short name T690
Test name
Test status
Simulation time 547897509 ps
CPU time 9.23 seconds
Started Jul 03 05:03:39 PM PDT 24
Finished Jul 03 05:03:49 PM PDT 24
Peak memory 218208 kb
Host smart-888f14cc-2808-43e3-b427-a00028c4cd94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467696872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.467696872
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.374235229
Short name T515
Test name
Test status
Simulation time 289246615 ps
CPU time 7.5 seconds
Started Jul 03 05:03:32 PM PDT 24
Finished Jul 03 05:03:40 PM PDT 24
Peak memory 218264 kb
Host smart-d8cfa5a1-d2a6-4350-9bc2-157da12bc0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374235229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.374235229
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.1932580892
Short name T561
Test name
Test status
Simulation time 42763379 ps
CPU time 1.28 seconds
Started Jul 03 05:03:43 PM PDT 24
Finished Jul 03 05:03:45 PM PDT 24
Peak memory 213712 kb
Host smart-9b5117f7-cbc9-4c22-bc44-bf5af787c7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932580892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1932580892
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.2686851677
Short name T282
Test name
Test status
Simulation time 764192134 ps
CPU time 16.81 seconds
Started Jul 03 05:03:39 PM PDT 24
Finished Jul 03 05:03:59 PM PDT 24
Peak memory 250896 kb
Host smart-70c5a470-1e50-4c29-867b-84bd115ce9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686851677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.2686851677
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.2531422299
Short name T363
Test name
Test status
Simulation time 419643155 ps
CPU time 8.04 seconds
Started Jul 03 05:04:02 PM PDT 24
Finished Jul 03 05:04:15 PM PDT 24
Peak memory 247284 kb
Host smart-767513d8-406e-41bf-828a-274deac1fdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531422299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2531422299
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1726908558
Short name T64
Test name
Test status
Simulation time 1375592598 ps
CPU time 45.27 seconds
Started Jul 03 05:03:31 PM PDT 24
Finished Jul 03 05:04:16 PM PDT 24
Peak memory 250616 kb
Host smart-afd6491e-462d-4508-9d7d-ed3b4acf756f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726908558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1726908558
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1967006094
Short name T712
Test name
Test status
Simulation time 28903127 ps
CPU time 0.9 seconds
Started Jul 03 05:03:43 PM PDT 24
Finished Jul 03 05:03:44 PM PDT 24
Peak memory 211892 kb
Host smart-0346f3d9-00b0-4761-86e7-b8e8225e1b2d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967006094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.1967006094
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.443217943
Short name T74
Test name
Test status
Simulation time 62594277 ps
CPU time 1.16 seconds
Started Jul 03 05:04:32 PM PDT 24
Finished Jul 03 05:04:34 PM PDT 24
Peak memory 208996 kb
Host smart-134a6146-beb8-463c-acd7-b6cb6b445933
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443217943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.443217943
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.2497143443
Short name T180
Test name
Test status
Simulation time 568421531 ps
CPU time 13.39 seconds
Started Jul 03 05:04:33 PM PDT 24
Finished Jul 03 05:04:47 PM PDT 24
Peak memory 225968 kb
Host smart-284daf80-130d-4681-89b3-2326874b060a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497143443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2497143443
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.3763982421
Short name T407
Test name
Test status
Simulation time 10343716857 ps
CPU time 18.66 seconds
Started Jul 03 05:04:30 PM PDT 24
Finished Jul 03 05:04:50 PM PDT 24
Peak memory 217644 kb
Host smart-e479a1f1-5629-4c4b-ad13-72cedca2bf25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763982421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.3763982421
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.3145938268
Short name T323
Test name
Test status
Simulation time 100028312 ps
CPU time 3.27 seconds
Started Jul 03 05:04:33 PM PDT 24
Finished Jul 03 05:04:37 PM PDT 24
Peak memory 218136 kb
Host smart-a1103520-6567-4b3b-882d-e6c448f64b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145938268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.3145938268
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.927085109
Short name T766
Test name
Test status
Simulation time 1213253549 ps
CPU time 15.4 seconds
Started Jul 03 05:04:40 PM PDT 24
Finished Jul 03 05:04:56 PM PDT 24
Peak memory 225952 kb
Host smart-994311bf-9f85-4d05-a0d2-7750b61f053c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927085109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.927085109
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2305693180
Short name T422
Test name
Test status
Simulation time 635832105 ps
CPU time 9.58 seconds
Started Jul 03 05:04:26 PM PDT 24
Finished Jul 03 05:04:39 PM PDT 24
Peak memory 225912 kb
Host smart-71f0e507-9a4c-4399-8473-0c799e33e625
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305693180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.2305693180
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1769737683
Short name T756
Test name
Test status
Simulation time 520498371 ps
CPU time 7.44 seconds
Started Jul 03 05:04:25 PM PDT 24
Finished Jul 03 05:04:35 PM PDT 24
Peak memory 218172 kb
Host smart-7f49f8f7-46ed-4931-ab49-4def82cd5965
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769737683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1769737683
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.2843883932
Short name T859
Test name
Test status
Simulation time 3439420399 ps
CPU time 10.1 seconds
Started Jul 03 05:04:28 PM PDT 24
Finished Jul 03 05:04:40 PM PDT 24
Peak memory 226000 kb
Host smart-cd33f7f0-8dcf-4f30-8bfc-fcb240c81d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843883932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2843883932
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.3681068368
Short name T423
Test name
Test status
Simulation time 44045364 ps
CPU time 1.6 seconds
Started Jul 03 05:04:26 PM PDT 24
Finished Jul 03 05:04:31 PM PDT 24
Peak memory 217632 kb
Host smart-97fcfa44-d173-4e3a-acb0-4e550a4e1e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681068368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3681068368
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.1135502818
Short name T586
Test name
Test status
Simulation time 626456933 ps
CPU time 28.82 seconds
Started Jul 03 05:04:27 PM PDT 24
Finished Jul 03 05:04:58 PM PDT 24
Peak memory 250900 kb
Host smart-023779bf-c1fb-440d-ae19-31db55aeb731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135502818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1135502818
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1427448599
Short name T427
Test name
Test status
Simulation time 344326761 ps
CPU time 6.84 seconds
Started Jul 03 05:04:21 PM PDT 24
Finished Jul 03 05:04:29 PM PDT 24
Peak memory 247224 kb
Host smart-00d94e8b-7406-4134-9819-125c6d4bbbda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427448599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1427448599
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3271716922
Short name T37
Test name
Test status
Simulation time 5248517357 ps
CPU time 58.1 seconds
Started Jul 03 05:04:23 PM PDT 24
Finished Jul 03 05:05:23 PM PDT 24
Peak memory 250932 kb
Host smart-c18f3de5-8411-4e75-b82c-30b53c030d92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271716922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3271716922
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.2067695840
Short name T146
Test name
Test status
Simulation time 5348457267 ps
CPU time 231.73 seconds
Started Jul 03 05:04:31 PM PDT 24
Finished Jul 03 05:08:23 PM PDT 24
Peak memory 273432 kb
Host smart-e56ffc27-c741-408f-bcfa-24befb4dfa10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2067695840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.2067695840
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2897365104
Short name T503
Test name
Test status
Simulation time 14826984 ps
CPU time 0.91 seconds
Started Jul 03 05:04:31 PM PDT 24
Finished Jul 03 05:04:32 PM PDT 24
Peak memory 217644 kb
Host smart-7868a339-f63b-4cab-a61e-e890d77a2126
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897365104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2897365104
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.1078080872
Short name T810
Test name
Test status
Simulation time 20687329 ps
CPU time 0.92 seconds
Started Jul 03 05:04:30 PM PDT 24
Finished Jul 03 05:04:32 PM PDT 24
Peak memory 208976 kb
Host smart-cccecca6-4237-4d84-bf47-d4cda287558f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078080872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1078080872
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.2223214320
Short name T829
Test name
Test status
Simulation time 188342222 ps
CPU time 9.78 seconds
Started Jul 03 05:04:23 PM PDT 24
Finished Jul 03 05:04:35 PM PDT 24
Peak memory 218176 kb
Host smart-736353fe-6d47-43ce-8d19-60165f4a45d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223214320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.2223214320
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.2067529796
Short name T30
Test name
Test status
Simulation time 459278827 ps
CPU time 7.73 seconds
Started Jul 03 05:04:28 PM PDT 24
Finished Jul 03 05:04:38 PM PDT 24
Peak memory 217208 kb
Host smart-c9922acd-9c23-450a-bbe7-0a9a10e47d40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067529796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.2067529796
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.3521695701
Short name T688
Test name
Test status
Simulation time 43911308 ps
CPU time 1.71 seconds
Started Jul 03 05:04:55 PM PDT 24
Finished Jul 03 05:04:57 PM PDT 24
Peak memory 218136 kb
Host smart-7ca4aa94-fa17-4a9b-9f64-28207bd78d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521695701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.3521695701
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1475743826
Short name T349
Test name
Test status
Simulation time 2083560452 ps
CPU time 7.72 seconds
Started Jul 03 05:04:53 PM PDT 24
Finished Jul 03 05:05:01 PM PDT 24
Peak memory 225936 kb
Host smart-62b0e287-9820-49ac-83f3-d63cd7d419f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475743826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1475743826
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1963876669
Short name T378
Test name
Test status
Simulation time 4772791220 ps
CPU time 11.52 seconds
Started Jul 03 05:04:28 PM PDT 24
Finished Jul 03 05:04:41 PM PDT 24
Peak memory 226012 kb
Host smart-ecf31ca4-3a91-4ca2-ac6f-6fd66953c25f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963876669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1963876669
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.401435128
Short name T649
Test name
Test status
Simulation time 327865998 ps
CPU time 8.67 seconds
Started Jul 03 05:04:41 PM PDT 24
Finished Jul 03 05:04:50 PM PDT 24
Peak memory 225992 kb
Host smart-46741f44-03cc-4507-aab9-e1ecb65a0b11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401435128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.401435128
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.1795146130
Short name T58
Test name
Test status
Simulation time 294040384 ps
CPU time 8.44 seconds
Started Jul 03 05:04:31 PM PDT 24
Finished Jul 03 05:04:40 PM PDT 24
Peak memory 225944 kb
Host smart-cd7b566f-bec4-4ce9-9f62-e325feb3ae6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795146130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1795146130
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.3379620044
Short name T329
Test name
Test status
Simulation time 146043985 ps
CPU time 1.36 seconds
Started Jul 03 05:04:37 PM PDT 24
Finished Jul 03 05:04:39 PM PDT 24
Peak memory 213568 kb
Host smart-be59c235-16ce-408e-9c5b-716e5c4b79a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379620044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3379620044
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.2875382375
Short name T153
Test name
Test status
Simulation time 638394871 ps
CPU time 29.12 seconds
Started Jul 03 05:04:25 PM PDT 24
Finished Jul 03 05:04:57 PM PDT 24
Peak memory 250948 kb
Host smart-209b922a-97b7-42eb-9169-4a9ee7c073d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875382375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2875382375
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.1091025826
Short name T717
Test name
Test status
Simulation time 357241820 ps
CPU time 8.58 seconds
Started Jul 03 05:04:25 PM PDT 24
Finished Jul 03 05:04:37 PM PDT 24
Peak memory 242808 kb
Host smart-8173c79f-bd33-4b4c-81a5-c914874e87b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091025826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1091025826
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.3082518782
Short name T500
Test name
Test status
Simulation time 19456515267 ps
CPU time 186.36 seconds
Started Jul 03 05:04:54 PM PDT 24
Finished Jul 03 05:08:01 PM PDT 24
Peak memory 267848 kb
Host smart-02d63d61-d04b-4811-ad9e-b8637fc52ae4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082518782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.3082518782
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.2493642733
Short name T77
Test name
Test status
Simulation time 18147878920 ps
CPU time 801.78 seconds
Started Jul 03 05:04:30 PM PDT 24
Finished Jul 03 05:17:53 PM PDT 24
Peak memory 464080 kb
Host smart-8046785a-061b-41ff-8bab-ed01d865d430
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2493642733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.2493642733
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.357014646
Short name T315
Test name
Test status
Simulation time 13766054 ps
CPU time 0.89 seconds
Started Jul 03 05:04:23 PM PDT 24
Finished Jul 03 05:04:25 PM PDT 24
Peak memory 211872 kb
Host smart-52257eab-fbb5-4c88-bb5f-3255caf39fbd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357014646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.357014646
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.238290637
Short name T294
Test name
Test status
Simulation time 12697673 ps
CPU time 0.97 seconds
Started Jul 03 05:04:27 PM PDT 24
Finished Jul 03 05:04:30 PM PDT 24
Peak memory 208904 kb
Host smart-78b4e08b-360e-4cde-83c6-cba20ec554e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238290637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.238290637
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2053633960
Short name T847
Test name
Test status
Simulation time 1188696053 ps
CPU time 10.19 seconds
Started Jul 03 05:04:48 PM PDT 24
Finished Jul 03 05:04:58 PM PDT 24
Peak memory 218152 kb
Host smart-e1420ba5-7adb-4c14-99c8-77e71df87980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053633960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2053633960
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.939141847
Short name T667
Test name
Test status
Simulation time 2944542537 ps
CPU time 16.32 seconds
Started Jul 03 05:04:25 PM PDT 24
Finished Jul 03 05:04:44 PM PDT 24
Peak memory 217564 kb
Host smart-ce8fa64e-33e2-4753-9960-81fba8294b7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939141847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.939141847
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.1289676678
Short name T259
Test name
Test status
Simulation time 705088657 ps
CPU time 4.27 seconds
Started Jul 03 05:04:26 PM PDT 24
Finished Jul 03 05:04:33 PM PDT 24
Peak memory 222024 kb
Host smart-d854f519-9e0f-4f50-aa39-c2e72f49cd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289676678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1289676678
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.23333660
Short name T538
Test name
Test status
Simulation time 2060301542 ps
CPU time 11.72 seconds
Started Jul 03 05:04:26 PM PDT 24
Finished Jul 03 05:04:40 PM PDT 24
Peak memory 218168 kb
Host smart-4eacd274-5a18-4194-bc81-5c8b6624703b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23333660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.23333660
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.415726732
Short name T655
Test name
Test status
Simulation time 683547452 ps
CPU time 7.37 seconds
Started Jul 03 05:04:27 PM PDT 24
Finished Jul 03 05:04:37 PM PDT 24
Peak memory 226028 kb
Host smart-953c7843-b738-41b3-b340-2ae40b334b5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415726732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_di
gest.415726732
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.757647658
Short name T506
Test name
Test status
Simulation time 1063225884 ps
CPU time 8.34 seconds
Started Jul 03 05:04:25 PM PDT 24
Finished Jul 03 05:04:36 PM PDT 24
Peak memory 218144 kb
Host smart-0c9eaa96-e91c-42d9-b114-3e4d4a20ff73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757647658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.757647658
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.1676096983
Short name T221
Test name
Test status
Simulation time 786732115 ps
CPU time 6.94 seconds
Started Jul 03 05:04:25 PM PDT 24
Finished Jul 03 05:04:35 PM PDT 24
Peak memory 225436 kb
Host smart-beebd8fc-a805-4cf4-8022-61f1d74116dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676096983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1676096983
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.224093499
Short name T237
Test name
Test status
Simulation time 120905077 ps
CPU time 3.18 seconds
Started Jul 03 05:04:24 PM PDT 24
Finished Jul 03 05:04:29 PM PDT 24
Peak memory 217652 kb
Host smart-aec0d821-2c33-4dad-9a4b-6c3fbe06f7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224093499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.224093499
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.59017469
Short name T778
Test name
Test status
Simulation time 514356101 ps
CPU time 22.35 seconds
Started Jul 03 05:04:21 PM PDT 24
Finished Jul 03 05:04:45 PM PDT 24
Peak memory 250968 kb
Host smart-9d097a1e-407e-4263-82bc-f6bec82a5469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59017469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.59017469
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1687954702
Short name T324
Test name
Test status
Simulation time 209075297 ps
CPU time 7.94 seconds
Started Jul 03 05:04:26 PM PDT 24
Finished Jul 03 05:04:37 PM PDT 24
Peak memory 250900 kb
Host smart-8cbf3f86-fc25-492c-b784-94ea0141cabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687954702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1687954702
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.850256439
Short name T796
Test name
Test status
Simulation time 4345213202 ps
CPU time 108.29 seconds
Started Jul 03 05:04:27 PM PDT 24
Finished Jul 03 05:06:18 PM PDT 24
Peak memory 277848 kb
Host smart-e430cd1c-3ce5-40b0-bd95-2b71ca83f892
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850256439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.850256439
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3563198593
Short name T165
Test name
Test status
Simulation time 46951145 ps
CPU time 0.85 seconds
Started Jul 03 05:04:30 PM PDT 24
Finished Jul 03 05:04:32 PM PDT 24
Peak memory 211820 kb
Host smart-814c58d2-c8f1-4993-870c-8300ec4fb7ee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563198593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.3563198593
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.3878212904
Short name T849
Test name
Test status
Simulation time 44504590 ps
CPU time 0.99 seconds
Started Jul 03 05:04:42 PM PDT 24
Finished Jul 03 05:04:44 PM PDT 24
Peak memory 208948 kb
Host smart-cf653596-4090-424b-b3fe-e05c50204aeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878212904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3878212904
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2863062769
Short name T415
Test name
Test status
Simulation time 621514614 ps
CPU time 10.68 seconds
Started Jul 03 05:04:38 PM PDT 24
Finished Jul 03 05:04:49 PM PDT 24
Peak memory 218180 kb
Host smart-672c1804-ffcd-4d94-8612-fed4bcbb745d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863062769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2863062769
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.3433990948
Short name T575
Test name
Test status
Simulation time 1328110847 ps
CPU time 7.38 seconds
Started Jul 03 05:04:38 PM PDT 24
Finished Jul 03 05:04:46 PM PDT 24
Peak memory 217328 kb
Host smart-87b9996e-8d04-4ae3-b8a3-92bef568a10b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433990948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.3433990948
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2315695110
Short name T826
Test name
Test status
Simulation time 74935365 ps
CPU time 1.78 seconds
Started Jul 03 05:04:22 PM PDT 24
Finished Jul 03 05:04:26 PM PDT 24
Peak memory 218136 kb
Host smart-ac3223db-b529-43f0-83cb-f86a617fcbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315695110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2315695110
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.3664631668
Short name T484
Test name
Test status
Simulation time 2290074105 ps
CPU time 16.28 seconds
Started Jul 03 05:04:34 PM PDT 24
Finished Jul 03 05:04:51 PM PDT 24
Peak memory 226016 kb
Host smart-34fa7c44-156f-4a3b-ac46-9aa6d4a90820
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664631668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.3664631668
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.4028243828
Short name T483
Test name
Test status
Simulation time 378142792 ps
CPU time 9.56 seconds
Started Jul 03 05:04:26 PM PDT 24
Finished Jul 03 05:04:38 PM PDT 24
Peak memory 225960 kb
Host smart-f244c467-eda9-4d83-9984-495c4328fefd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028243828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.4028243828
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.338462782
Short name T748
Test name
Test status
Simulation time 346478115 ps
CPU time 7.41 seconds
Started Jul 03 05:04:22 PM PDT 24
Finished Jul 03 05:04:31 PM PDT 24
Peak memory 225948 kb
Host smart-bf55b6e7-0a6a-4a42-a319-1dec794aa640
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338462782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.338462782
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.660961906
Short name T508
Test name
Test status
Simulation time 444039499 ps
CPU time 8.07 seconds
Started Jul 03 05:04:23 PM PDT 24
Finished Jul 03 05:04:33 PM PDT 24
Peak memory 224572 kb
Host smart-0a436720-c07a-4036-9464-b2c40926e3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660961906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.660961906
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.3687828000
Short name T365
Test name
Test status
Simulation time 45453537 ps
CPU time 1.21 seconds
Started Jul 03 05:04:23 PM PDT 24
Finished Jul 03 05:04:26 PM PDT 24
Peak memory 213676 kb
Host smart-1e199c62-6dc4-492c-9cf7-0b35fb21b3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687828000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.3687828000
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.546923668
Short name T668
Test name
Test status
Simulation time 183886343 ps
CPU time 22.25 seconds
Started Jul 03 05:04:25 PM PDT 24
Finished Jul 03 05:04:49 PM PDT 24
Peak memory 250776 kb
Host smart-fc1756ad-512a-4554-868e-f08f4f5e7ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546923668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.546923668
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.856152468
Short name T714
Test name
Test status
Simulation time 59626478 ps
CPU time 7.3 seconds
Started Jul 03 05:04:40 PM PDT 24
Finished Jul 03 05:04:48 PM PDT 24
Peak memory 250896 kb
Host smart-c53a734b-b185-4dcd-887e-73153fca7f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856152468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.856152468
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3075928741
Short name T364
Test name
Test status
Simulation time 6930801268 ps
CPU time 201.05 seconds
Started Jul 03 05:04:34 PM PDT 24
Finished Jul 03 05:08:00 PM PDT 24
Peak memory 226020 kb
Host smart-da3299e3-2634-4b74-ba8c-a5f7be895e17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075928741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3075928741
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.4000971639
Short name T162
Test name
Test status
Simulation time 33712605432 ps
CPU time 778.3 seconds
Started Jul 03 05:04:28 PM PDT 24
Finished Jul 03 05:17:28 PM PDT 24
Peak memory 415472 kb
Host smart-4f117905-a87e-48cb-a4cf-25446da32e9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4000971639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.4000971639
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2095298654
Short name T317
Test name
Test status
Simulation time 12893660 ps
CPU time 1.05 seconds
Started Jul 03 05:04:29 PM PDT 24
Finished Jul 03 05:04:31 PM PDT 24
Peak memory 211840 kb
Host smart-ec7648a0-0a7a-40e6-8212-5022f2a092b5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095298654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.2095298654
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.3274313552
Short name T242
Test name
Test status
Simulation time 24395237 ps
CPU time 1.04 seconds
Started Jul 03 05:04:25 PM PDT 24
Finished Jul 03 05:04:28 PM PDT 24
Peak memory 208940 kb
Host smart-fcfffa83-2462-4546-aaf3-86699fc661ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274313552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3274313552
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.3239638223
Short name T821
Test name
Test status
Simulation time 368607737 ps
CPU time 11.33 seconds
Started Jul 03 05:04:26 PM PDT 24
Finished Jul 03 05:04:40 PM PDT 24
Peak memory 218036 kb
Host smart-5f0273d9-7ea1-4c03-8029-333e0ff3a91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239638223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3239638223
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.1470538207
Short name T784
Test name
Test status
Simulation time 1149267124 ps
CPU time 4.24 seconds
Started Jul 03 05:04:43 PM PDT 24
Finished Jul 03 05:04:47 PM PDT 24
Peak memory 216996 kb
Host smart-8453f91f-5723-4c19-bf75-ef7759e67b37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470538207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.1470538207
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3060755353
Short name T472
Test name
Test status
Simulation time 48944890 ps
CPU time 1.72 seconds
Started Jul 03 05:04:28 PM PDT 24
Finished Jul 03 05:04:32 PM PDT 24
Peak memory 218048 kb
Host smart-d3e0ec45-9fba-40da-8e4f-81aaa79c9be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060755353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3060755353
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2825395931
Short name T478
Test name
Test status
Simulation time 412703933 ps
CPU time 10.96 seconds
Started Jul 03 05:04:36 PM PDT 24
Finished Jul 03 05:04:48 PM PDT 24
Peak memory 225952 kb
Host smart-45a72aa8-b712-4084-895c-e43207a0add1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825395931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.2825395931
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2059060861
Short name T637
Test name
Test status
Simulation time 274883411 ps
CPU time 6.35 seconds
Started Jul 03 05:04:24 PM PDT 24
Finished Jul 03 05:04:33 PM PDT 24
Peak memory 218148 kb
Host smart-f3c7dad0-a0f6-403e-a81a-6d3d2d0c6637
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059060861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
2059060861
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.201012156
Short name T780
Test name
Test status
Simulation time 644813505 ps
CPU time 7.58 seconds
Started Jul 03 05:04:42 PM PDT 24
Finished Jul 03 05:04:50 PM PDT 24
Peak memory 224640 kb
Host smart-e616de22-e68e-4de3-a8ce-c3076ba07e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201012156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.201012156
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.75286450
Short name T87
Test name
Test status
Simulation time 58354438 ps
CPU time 1.35 seconds
Started Jul 03 05:04:36 PM PDT 24
Finished Jul 03 05:04:38 PM PDT 24
Peak memory 213636 kb
Host smart-a1e999bb-1c39-4534-a7f7-ce509f09994e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75286450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.75286450
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1017920993
Short name T651
Test name
Test status
Simulation time 1302273345 ps
CPU time 23.47 seconds
Started Jul 03 05:04:29 PM PDT 24
Finished Jul 03 05:04:54 PM PDT 24
Peak memory 250928 kb
Host smart-6e81f17e-af77-4def-ab7b-0d85c0f0100e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017920993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1017920993
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.2418320498
Short name T580
Test name
Test status
Simulation time 1399501763 ps
CPU time 6.34 seconds
Started Jul 03 05:04:36 PM PDT 24
Finished Jul 03 05:04:43 PM PDT 24
Peak memory 244688 kb
Host smart-aa5308ff-a9a7-443d-b6db-ab12f5a0c771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418320498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.2418320498
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3596899790
Short name T788
Test name
Test status
Simulation time 52243214915 ps
CPU time 166.94 seconds
Started Jul 03 05:04:28 PM PDT 24
Finished Jul 03 05:07:17 PM PDT 24
Peak memory 251340 kb
Host smart-6e2fcfd1-f495-42ca-a6ff-4e8ef073015a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596899790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3596899790
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.4265835060
Short name T147
Test name
Test status
Simulation time 18260898495 ps
CPU time 463.61 seconds
Started Jul 03 05:04:36 PM PDT 24
Finished Jul 03 05:12:20 PM PDT 24
Peak memory 316448 kb
Host smart-0ebdfb8d-642d-418b-916a-65906878f224
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4265835060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.4265835060
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2111421261
Short name T455
Test name
Test status
Simulation time 33934816 ps
CPU time 0.95 seconds
Started Jul 03 05:04:44 PM PDT 24
Finished Jul 03 05:04:45 PM PDT 24
Peak memory 211804 kb
Host smart-d729c445-183e-4e76-9479-ccea7ef1bdc9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111421261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.2111421261
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.2661416644
Short name T707
Test name
Test status
Simulation time 40626155 ps
CPU time 0.88 seconds
Started Jul 03 05:04:50 PM PDT 24
Finished Jul 03 05:04:51 PM PDT 24
Peak memory 208720 kb
Host smart-7ed741cd-2a61-4a1f-ae39-8345a37dbce1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661416644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.2661416644
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.224368462
Short name T273
Test name
Test status
Simulation time 262210718 ps
CPU time 8.88 seconds
Started Jul 03 05:04:30 PM PDT 24
Finished Jul 03 05:04:40 PM PDT 24
Peak memory 218144 kb
Host smart-87acb813-ac1c-405a-a51e-3a1e5f338ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224368462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.224368462
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.2618356780
Short name T705
Test name
Test status
Simulation time 762511195 ps
CPU time 5.15 seconds
Started Jul 03 05:04:26 PM PDT 24
Finished Jul 03 05:04:33 PM PDT 24
Peak memory 217356 kb
Host smart-42069c61-bfea-408b-acde-03b165846965
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618356780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.2618356780
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.4099424992
Short name T658
Test name
Test status
Simulation time 85662366 ps
CPU time 3.86 seconds
Started Jul 03 05:04:47 PM PDT 24
Finished Jul 03 05:04:51 PM PDT 24
Peak memory 218168 kb
Host smart-4f1e7191-638d-464f-9ec0-320c3bc9463f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099424992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.4099424992
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.3087503130
Short name T238
Test name
Test status
Simulation time 776209002 ps
CPU time 11.09 seconds
Started Jul 03 05:04:34 PM PDT 24
Finished Jul 03 05:04:45 PM PDT 24
Peak memory 219836 kb
Host smart-4c06456f-936b-4b78-9a28-52285144436a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087503130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.3087503130
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.582353968
Short name T425
Test name
Test status
Simulation time 1221115600 ps
CPU time 7.74 seconds
Started Jul 03 05:04:24 PM PDT 24
Finished Jul 03 05:04:34 PM PDT 24
Peak memory 225740 kb
Host smart-32706733-d86f-4676-b1a1-79c36f8cc491
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582353968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_di
gest.582353968
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.4162604753
Short name T842
Test name
Test status
Simulation time 1304933849 ps
CPU time 8.82 seconds
Started Jul 03 05:04:51 PM PDT 24
Finished Jul 03 05:05:02 PM PDT 24
Peak memory 218152 kb
Host smart-f690c0b7-086e-4275-852b-ed034d9874d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162604753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
4162604753
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.881510299
Short name T751
Test name
Test status
Simulation time 545580725 ps
CPU time 7.07 seconds
Started Jul 03 05:04:36 PM PDT 24
Finished Jul 03 05:04:43 PM PDT 24
Peak memory 218308 kb
Host smart-cd798346-8710-49ce-9099-0699a7e8fb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881510299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.881510299
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3006049344
Short name T493
Test name
Test status
Simulation time 40702620 ps
CPU time 1.03 seconds
Started Jul 03 05:04:41 PM PDT 24
Finished Jul 03 05:04:42 PM PDT 24
Peak memory 217668 kb
Host smart-b0e965ef-31e6-440f-b0c6-1cdc9f17ea4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006049344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3006049344
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3125662683
Short name T567
Test name
Test status
Simulation time 326560389 ps
CPU time 31.84 seconds
Started Jul 03 05:04:45 PM PDT 24
Finished Jul 03 05:05:18 PM PDT 24
Peak memory 250920 kb
Host smart-8d5fb335-cfd7-439c-9d71-17f2cd57b6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125662683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3125662683
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.2875824774
Short name T311
Test name
Test status
Simulation time 199059955 ps
CPU time 7.09 seconds
Started Jul 03 05:04:49 PM PDT 24
Finished Jul 03 05:04:56 PM PDT 24
Peak memory 250928 kb
Host smart-d5c4b9cf-6174-4e96-b8d3-14ad5f27b10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875824774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.2875824774
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.3235467830
Short name T232
Test name
Test status
Simulation time 11932598312 ps
CPU time 116.69 seconds
Started Jul 03 05:04:52 PM PDT 24
Finished Jul 03 05:06:49 PM PDT 24
Peak memory 259244 kb
Host smart-4df7ca17-0725-4181-9ec1-ca7235ffeb3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235467830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.3235467830
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.21738611
Short name T289
Test name
Test status
Simulation time 77103312 ps
CPU time 1.05 seconds
Started Jul 03 05:04:29 PM PDT 24
Finished Jul 03 05:04:31 PM PDT 24
Peak memory 217660 kb
Host smart-d812b272-0ac2-4fcd-b532-5e70f773b151
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21738611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctr
l_volatile_unlock_smoke.21738611
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.989212284
Short name T347
Test name
Test status
Simulation time 19801893 ps
CPU time 0.94 seconds
Started Jul 03 05:04:41 PM PDT 24
Finished Jul 03 05:04:43 PM PDT 24
Peak memory 208920 kb
Host smart-74ad905c-0bdc-4532-8399-dc4f423ed550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989212284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.989212284
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.697570778
Short name T685
Test name
Test status
Simulation time 836813244 ps
CPU time 20.27 seconds
Started Jul 03 05:04:26 PM PDT 24
Finished Jul 03 05:04:49 PM PDT 24
Peak memory 218140 kb
Host smart-38a2bd5b-905e-41d6-b5bc-f29b3b0ebcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697570778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.697570778
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.3214238444
Short name T510
Test name
Test status
Simulation time 2119597364 ps
CPU time 4.5 seconds
Started Jul 03 05:04:53 PM PDT 24
Finished Jul 03 05:04:58 PM PDT 24
Peak memory 217020 kb
Host smart-5a6e2aad-aa24-4348-9b35-d4fc10941da1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214238444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.3214238444
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.1475484782
Short name T235
Test name
Test status
Simulation time 148116524 ps
CPU time 2.91 seconds
Started Jul 03 05:04:49 PM PDT 24
Finished Jul 03 05:04:53 PM PDT 24
Peak memory 218140 kb
Host smart-27dde6b2-414f-4b03-b10a-6404435a52c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475484782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1475484782
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.1496914287
Short name T233
Test name
Test status
Simulation time 1014730150 ps
CPU time 10.62 seconds
Started Jul 03 05:04:44 PM PDT 24
Finished Jul 03 05:04:55 PM PDT 24
Peak memory 225984 kb
Host smart-2687615a-de96-41fb-8020-da15875c80c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496914287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.1496914287
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.748110597
Short name T509
Test name
Test status
Simulation time 1669067475 ps
CPU time 14.15 seconds
Started Jul 03 05:04:41 PM PDT 24
Finished Jul 03 05:04:55 PM PDT 24
Peak memory 218056 kb
Host smart-d39abe7f-6b0e-4b09-b44a-913602673c29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748110597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_di
gest.748110597
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1631221075
Short name T662
Test name
Test status
Simulation time 852391516 ps
CPU time 5.65 seconds
Started Jul 03 05:04:25 PM PDT 24
Finished Jul 03 05:04:33 PM PDT 24
Peak memory 218052 kb
Host smart-ae6901ad-ab77-4954-9188-ab955474b82d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631221075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1631221075
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.1085060600
Short name T65
Test name
Test status
Simulation time 38283332 ps
CPU time 3.18 seconds
Started Jul 03 05:04:31 PM PDT 24
Finished Jul 03 05:04:35 PM PDT 24
Peak memory 214820 kb
Host smart-67f7a27c-20c2-4957-9197-50d20cd5ef6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085060600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1085060600
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.497598447
Short name T330
Test name
Test status
Simulation time 1053656627 ps
CPU time 33.48 seconds
Started Jul 03 05:04:41 PM PDT 24
Finished Jul 03 05:05:15 PM PDT 24
Peak memory 250916 kb
Host smart-e4df0d05-b5b4-4689-86c5-0c3bdc6cfb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497598447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.497598447
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.1169972296
Short name T261
Test name
Test status
Simulation time 126998024 ps
CPU time 10.46 seconds
Started Jul 03 05:04:34 PM PDT 24
Finished Jul 03 05:04:44 PM PDT 24
Peak memory 250920 kb
Host smart-76c3aa30-3386-46b8-a2ac-f01feceb79c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169972296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1169972296
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.1843163478
Short name T807
Test name
Test status
Simulation time 5649436914 ps
CPU time 181.68 seconds
Started Jul 03 05:04:47 PM PDT 24
Finished Jul 03 05:07:49 PM PDT 24
Peak memory 274372 kb
Host smart-abd452ec-893a-40d2-87d5-66e5428a0b3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843163478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.1843163478
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.50034068
Short name T448
Test name
Test status
Simulation time 86438982 ps
CPU time 0.88 seconds
Started Jul 03 05:04:34 PM PDT 24
Finished Jul 03 05:04:35 PM PDT 24
Peak memory 211824 kb
Host smart-3377685b-3841-4e33-b5ac-8698becf36f0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50034068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctr
l_volatile_unlock_smoke.50034068
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.713637321
Short name T346
Test name
Test status
Simulation time 21332691 ps
CPU time 1.22 seconds
Started Jul 03 05:04:42 PM PDT 24
Finished Jul 03 05:04:44 PM PDT 24
Peak memory 209016 kb
Host smart-77cd09c7-fe23-4129-b1bc-6228bfde18ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713637321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.713637321
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.3834498514
Short name T49
Test name
Test status
Simulation time 2725072371 ps
CPU time 14.4 seconds
Started Jul 03 05:04:45 PM PDT 24
Finished Jul 03 05:05:00 PM PDT 24
Peak memory 226056 kb
Host smart-dbc777d2-7af6-4f1c-9e9a-3eee7b35b25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834498514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.3834498514
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1593730219
Short name T463
Test name
Test status
Simulation time 235425901 ps
CPU time 2.11 seconds
Started Jul 03 05:04:31 PM PDT 24
Finished Jul 03 05:04:34 PM PDT 24
Peak memory 217016 kb
Host smart-091ec9e5-9061-4d8f-8103-891e9d2f7032
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593730219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1593730219
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3185511287
Short name T640
Test name
Test status
Simulation time 100451235 ps
CPU time 1.54 seconds
Started Jul 03 05:04:38 PM PDT 24
Finished Jul 03 05:04:40 PM PDT 24
Peak memory 218172 kb
Host smart-f2300497-e0bf-4a38-9d99-49b387af130f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185511287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3185511287
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.122496510
Short name T674
Test name
Test status
Simulation time 515915457 ps
CPU time 10.62 seconds
Started Jul 03 05:04:53 PM PDT 24
Finished Jul 03 05:05:04 PM PDT 24
Peak memory 219356 kb
Host smart-81d2c529-77a3-4104-a9e9-2590d4f039e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122496510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.122496510
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.4221734309
Short name T858
Test name
Test status
Simulation time 318509352 ps
CPU time 12.49 seconds
Started Jul 03 05:04:41 PM PDT 24
Finished Jul 03 05:04:54 PM PDT 24
Peak memory 225864 kb
Host smart-bcd080ae-3894-4d07-90d6-2c94bb7b91e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221734309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.4221734309
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1256032024
Short name T244
Test name
Test status
Simulation time 423546300 ps
CPU time 9.9 seconds
Started Jul 03 05:04:49 PM PDT 24
Finished Jul 03 05:05:00 PM PDT 24
Peak memory 218172 kb
Host smart-488e9069-327d-4eab-8b9b-1ea3f47a530d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256032024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1256032024
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.583199108
Short name T456
Test name
Test status
Simulation time 274318229 ps
CPU time 6.78 seconds
Started Jul 03 05:04:45 PM PDT 24
Finished Jul 03 05:04:53 PM PDT 24
Peak memory 225972 kb
Host smart-7ba29b56-23fc-4e23-a5d3-be94ea4d327d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583199108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.583199108
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.768854581
Short name T615
Test name
Test status
Simulation time 186238833 ps
CPU time 3.05 seconds
Started Jul 03 05:04:49 PM PDT 24
Finished Jul 03 05:04:52 PM PDT 24
Peak memory 217652 kb
Host smart-e49ffd32-ac4b-4a7e-bc00-8240d3002f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768854581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.768854581
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.2400046799
Short name T314
Test name
Test status
Simulation time 367277252 ps
CPU time 16.57 seconds
Started Jul 03 05:04:41 PM PDT 24
Finished Jul 03 05:04:58 PM PDT 24
Peak memory 244904 kb
Host smart-3f3f82e2-5ddb-4de0-ab9f-3eda4ec98612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400046799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2400046799
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.2461054855
Short name T770
Test name
Test status
Simulation time 151391427 ps
CPU time 8.35 seconds
Started Jul 03 05:04:45 PM PDT 24
Finished Jul 03 05:04:54 PM PDT 24
Peak memory 250868 kb
Host smart-654528fd-f22e-4e3a-bf87-74bce55f2ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461054855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.2461054855
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3001557348
Short name T373
Test name
Test status
Simulation time 502351524 ps
CPU time 34.45 seconds
Started Jul 03 05:04:51 PM PDT 24
Finished Jul 03 05:05:26 PM PDT 24
Peak memory 248500 kb
Host smart-729c1b65-e525-4ec9-807c-fe638953066f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001557348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3001557348
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.2653132270
Short name T90
Test name
Test status
Simulation time 198427947278 ps
CPU time 968.97 seconds
Started Jul 03 05:04:35 PM PDT 24
Finished Jul 03 05:20:45 PM PDT 24
Peak memory 513252 kb
Host smart-9fd2e7f2-316c-4e40-be58-8bbbf453eef0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2653132270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.2653132270
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1933794372
Short name T405
Test name
Test status
Simulation time 31566459 ps
CPU time 0.76 seconds
Started Jul 03 05:04:42 PM PDT 24
Finished Jul 03 05:04:43 PM PDT 24
Peak memory 207048 kb
Host smart-f8bb2cd5-f372-4dfa-b5bf-bd8800849c66
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933794372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.1933794372
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1866021534
Short name T607
Test name
Test status
Simulation time 28489481 ps
CPU time 1.07 seconds
Started Jul 03 05:04:39 PM PDT 24
Finished Jul 03 05:04:40 PM PDT 24
Peak memory 208948 kb
Host smart-3657ec1b-a511-43ec-a4be-7cb5732b5adc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866021534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1866021534
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.4205567684
Short name T719
Test name
Test status
Simulation time 1276129244 ps
CPU time 15.63 seconds
Started Jul 03 05:04:26 PM PDT 24
Finished Jul 03 05:04:44 PM PDT 24
Peak memory 225656 kb
Host smart-2b05cd43-a630-4d6d-aaca-22c9290385ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205567684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.4205567684
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.2044663258
Short name T185
Test name
Test status
Simulation time 1580542570 ps
CPU time 5.46 seconds
Started Jul 03 05:04:48 PM PDT 24
Finished Jul 03 05:04:54 PM PDT 24
Peak memory 217320 kb
Host smart-0618f7a1-330b-4311-bc1e-bb55cdf6dcb3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044663258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.2044663258
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2257721264
Short name T268
Test name
Test status
Simulation time 67971676 ps
CPU time 2.33 seconds
Started Jul 03 05:04:53 PM PDT 24
Finished Jul 03 05:04:56 PM PDT 24
Peak memory 218180 kb
Host smart-332da714-7a5d-49fe-ab58-5af6b1dd950f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257721264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2257721264
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.2528864862
Short name T753
Test name
Test status
Simulation time 310114842 ps
CPU time 11.37 seconds
Started Jul 03 05:04:40 PM PDT 24
Finished Jul 03 05:04:52 PM PDT 24
Peak memory 225956 kb
Host smart-04a2fb69-b281-46f2-9fa4-a6151e35fe15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528864862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.2528864862
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2885131369
Short name T857
Test name
Test status
Simulation time 2985918344 ps
CPU time 15.43 seconds
Started Jul 03 05:04:44 PM PDT 24
Finished Jul 03 05:05:00 PM PDT 24
Peak memory 226012 kb
Host smart-e556d727-eb03-4906-ac69-8a680ba5ed16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885131369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.2885131369
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.4129520140
Short name T647
Test name
Test status
Simulation time 621411185 ps
CPU time 8.63 seconds
Started Jul 03 05:04:44 PM PDT 24
Finished Jul 03 05:04:53 PM PDT 24
Peak memory 225996 kb
Host smart-94e9f903-4f99-47db-8f7f-600f51386ff0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129520140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
4129520140
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.4133180000
Short name T379
Test name
Test status
Simulation time 259451815 ps
CPU time 7.46 seconds
Started Jul 03 05:04:46 PM PDT 24
Finished Jul 03 05:04:54 PM PDT 24
Peak memory 218240 kb
Host smart-d5ef5ecd-267e-4a15-9877-eab8a88a00ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133180000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.4133180000
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.1967902090
Short name T61
Test name
Test status
Simulation time 177126610 ps
CPU time 3.43 seconds
Started Jul 03 05:04:39 PM PDT 24
Finished Jul 03 05:04:43 PM PDT 24
Peak memory 214932 kb
Host smart-81962825-20f3-4fb0-b7a8-ca9ea3b2290d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967902090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.1967902090
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.707672851
Short name T41
Test name
Test status
Simulation time 303983167 ps
CPU time 27.03 seconds
Started Jul 03 05:04:47 PM PDT 24
Finished Jul 03 05:05:15 PM PDT 24
Peak memory 250900 kb
Host smart-745b8a70-a314-4a98-9d5c-1904c06cb88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707672851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.707672851
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.323088104
Short name T11
Test name
Test status
Simulation time 159091223 ps
CPU time 7.57 seconds
Started Jul 03 05:04:49 PM PDT 24
Finished Jul 03 05:04:57 PM PDT 24
Peak memory 250336 kb
Host smart-1f6d83f4-44ba-492e-a8d3-3f9e9bcd789d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323088104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.323088104
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.3268068068
Short name T114
Test name
Test status
Simulation time 35048277011 ps
CPU time 2466.75 seconds
Started Jul 03 05:04:40 PM PDT 24
Finished Jul 03 05:45:47 PM PDT 24
Peak memory 1552640 kb
Host smart-5f64dcfd-6d68-4eff-abce-d7c78669bb24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3268068068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.3268068068
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3040900585
Short name T675
Test name
Test status
Simulation time 37276057 ps
CPU time 0.99 seconds
Started Jul 03 05:04:48 PM PDT 24
Finished Jul 03 05:04:49 PM PDT 24
Peak memory 211760 kb
Host smart-e10eccc1-7ea0-4c07-9777-451aae4beaca
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040900585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3040900585
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.2426325396
Short name T654
Test name
Test status
Simulation time 15828445 ps
CPU time 1.08 seconds
Started Jul 03 05:04:41 PM PDT 24
Finished Jul 03 05:04:42 PM PDT 24
Peak memory 209052 kb
Host smart-b3dee88b-e7df-4def-bd30-d573ce0fea18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426325396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2426325396
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3079417153
Short name T376
Test name
Test status
Simulation time 721014412 ps
CPU time 11.18 seconds
Started Jul 03 05:04:49 PM PDT 24
Finished Jul 03 05:05:01 PM PDT 24
Peak memory 218180 kb
Host smart-dbd301da-451b-48cc-a449-c8fb04fe4e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079417153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3079417153
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.939366097
Short name T184
Test name
Test status
Simulation time 1252320111 ps
CPU time 7.82 seconds
Started Jul 03 05:04:46 PM PDT 24
Finished Jul 03 05:04:54 PM PDT 24
Peak memory 217660 kb
Host smart-e121b2ab-0ad7-4a88-9f35-847ec58a019a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939366097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.939366097
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.2419394633
Short name T383
Test name
Test status
Simulation time 229568407 ps
CPU time 3.18 seconds
Started Jul 03 05:04:51 PM PDT 24
Finished Jul 03 05:04:56 PM PDT 24
Peak memory 222256 kb
Host smart-e76ee377-7d2e-409c-845c-d6e0239a6663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419394633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.2419394633
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.1782848577
Short name T524
Test name
Test status
Simulation time 644825480 ps
CPU time 24.32 seconds
Started Jul 03 05:04:53 PM PDT 24
Finished Jul 03 05:05:18 PM PDT 24
Peak memory 225992 kb
Host smart-d32a369c-8aaa-4593-85e4-a8650aba4bae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782848577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1782848577
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1954606884
Short name T467
Test name
Test status
Simulation time 266679316 ps
CPU time 9.37 seconds
Started Jul 03 05:04:50 PM PDT 24
Finished Jul 03 05:05:00 PM PDT 24
Peak memory 225856 kb
Host smart-a3eb1066-e91e-47c2-8838-f240b7dd7e74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954606884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1954606884
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3084603548
Short name T264
Test name
Test status
Simulation time 635699153 ps
CPU time 12.52 seconds
Started Jul 03 05:04:49 PM PDT 24
Finished Jul 03 05:05:02 PM PDT 24
Peak memory 225960 kb
Host smart-bf2204a5-c610-4d87-ad49-14cb9fe4033d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084603548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3084603548
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.2056347386
Short name T159
Test name
Test status
Simulation time 3001558606 ps
CPU time 12.06 seconds
Started Jul 03 05:04:41 PM PDT 24
Finished Jul 03 05:04:54 PM PDT 24
Peak memory 218304 kb
Host smart-83d2d273-ca47-4787-952c-441ddf1e6dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056347386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.2056347386
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.973356891
Short name T501
Test name
Test status
Simulation time 109017325 ps
CPU time 1.77 seconds
Started Jul 03 05:04:49 PM PDT 24
Finished Jul 03 05:04:52 PM PDT 24
Peak memory 214136 kb
Host smart-2083b928-2c10-47ca-acee-bcac8b3fa2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973356891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.973356891
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.1067046664
Short name T686
Test name
Test status
Simulation time 233744589 ps
CPU time 22.63 seconds
Started Jul 03 05:04:48 PM PDT 24
Finished Jul 03 05:05:11 PM PDT 24
Peak memory 247456 kb
Host smart-ea510879-cc7f-49dd-b32f-d1ee5872053e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067046664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1067046664
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.413165230
Short name T168
Test name
Test status
Simulation time 328946085 ps
CPU time 9.61 seconds
Started Jul 03 05:04:37 PM PDT 24
Finished Jul 03 05:04:52 PM PDT 24
Peak memory 243296 kb
Host smart-3cdf0e08-1fd8-44f9-b380-3406c9f0af3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413165230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.413165230
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.2865795241
Short name T518
Test name
Test status
Simulation time 1531856811 ps
CPU time 46.66 seconds
Started Jul 03 05:04:42 PM PDT 24
Finished Jul 03 05:05:29 PM PDT 24
Peak memory 250436 kb
Host smart-5a047e08-46cf-48d9-a294-7c3110725de8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865795241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.2865795241
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.329599286
Short name T387
Test name
Test status
Simulation time 27139876 ps
CPU time 1.19 seconds
Started Jul 03 05:04:36 PM PDT 24
Finished Jul 03 05:04:38 PM PDT 24
Peak memory 213028 kb
Host smart-f88d610f-ba6e-40b3-bf5a-553758cfe332
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329599286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct
rl_volatile_unlock_smoke.329599286
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.1414343715
Short name T401
Test name
Test status
Simulation time 75774544 ps
CPU time 1.01 seconds
Started Jul 03 05:03:49 PM PDT 24
Finished Jul 03 05:03:50 PM PDT 24
Peak memory 208912 kb
Host smart-d90cc471-48ec-43e0-a63c-e536a06fdc50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414343715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1414343715
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.2909039373
Short name T73
Test name
Test status
Simulation time 18472617 ps
CPU time 0.94 seconds
Started Jul 03 05:03:55 PM PDT 24
Finished Jul 03 05:03:56 PM PDT 24
Peak memory 208860 kb
Host smart-d6e19369-69ab-4df1-b5fb-d89ae2adf495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909039373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.2909039373
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.598688519
Short name T767
Test name
Test status
Simulation time 1042718621 ps
CPU time 9.43 seconds
Started Jul 03 05:03:56 PM PDT 24
Finished Jul 03 05:04:06 PM PDT 24
Peak memory 218140 kb
Host smart-b1a57f9a-abfa-4e58-9771-2b9ed894561e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598688519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.598688519
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.4041296799
Short name T28
Test name
Test status
Simulation time 2373256026 ps
CPU time 8.61 seconds
Started Jul 03 05:03:30 PM PDT 24
Finished Jul 03 05:03:38 PM PDT 24
Peak memory 217624 kb
Host smart-34545136-3c52-45e6-b563-aa50453d9a07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041296799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.4041296799
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.3603638253
Short name T573
Test name
Test status
Simulation time 2153609017 ps
CPU time 58.23 seconds
Started Jul 03 05:03:44 PM PDT 24
Finished Jul 03 05:04:42 PM PDT 24
Peak memory 218180 kb
Host smart-2a8fa2d6-3172-4a02-b218-d101758f4f9a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603638253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.3603638253
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.4045902929
Short name T306
Test name
Test status
Simulation time 1218324190 ps
CPU time 12.39 seconds
Started Jul 03 05:03:47 PM PDT 24
Finished Jul 03 05:04:00 PM PDT 24
Peak memory 217632 kb
Host smart-e18aaa52-f56a-4a49-b732-71b293d77b82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045902929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.4
045902929
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1799709292
Short name T276
Test name
Test status
Simulation time 314493870 ps
CPU time 6 seconds
Started Jul 03 05:03:34 PM PDT 24
Finished Jul 03 05:03:40 PM PDT 24
Peak memory 218144 kb
Host smart-c3685eda-0457-4180-b727-fd93f4a3c0b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799709292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1799709292
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.202974630
Short name T704
Test name
Test status
Simulation time 1087136079 ps
CPU time 14.32 seconds
Started Jul 03 05:04:00 PM PDT 24
Finished Jul 03 05:04:15 PM PDT 24
Peak memory 217692 kb
Host smart-e369e9ba-f30c-4d6e-9ad2-e28d137387ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202974630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_regwen_during_op.202974630
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.259282167
Short name T69
Test name
Test status
Simulation time 318123769 ps
CPU time 7.95 seconds
Started Jul 03 05:03:56 PM PDT 24
Finished Jul 03 05:04:04 PM PDT 24
Peak memory 217668 kb
Host smart-a685c1e2-1408-4c97-be11-26036308783b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259282167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.259282167
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.727400678
Short name T604
Test name
Test status
Simulation time 10597388198 ps
CPU time 50.78 seconds
Started Jul 03 05:04:09 PM PDT 24
Finished Jul 03 05:05:01 PM PDT 24
Peak memory 280928 kb
Host smart-c527141a-7252-4a60-bb9f-53a7ece5bbfc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727400678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_state_failure.727400678
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.1092801189
Short name T370
Test name
Test status
Simulation time 369551422 ps
CPU time 9.53 seconds
Started Jul 03 05:03:42 PM PDT 24
Finished Jul 03 05:03:52 PM PDT 24
Peak memory 246036 kb
Host smart-2a7b3063-0cee-46d9-b61e-dc648c8dfa1d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092801189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.1092801189
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.940600101
Short name T822
Test name
Test status
Simulation time 56879215 ps
CPU time 2.52 seconds
Started Jul 03 05:03:54 PM PDT 24
Finished Jul 03 05:03:57 PM PDT 24
Peak memory 218176 kb
Host smart-469dd1c1-e407-46db-8b5d-f497a9cdfcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940600101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.940600101
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1155194413
Short name T837
Test name
Test status
Simulation time 1097538920 ps
CPU time 17.79 seconds
Started Jul 03 05:03:45 PM PDT 24
Finished Jul 03 05:04:03 PM PDT 24
Peak memory 214124 kb
Host smart-2b200e69-e806-4b49-a948-6aaf2c32e43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155194413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1155194413
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1661263095
Short name T60
Test name
Test status
Simulation time 120159362 ps
CPU time 21.72 seconds
Started Jul 03 05:04:06 PM PDT 24
Finished Jul 03 05:04:28 PM PDT 24
Peak memory 269004 kb
Host smart-a657a390-4ce3-4eb1-85ab-7bfbca044fc3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661263095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1661263095
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.1952366827
Short name T633
Test name
Test status
Simulation time 727970519 ps
CPU time 20.97 seconds
Started Jul 03 05:04:03 PM PDT 24
Finished Jul 03 05:04:25 PM PDT 24
Peak memory 225988 kb
Host smart-857d7992-17ae-4633-942d-c16bfddb051b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952366827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1952366827
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.1488422619
Short name T308
Test name
Test status
Simulation time 934640320 ps
CPU time 11.95 seconds
Started Jul 03 05:03:44 PM PDT 24
Finished Jul 03 05:03:56 PM PDT 24
Peak memory 225864 kb
Host smart-90f242d2-a971-4ec9-9253-9b72769e827b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488422619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.1488422619
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.3710420700
Short name T20
Test name
Test status
Simulation time 1230457654 ps
CPU time 10.31 seconds
Started Jul 03 05:03:44 PM PDT 24
Finished Jul 03 05:03:54 PM PDT 24
Peak memory 225260 kb
Host smart-78d96fdc-e878-444d-9c4a-695daedab36c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710420700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.3
710420700
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.2448195587
Short name T793
Test name
Test status
Simulation time 799222780 ps
CPU time 6.57 seconds
Started Jul 03 05:03:31 PM PDT 24
Finished Jul 03 05:03:38 PM PDT 24
Peak memory 218224 kb
Host smart-3bddd0be-ab9b-4866-b46a-fc3687098c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448195587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.2448195587
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.1540530294
Short name T532
Test name
Test status
Simulation time 37812058 ps
CPU time 2.73 seconds
Started Jul 03 05:03:38 PM PDT 24
Finished Jul 03 05:03:41 PM PDT 24
Peak memory 214776 kb
Host smart-f717808a-44d3-4968-9cb4-d82b97287363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540530294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1540530294
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.1142420650
Short name T593
Test name
Test status
Simulation time 503691959 ps
CPU time 20.75 seconds
Started Jul 03 05:04:00 PM PDT 24
Finished Jul 03 05:04:21 PM PDT 24
Peak memory 250936 kb
Host smart-986456e4-3564-4cd9-8833-15b485c1c30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142420650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1142420650
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.171386882
Short name T426
Test name
Test status
Simulation time 233976699 ps
CPU time 9.01 seconds
Started Jul 03 05:03:32 PM PDT 24
Finished Jul 03 05:03:41 PM PDT 24
Peak memory 250780 kb
Host smart-66ad2685-4350-4cbd-b2dd-0c5dcc7fb0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171386882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.171386882
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.2564835679
Short name T256
Test name
Test status
Simulation time 7505951872 ps
CPU time 151.68 seconds
Started Jul 03 05:03:48 PM PDT 24
Finished Jul 03 05:06:21 PM PDT 24
Peak memory 309892 kb
Host smart-2d6ced6f-c659-4793-9e45-7e16e8ad9bb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564835679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.2564835679
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.1331078059
Short name T95
Test name
Test status
Simulation time 192363772061 ps
CPU time 1213.32 seconds
Started Jul 03 05:04:04 PM PDT 24
Finished Jul 03 05:24:18 PM PDT 24
Peak memory 300208 kb
Host smart-99abb2bf-7a9d-448c-807b-5a6866a14820
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1331078059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.1331078059
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.3219738840
Short name T709
Test name
Test status
Simulation time 12343937 ps
CPU time 0.88 seconds
Started Jul 03 05:03:39 PM PDT 24
Finished Jul 03 05:03:40 PM PDT 24
Peak memory 211768 kb
Host smart-cfedf85e-e0bc-47b8-ac43-6019af829d54
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219738840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.3219738840
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.845184673
Short name T393
Test name
Test status
Simulation time 86595093 ps
CPU time 1 seconds
Started Jul 03 05:04:50 PM PDT 24
Finished Jul 03 05:04:51 PM PDT 24
Peak memory 208944 kb
Host smart-feae3fe9-f0d8-4471-8205-a44e6f04c63e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845184673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.845184673
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.706709819
Short name T631
Test name
Test status
Simulation time 807282414 ps
CPU time 17.9 seconds
Started Jul 03 05:04:55 PM PDT 24
Finished Jul 03 05:05:14 PM PDT 24
Peak memory 218152 kb
Host smart-e038408b-dfe1-42ed-a0d9-4cc0ad3b0942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706709819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.706709819
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.4116932041
Short name T727
Test name
Test status
Simulation time 8831779782 ps
CPU time 17.04 seconds
Started Jul 03 05:04:45 PM PDT 24
Finished Jul 03 05:05:03 PM PDT 24
Peak memory 217732 kb
Host smart-cb440f2c-dc8a-4252-921a-791c88259afd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116932041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.4116932041
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.2370449777
Short name T659
Test name
Test status
Simulation time 36172092 ps
CPU time 2.08 seconds
Started Jul 03 05:04:47 PM PDT 24
Finished Jul 03 05:04:50 PM PDT 24
Peak memory 222232 kb
Host smart-7bb4322b-29b5-4dee-952b-200e720e4f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370449777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.2370449777
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.3891685347
Short name T413
Test name
Test status
Simulation time 1689341348 ps
CPU time 18.01 seconds
Started Jul 03 05:04:47 PM PDT 24
Finished Jul 03 05:05:05 PM PDT 24
Peak memory 225952 kb
Host smart-2b6ff7dd-a55f-4852-b86e-ecd426def9df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891685347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3891685347
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.2363419223
Short name T392
Test name
Test status
Simulation time 389128258 ps
CPU time 16.19 seconds
Started Jul 03 05:04:46 PM PDT 24
Finished Jul 03 05:05:03 PM PDT 24
Peak memory 225960 kb
Host smart-b45488a9-5372-426c-a3c7-f8d8b8641093
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363419223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.2363419223
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1817634547
Short name T531
Test name
Test status
Simulation time 236390339 ps
CPU time 9.86 seconds
Started Jul 03 05:04:46 PM PDT 24
Finished Jul 03 05:04:57 PM PDT 24
Peak memory 218232 kb
Host smart-4757974f-b6cf-4167-898c-e1258300fc80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817634547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1817634547
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2098272296
Short name T465
Test name
Test status
Simulation time 29020662 ps
CPU time 1.43 seconds
Started Jul 03 05:04:41 PM PDT 24
Finished Jul 03 05:04:44 PM PDT 24
Peak memory 213756 kb
Host smart-c87f0adc-6fc8-4c98-a7ac-0d45a34b86c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098272296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2098272296
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.3040216923
Short name T288
Test name
Test status
Simulation time 1206304734 ps
CPU time 25.04 seconds
Started Jul 03 05:04:41 PM PDT 24
Finished Jul 03 05:05:07 PM PDT 24
Peak memory 250916 kb
Host smart-a4d2459d-a32c-4b0e-a7cd-18413c54f5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040216923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3040216923
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.1492061780
Short name T309
Test name
Test status
Simulation time 189849928 ps
CPU time 10.25 seconds
Started Jul 03 05:04:50 PM PDT 24
Finished Jul 03 05:05:01 PM PDT 24
Peak memory 250900 kb
Host smart-5378a7e4-21b8-4407-9750-3bb44b8b4f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492061780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.1492061780
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3385024307
Short name T105
Test name
Test status
Simulation time 91063505094 ps
CPU time 146.12 seconds
Started Jul 03 05:04:54 PM PDT 24
Finished Jul 03 05:07:21 PM PDT 24
Peak memory 267344 kb
Host smart-f542f88e-63b6-48ac-95ab-93c52ef86d99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385024307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3385024307
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.4123031102
Short name T63
Test name
Test status
Simulation time 23140260806 ps
CPU time 478.22 seconds
Started Jul 03 05:04:43 PM PDT 24
Finished Jul 03 05:12:42 PM PDT 24
Peak memory 283920 kb
Host smart-ff4a0541-2ce7-472e-9192-e078a08393b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4123031102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.4123031102
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.539696830
Short name T341
Test name
Test status
Simulation time 17782400 ps
CPU time 0.89 seconds
Started Jul 03 05:04:47 PM PDT 24
Finished Jul 03 05:04:48 PM PDT 24
Peak memory 211840 kb
Host smart-18ecb163-f989-4fd5-b018-66931b97657e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539696830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct
rl_volatile_unlock_smoke.539696830
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.2025154240
Short name T610
Test name
Test status
Simulation time 27112150 ps
CPU time 0.99 seconds
Started Jul 03 05:04:44 PM PDT 24
Finished Jul 03 05:04:46 PM PDT 24
Peak memory 209012 kb
Host smart-c5439e7f-6e58-4c2c-8c2a-2fcf7e1f9dbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025154240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.2025154240
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.3789814682
Short name T386
Test name
Test status
Simulation time 3864726511 ps
CPU time 16.02 seconds
Started Jul 03 05:04:58 PM PDT 24
Finished Jul 03 05:05:14 PM PDT 24
Peak memory 218840 kb
Host smart-9102bac5-b7d5-4987-8497-03caf0674f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789814682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3789814682
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.2602849096
Short name T589
Test name
Test status
Simulation time 298655981 ps
CPU time 1.72 seconds
Started Jul 03 05:04:53 PM PDT 24
Finished Jul 03 05:04:56 PM PDT 24
Peak memory 216992 kb
Host smart-595ad52e-6081-4f47-8cdb-96c5e8849689
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602849096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.2602849096
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.959333579
Short name T102
Test name
Test status
Simulation time 362078385 ps
CPU time 7.09 seconds
Started Jul 03 05:04:44 PM PDT 24
Finished Jul 03 05:04:52 PM PDT 24
Peak memory 218132 kb
Host smart-b132d525-1d80-4a8e-8caa-e2696f87e1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959333579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.959333579
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2535880041
Short name T291
Test name
Test status
Simulation time 2063548810 ps
CPU time 14.92 seconds
Started Jul 03 05:04:44 PM PDT 24
Finished Jul 03 05:05:00 PM PDT 24
Peak memory 225984 kb
Host smart-b3ce53de-f042-40da-aa21-5378573b9f34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535880041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2535880041
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3698526244
Short name T702
Test name
Test status
Simulation time 1594044354 ps
CPU time 15.08 seconds
Started Jul 03 05:04:39 PM PDT 24
Finished Jul 03 05:04:55 PM PDT 24
Peak memory 225936 kb
Host smart-76e801ca-c24f-4da0-a415-4eb243b373cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698526244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.3698526244
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3177545209
Short name T835
Test name
Test status
Simulation time 431195755 ps
CPU time 8.67 seconds
Started Jul 03 05:04:42 PM PDT 24
Finished Jul 03 05:04:51 PM PDT 24
Peak memory 226068 kb
Host smart-0dd24b67-d4d8-421d-b411-d04a7f730c1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177545209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
3177545209
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.5138743
Short name T442
Test name
Test status
Simulation time 2025297063 ps
CPU time 10.55 seconds
Started Jul 03 05:04:54 PM PDT 24
Finished Jul 03 05:05:05 PM PDT 24
Peak memory 218196 kb
Host smart-87ea76db-908f-44a0-8665-d7b45facd4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5138743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.5138743
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.1949470687
Short name T755
Test name
Test status
Simulation time 243720668 ps
CPU time 2.76 seconds
Started Jul 03 05:04:50 PM PDT 24
Finished Jul 03 05:04:56 PM PDT 24
Peak memory 214696 kb
Host smart-11d9d027-8d75-4335-a507-3b8300d576c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949470687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.1949470687
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.4083826735
Short name T489
Test name
Test status
Simulation time 320119544 ps
CPU time 28.59 seconds
Started Jul 03 05:04:41 PM PDT 24
Finished Jul 03 05:05:11 PM PDT 24
Peak memory 250916 kb
Host smart-badde695-a990-4424-b46d-4ee0a22ac671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083826735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.4083826735
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1469672136
Short name T739
Test name
Test status
Simulation time 2298235416 ps
CPU time 8.7 seconds
Started Jul 03 05:04:44 PM PDT 24
Finished Jul 03 05:04:53 PM PDT 24
Peak memory 251000 kb
Host smart-ca28e793-0733-4067-9632-38385d9003af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469672136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1469672136
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.662103253
Short name T602
Test name
Test status
Simulation time 6516582648 ps
CPU time 24.12 seconds
Started Jul 03 05:04:51 PM PDT 24
Finished Jul 03 05:05:16 PM PDT 24
Peak memory 242800 kb
Host smart-98af1234-1c94-4ddc-b1ee-89818c08b203
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662103253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.662103253
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1657459341
Short name T340
Test name
Test status
Simulation time 19465850 ps
CPU time 0.99 seconds
Started Jul 03 05:04:49 PM PDT 24
Finished Jul 03 05:04:51 PM PDT 24
Peak memory 211948 kb
Host smart-200db984-9db4-483f-b519-d3c040a45bd6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657459341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1657459341
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3720300136
Short name T440
Test name
Test status
Simulation time 121845234 ps
CPU time 1.12 seconds
Started Jul 03 05:04:50 PM PDT 24
Finished Jul 03 05:04:52 PM PDT 24
Peak memory 208880 kb
Host smart-1e8bf258-9322-4e23-9189-165166fbe961
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720300136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3720300136
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2554493469
Short name T362
Test name
Test status
Simulation time 481348603 ps
CPU time 19.77 seconds
Started Jul 03 05:04:56 PM PDT 24
Finished Jul 03 05:05:17 PM PDT 24
Peak memory 218048 kb
Host smart-5080df9a-2869-4fb0-b224-c5e7f75e4992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554493469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2554493469
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.4025677425
Short name T771
Test name
Test status
Simulation time 904558537 ps
CPU time 6.23 seconds
Started Jul 03 05:04:43 PM PDT 24
Finished Jul 03 05:04:50 PM PDT 24
Peak memory 217112 kb
Host smart-398e6fb1-22be-4b1c-b24c-cc1257cdf6bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025677425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.4025677425
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3485956928
Short name T269
Test name
Test status
Simulation time 75772899 ps
CPU time 3.92 seconds
Started Jul 03 05:05:02 PM PDT 24
Finished Jul 03 05:05:07 PM PDT 24
Peak memory 218132 kb
Host smart-8bf22925-2bf6-4fa5-8520-2dbef3da21b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485956928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3485956928
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.2828603382
Short name T773
Test name
Test status
Simulation time 1393705023 ps
CPU time 16.19 seconds
Started Jul 03 05:04:49 PM PDT 24
Finished Jul 03 05:05:06 PM PDT 24
Peak memory 225944 kb
Host smart-e22109b7-902b-4707-b7a8-cf72718f39b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828603382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.2828603382
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.477725110
Short name T817
Test name
Test status
Simulation time 1805479701 ps
CPU time 11.32 seconds
Started Jul 03 05:04:48 PM PDT 24
Finished Jul 03 05:04:59 PM PDT 24
Peak memory 225976 kb
Host smart-6a44e94e-e14a-4ee9-b3aa-02471edc47e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477725110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_di
gest.477725110
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.428063271
Short name T354
Test name
Test status
Simulation time 447822874 ps
CPU time 8.59 seconds
Started Jul 03 05:04:54 PM PDT 24
Finished Jul 03 05:05:03 PM PDT 24
Peak memory 224720 kb
Host smart-a22a118d-01ff-4d1c-b206-be735ac4d637
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428063271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.428063271
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.1853405554
Short name T622
Test name
Test status
Simulation time 244141843 ps
CPU time 7.82 seconds
Started Jul 03 05:04:49 PM PDT 24
Finished Jul 03 05:04:58 PM PDT 24
Peak memory 225820 kb
Host smart-df71bbc7-7d60-4897-a15a-5697e62e2dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853405554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.1853405554
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.1596177662
Short name T764
Test name
Test status
Simulation time 247456588 ps
CPU time 3.93 seconds
Started Jul 03 05:04:54 PM PDT 24
Finished Jul 03 05:04:58 PM PDT 24
Peak memory 214584 kb
Host smart-2238ab2f-429b-4728-841f-06cc4f4e7fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596177662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.1596177662
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.2780956829
Short name T431
Test name
Test status
Simulation time 563352699 ps
CPU time 24.17 seconds
Started Jul 03 05:04:38 PM PDT 24
Finished Jul 03 05:05:03 PM PDT 24
Peak memory 250876 kb
Host smart-c5a5f578-7993-4ea9-8bba-36bf643d7b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780956829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.2780956829
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.3790234508
Short name T648
Test name
Test status
Simulation time 216562084 ps
CPU time 6.33 seconds
Started Jul 03 05:04:56 PM PDT 24
Finished Jul 03 05:05:03 PM PDT 24
Peak memory 246572 kb
Host smart-b5ac0c2e-b116-489b-bfb3-08eb6c3d26c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790234508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3790234508
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.4269081990
Short name T466
Test name
Test status
Simulation time 10122454595 ps
CPU time 159.01 seconds
Started Jul 03 05:04:56 PM PDT 24
Finished Jul 03 05:07:36 PM PDT 24
Peak memory 276524 kb
Host smart-664b9aed-f8d4-477b-9655-59d267d7f25c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269081990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.4269081990
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.1376589748
Short name T42
Test name
Test status
Simulation time 97553350830 ps
CPU time 748.19 seconds
Started Jul 03 05:04:45 PM PDT 24
Finished Jul 03 05:17:14 PM PDT 24
Peak memory 300156 kb
Host smart-12824244-887d-4220-b3fb-5d1a8891eb4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1376589748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.1376589748
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.465709787
Short name T576
Test name
Test status
Simulation time 11841470 ps
CPU time 1.05 seconds
Started Jul 03 05:04:56 PM PDT 24
Finished Jul 03 05:04:58 PM PDT 24
Peak memory 211872 kb
Host smart-d5a133de-2f49-46ae-a09d-272aeb08ee85
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465709787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ct
rl_volatile_unlock_smoke.465709787
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.1011812090
Short name T108
Test name
Test status
Simulation time 647222794 ps
CPU time 8.91 seconds
Started Jul 03 05:04:55 PM PDT 24
Finished Jul 03 05:05:05 PM PDT 24
Peak memory 225980 kb
Host smart-1f46870b-1c47-4c7c-a887-07dfe7a4c561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011812090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1011812090
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1609693439
Short name T820
Test name
Test status
Simulation time 545705134 ps
CPU time 13.55 seconds
Started Jul 03 05:04:46 PM PDT 24
Finished Jul 03 05:05:00 PM PDT 24
Peak memory 217336 kb
Host smart-07412c70-730a-4d66-a0e4-7a5a35a72c84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609693439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1609693439
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2894761578
Short name T404
Test name
Test status
Simulation time 203715970 ps
CPU time 3.2 seconds
Started Jul 03 05:04:51 PM PDT 24
Finished Jul 03 05:05:00 PM PDT 24
Peak memory 222260 kb
Host smart-b757c544-95f5-445d-b637-a5e8864a02be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894761578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2894761578
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.2200935966
Short name T19
Test name
Test status
Simulation time 977229631 ps
CPU time 10.53 seconds
Started Jul 03 05:05:12 PM PDT 24
Finished Jul 03 05:05:23 PM PDT 24
Peak memory 226048 kb
Host smart-eac8a549-9263-4f6e-8a04-c0a775850583
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200935966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2200935966
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2893400169
Short name T253
Test name
Test status
Simulation time 420571269 ps
CPU time 9.47 seconds
Started Jul 03 05:04:43 PM PDT 24
Finished Jul 03 05:04:53 PM PDT 24
Peak memory 225924 kb
Host smart-02e3e9ad-11fe-4bc2-94c5-3a1725e0213f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893400169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2893400169
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3290555460
Short name T850
Test name
Test status
Simulation time 1258263114 ps
CPU time 10.35 seconds
Started Jul 03 05:05:12 PM PDT 24
Finished Jul 03 05:05:23 PM PDT 24
Peak memory 218192 kb
Host smart-4acd0501-02be-4acd-8dee-feefeb62609c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290555460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3290555460
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.113400994
Short name T437
Test name
Test status
Simulation time 610128259 ps
CPU time 12.99 seconds
Started Jul 03 05:04:52 PM PDT 24
Finished Jul 03 05:05:06 PM PDT 24
Peak memory 218272 kb
Host smart-b4c57b78-4419-4c5b-9b30-beb32e626161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113400994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.113400994
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.3213490487
Short name T470
Test name
Test status
Simulation time 45803747 ps
CPU time 1.71 seconds
Started Jul 03 05:04:37 PM PDT 24
Finished Jul 03 05:04:39 PM PDT 24
Peak memory 213876 kb
Host smart-710818b0-0e61-4ee9-a0ff-400446994ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213490487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3213490487
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.977968026
Short name T527
Test name
Test status
Simulation time 2232502447 ps
CPU time 35.91 seconds
Started Jul 03 05:04:49 PM PDT 24
Finished Jul 03 05:05:25 PM PDT 24
Peak memory 250868 kb
Host smart-6b098d60-eb79-414d-b5f2-320180231fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977968026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.977968026
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.2332935880
Short name T536
Test name
Test status
Simulation time 688493048 ps
CPU time 8.12 seconds
Started Jul 03 05:04:50 PM PDT 24
Finished Jul 03 05:05:03 PM PDT 24
Peak memory 242732 kb
Host smart-a017fe73-1991-4ffd-aee0-2d08f35da98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332935880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2332935880
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.2363332479
Short name T166
Test name
Test status
Simulation time 86274173393 ps
CPU time 116.34 seconds
Started Jul 03 05:04:53 PM PDT 24
Finished Jul 03 05:06:50 PM PDT 24
Peak memory 332928 kb
Host smart-72ff24f0-a356-4c43-a9d5-495a46a1b24d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363332479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.2363332479
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1671761505
Short name T434
Test name
Test status
Simulation time 27993335 ps
CPU time 0.95 seconds
Started Jul 03 05:04:36 PM PDT 24
Finished Jul 03 05:04:37 PM PDT 24
Peak memory 212928 kb
Host smart-505ad72c-5d36-4418-908c-d7f7671380d3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671761505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.1671761505
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.3419210807
Short name T816
Test name
Test status
Simulation time 35356865 ps
CPU time 1.05 seconds
Started Jul 03 05:05:09 PM PDT 24
Finished Jul 03 05:05:10 PM PDT 24
Peak memory 208884 kb
Host smart-7eb14afc-64da-4987-941f-9eda51d6d3d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419210807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3419210807
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.492106635
Short name T546
Test name
Test status
Simulation time 538173131 ps
CPU time 9.66 seconds
Started Jul 03 05:04:52 PM PDT 24
Finished Jul 03 05:05:02 PM PDT 24
Peak memory 218236 kb
Host smart-351e4448-4bc6-4753-bab2-48f561fc38b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492106635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.492106635
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.2801973792
Short name T741
Test name
Test status
Simulation time 126296041 ps
CPU time 2.15 seconds
Started Jul 03 05:04:59 PM PDT 24
Finished Jul 03 05:05:01 PM PDT 24
Peak memory 217076 kb
Host smart-26b650c7-9396-4313-9380-ef77cf911e95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801973792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.2801973792
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.637991216
Short name T673
Test name
Test status
Simulation time 164908279 ps
CPU time 2.68 seconds
Started Jul 03 05:04:48 PM PDT 24
Finished Jul 03 05:04:52 PM PDT 24
Peak memory 222212 kb
Host smart-303ea6b5-31c3-4d93-ad39-5d1acb074655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637991216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.637991216
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3894477591
Short name T406
Test name
Test status
Simulation time 1438901772 ps
CPU time 23.27 seconds
Started Jul 03 05:05:01 PM PDT 24
Finished Jul 03 05:05:25 PM PDT 24
Peak memory 225864 kb
Host smart-1c793529-cf05-4bb9-a907-50daeb56b65a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894477591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3894477591
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.672339097
Short name T175
Test name
Test status
Simulation time 3237931112 ps
CPU time 8 seconds
Started Jul 03 05:05:01 PM PDT 24
Finished Jul 03 05:05:09 PM PDT 24
Peak memory 218240 kb
Host smart-2e9f5cc8-7b79-40f6-8683-17a3dc8f9dd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672339097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.672339097
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.4263881030
Short name T56
Test name
Test status
Simulation time 458113529 ps
CPU time 10.72 seconds
Started Jul 03 05:04:55 PM PDT 24
Finished Jul 03 05:05:07 PM PDT 24
Peak memory 226040 kb
Host smart-a6d427bb-8127-4cdc-916c-00b67ebcebf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263881030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.4263881030
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.1457909775
Short name T72
Test name
Test status
Simulation time 15517097 ps
CPU time 0.91 seconds
Started Jul 03 05:04:52 PM PDT 24
Finished Jul 03 05:04:53 PM PDT 24
Peak memory 208980 kb
Host smart-f75c03e0-e49f-47b0-9040-5e8b8becc165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457909775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.1457909775
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1507533329
Short name T163
Test name
Test status
Simulation time 253237401 ps
CPU time 19.96 seconds
Started Jul 03 05:05:02 PM PDT 24
Finished Jul 03 05:05:23 PM PDT 24
Peak memory 250928 kb
Host smart-2eb718e3-1bd7-4ada-aaa6-156f80e507e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507533329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1507533329
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2484319208
Short name T445
Test name
Test status
Simulation time 80812958 ps
CPU time 6.01 seconds
Started Jul 03 05:04:57 PM PDT 24
Finished Jul 03 05:05:03 PM PDT 24
Peak memory 246764 kb
Host smart-070c3729-1a79-4367-bd6d-3754e2e87dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484319208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2484319208
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.2386010020
Short name T869
Test name
Test status
Simulation time 32465542769 ps
CPU time 292.55 seconds
Started Jul 03 05:05:11 PM PDT 24
Finished Jul 03 05:10:05 PM PDT 24
Peak memory 283668 kb
Host smart-b6172579-fcab-4f16-a4dc-59891051d1da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386010020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.2386010020
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1782907698
Short name T371
Test name
Test status
Simulation time 27859195 ps
CPU time 0.94 seconds
Started Jul 03 05:04:55 PM PDT 24
Finished Jul 03 05:04:57 PM PDT 24
Peak memory 212960 kb
Host smart-a46f434f-3a71-4d61-a0bd-63d9019d26f8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782907698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1782907698
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.3541505790
Short name T583
Test name
Test status
Simulation time 16813581 ps
CPU time 1.09 seconds
Started Jul 03 05:04:53 PM PDT 24
Finished Jul 03 05:04:55 PM PDT 24
Peak memory 208932 kb
Host smart-33424121-8b6d-42ea-85a9-321e4218ca20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541505790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3541505790
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.1887016572
Short name T453
Test name
Test status
Simulation time 921515923 ps
CPU time 17.61 seconds
Started Jul 03 05:05:09 PM PDT 24
Finished Jul 03 05:05:27 PM PDT 24
Peak memory 218012 kb
Host smart-005d41da-d2e5-49e2-bff1-dbf431f19379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887016572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.1887016572
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.1836144578
Short name T627
Test name
Test status
Simulation time 10959755299 ps
CPU time 14.49 seconds
Started Jul 03 05:05:12 PM PDT 24
Finished Jul 03 05:05:27 PM PDT 24
Peak memory 217716 kb
Host smart-55f26216-b5cc-443e-bc59-4531eda4cf3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836144578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.1836144578
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.303074623
Short name T449
Test name
Test status
Simulation time 1476658337 ps
CPU time 4.46 seconds
Started Jul 03 05:04:59 PM PDT 24
Finished Jul 03 05:05:04 PM PDT 24
Peak memory 218180 kb
Host smart-eb81f627-5776-44cc-8cb3-6dbe80a0095a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303074623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.303074623
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.1267052445
Short name T257
Test name
Test status
Simulation time 1204277979 ps
CPU time 14.56 seconds
Started Jul 03 05:04:57 PM PDT 24
Finished Jul 03 05:05:12 PM PDT 24
Peak memory 225936 kb
Host smart-ac5cde5b-d0a5-4298-ae7b-7318daa83f53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267052445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.1267052445
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.3080382868
Short name T243
Test name
Test status
Simulation time 496921002 ps
CPU time 11.39 seconds
Started Jul 03 05:05:15 PM PDT 24
Finished Jul 03 05:05:27 PM PDT 24
Peak memory 225940 kb
Host smart-f06b63fc-aba7-4ccd-9fca-f0324bec9aad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080382868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.3080382868
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.3198409093
Short name T412
Test name
Test status
Simulation time 376492786 ps
CPU time 13.39 seconds
Started Jul 03 05:05:02 PM PDT 24
Finished Jul 03 05:05:16 PM PDT 24
Peak memory 218028 kb
Host smart-413fb9ed-1833-4d60-9009-44efae732652
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198409093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
3198409093
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.4294344281
Short name T656
Test name
Test status
Simulation time 1757731545 ps
CPU time 13.68 seconds
Started Jul 03 05:05:17 PM PDT 24
Finished Jul 03 05:05:32 PM PDT 24
Peak memory 225988 kb
Host smart-0d9380e4-5836-4df7-8502-04a5e0355d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294344281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.4294344281
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.2343428401
Short name T523
Test name
Test status
Simulation time 340088179 ps
CPU time 2.57 seconds
Started Jul 03 05:04:51 PM PDT 24
Finished Jul 03 05:04:54 PM PDT 24
Peak memory 223524 kb
Host smart-47dfc153-6b6b-4b64-b801-6950b0667f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343428401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.2343428401
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.565156829
Short name T52
Test name
Test status
Simulation time 540946546 ps
CPU time 25.17 seconds
Started Jul 03 05:04:59 PM PDT 24
Finished Jul 03 05:05:24 PM PDT 24
Peak memory 246052 kb
Host smart-4b38cd78-fd9d-4cae-898c-c05d58a0f359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565156829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.565156829
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.1808327273
Short name T429
Test name
Test status
Simulation time 55788675 ps
CPU time 10.32 seconds
Started Jul 03 05:05:09 PM PDT 24
Finished Jul 03 05:05:20 PM PDT 24
Peak memory 250932 kb
Host smart-1da7a34a-4af4-405a-99df-baa5c2232b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808327273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1808327273
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2910067084
Short name T389
Test name
Test status
Simulation time 39015147558 ps
CPU time 340.23 seconds
Started Jul 03 05:05:10 PM PDT 24
Finished Jul 03 05:10:51 PM PDT 24
Peak memory 372772 kb
Host smart-f249f614-1671-4e23-bccd-5c89654eb10b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910067084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2910067084
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.792074770
Short name T161
Test name
Test status
Simulation time 49732911018 ps
CPU time 1199.58 seconds
Started Jul 03 05:05:17 PM PDT 24
Finished Jul 03 05:25:18 PM PDT 24
Peak memory 496872 kb
Host smart-05052a3a-4db6-4765-974c-1fc2a1cadb96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=792074770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.792074770
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.836787610
Short name T533
Test name
Test status
Simulation time 19062139 ps
CPU time 1.23 seconds
Started Jul 03 05:05:10 PM PDT 24
Finished Jul 03 05:05:12 PM PDT 24
Peak memory 212876 kb
Host smart-49e2e5f5-673a-4317-ad12-3d8bb10acba5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836787610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ct
rl_volatile_unlock_smoke.836787610
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3357384429
Short name T286
Test name
Test status
Simulation time 16853712 ps
CPU time 0.92 seconds
Started Jul 03 05:05:02 PM PDT 24
Finished Jul 03 05:05:03 PM PDT 24
Peak memory 208908 kb
Host smart-1f592715-59aa-46a5-b5fe-8a1257dd26e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357384429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3357384429
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.4165825583
Short name T774
Test name
Test status
Simulation time 1073567706 ps
CPU time 8.74 seconds
Started Jul 03 05:05:09 PM PDT 24
Finished Jul 03 05:05:18 PM PDT 24
Peak memory 218156 kb
Host smart-b445653f-4341-410a-a14a-7440ecba978b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165825583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.4165825583
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.2541006380
Short name T176
Test name
Test status
Simulation time 227007400 ps
CPU time 6.6 seconds
Started Jul 03 05:05:11 PM PDT 24
Finished Jul 03 05:05:17 PM PDT 24
Peak memory 217664 kb
Host smart-ad077c6a-d3d7-49b8-bb01-351099730da9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541006380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.2541006380
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.2303379079
Short name T327
Test name
Test status
Simulation time 51309681 ps
CPU time 2.89 seconds
Started Jul 03 05:05:05 PM PDT 24
Finished Jul 03 05:05:08 PM PDT 24
Peak memory 218168 kb
Host smart-b1e4648e-64ea-47ae-8e20-7792b7052c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303379079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2303379079
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1509706783
Short name T722
Test name
Test status
Simulation time 935488576 ps
CPU time 9.63 seconds
Started Jul 03 05:05:02 PM PDT 24
Finished Jul 03 05:05:12 PM PDT 24
Peak memory 218772 kb
Host smart-6dc18c21-8c43-4579-aea6-701d14d5d576
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509706783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1509706783
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.2158530464
Short name T754
Test name
Test status
Simulation time 5000376323 ps
CPU time 19.32 seconds
Started Jul 03 05:05:08 PM PDT 24
Finished Jul 03 05:05:27 PM PDT 24
Peak memory 226040 kb
Host smart-a79c64e6-be2c-4e56-a80c-75a9c13fd679
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158530464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.2158530464
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.188890454
Short name T399
Test name
Test status
Simulation time 3286266655 ps
CPU time 8.77 seconds
Started Jul 03 05:05:04 PM PDT 24
Finished Jul 03 05:05:13 PM PDT 24
Peak memory 225884 kb
Host smart-c1d4dc13-5d13-4507-970c-40aa24da878f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188890454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.188890454
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.908413730
Short name T220
Test name
Test status
Simulation time 1097778877 ps
CPU time 10.8 seconds
Started Jul 03 05:05:07 PM PDT 24
Finished Jul 03 05:05:18 PM PDT 24
Peak memory 225956 kb
Host smart-a538771a-3454-4906-9adc-d85fe63f973d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908413730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.908413730
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.3839525453
Short name T84
Test name
Test status
Simulation time 127621612 ps
CPU time 2.61 seconds
Started Jul 03 05:04:54 PM PDT 24
Finished Jul 03 05:04:57 PM PDT 24
Peak memory 214452 kb
Host smart-edfd1880-7255-4e33-a5fe-f83b166abd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839525453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.3839525453
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3071880422
Short name T307
Test name
Test status
Simulation time 325126538 ps
CPU time 19.4 seconds
Started Jul 03 05:05:10 PM PDT 24
Finished Jul 03 05:05:30 PM PDT 24
Peak memory 250920 kb
Host smart-7ce73e81-9f3e-4ef3-9e02-6ef6f3f34079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071880422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3071880422
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.4041809909
Short name T812
Test name
Test status
Simulation time 227212412 ps
CPU time 2.5 seconds
Started Jul 03 05:04:54 PM PDT 24
Finished Jul 03 05:04:57 PM PDT 24
Peak memory 218152 kb
Host smart-a2b6921e-af53-4702-94fa-0230c8f9e0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041809909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.4041809909
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.376026293
Short name T181
Test name
Test status
Simulation time 1420373516 ps
CPU time 19.89 seconds
Started Jul 03 05:05:00 PM PDT 24
Finished Jul 03 05:05:20 PM PDT 24
Peak memory 243704 kb
Host smart-d8e0ab70-6a71-4963-a38d-c5ba23dd89c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376026293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.376026293
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.4069821914
Short name T66
Test name
Test status
Simulation time 148917790456 ps
CPU time 1005.25 seconds
Started Jul 03 05:05:02 PM PDT 24
Finished Jul 03 05:21:48 PM PDT 24
Peak memory 496656 kb
Host smart-987a23d4-ae49-44b3-8a8b-78b61741df7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4069821914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.4069821914
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.380967942
Short name T507
Test name
Test status
Simulation time 53072644 ps
CPU time 0.99 seconds
Started Jul 03 05:05:16 PM PDT 24
Finished Jul 03 05:05:19 PM PDT 24
Peak memory 213076 kb
Host smart-a05fb202-4df2-4718-b824-bd4e67bda746
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380967942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ct
rl_volatile_unlock_smoke.380967942
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.167798345
Short name T832
Test name
Test status
Simulation time 60149791 ps
CPU time 1.09 seconds
Started Jul 03 05:05:19 PM PDT 24
Finished Jul 03 05:05:22 PM PDT 24
Peak memory 208932 kb
Host smart-6e048942-52d1-42d2-bc46-1ecf590daf32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167798345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.167798345
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.834042398
Short name T302
Test name
Test status
Simulation time 558411542 ps
CPU time 12 seconds
Started Jul 03 05:04:54 PM PDT 24
Finished Jul 03 05:05:06 PM PDT 24
Peak memory 218132 kb
Host smart-a1c6285b-21d0-4d4b-888a-d58be412ca0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834042398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.834042398
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.286562337
Short name T182
Test name
Test status
Simulation time 522907059 ps
CPU time 11.72 seconds
Started Jul 03 05:04:56 PM PDT 24
Finished Jul 03 05:05:09 PM PDT 24
Peak memory 217332 kb
Host smart-66cee46d-9a34-4548-8bba-7c6f275a379e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286562337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.286562337
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.1863738332
Short name T263
Test name
Test status
Simulation time 52761776 ps
CPU time 1.69 seconds
Started Jul 03 05:04:54 PM PDT 24
Finished Jul 03 05:04:56 PM PDT 24
Peak memory 221960 kb
Host smart-c434868a-711e-4f45-b1cb-bfa5ab9d81e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863738332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.1863738332
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.1605017019
Short name T239
Test name
Test status
Simulation time 8403855569 ps
CPU time 14.81 seconds
Started Jul 03 05:04:57 PM PDT 24
Finished Jul 03 05:05:12 PM PDT 24
Peak memory 226040 kb
Host smart-25b862ef-3eed-4b0a-821e-bd7ac5019fac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605017019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.1605017019
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.798245684
Short name T671
Test name
Test status
Simulation time 2119490310 ps
CPU time 15.67 seconds
Started Jul 03 05:05:14 PM PDT 24
Finished Jul 03 05:05:30 PM PDT 24
Peak memory 225960 kb
Host smart-175ab694-0e97-4cf2-870e-cd27d7b1090b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798245684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_di
gest.798245684
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2438410698
Short name T791
Test name
Test status
Simulation time 742008000 ps
CPU time 9.73 seconds
Started Jul 03 05:05:11 PM PDT 24
Finished Jul 03 05:05:21 PM PDT 24
Peak memory 218084 kb
Host smart-a496d77a-ad8f-429e-9da6-787476a3bfc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438410698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2438410698
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.2502292345
Short name T700
Test name
Test status
Simulation time 355822977 ps
CPU time 9.01 seconds
Started Jul 03 05:04:58 PM PDT 24
Finished Jul 03 05:05:07 PM PDT 24
Peak memory 225108 kb
Host smart-e0533772-f0d7-4308-8fdd-ddf96dfdd386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502292345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.2502292345
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.1515577035
Short name T290
Test name
Test status
Simulation time 158563968 ps
CPU time 3.04 seconds
Started Jul 03 05:04:55 PM PDT 24
Finished Jul 03 05:04:59 PM PDT 24
Peak memory 217708 kb
Host smart-bd874f93-23aa-434a-b2dd-ce7bd521815d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515577035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.1515577035
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.934090381
Short name T605
Test name
Test status
Simulation time 280045272 ps
CPU time 21.77 seconds
Started Jul 03 05:05:01 PM PDT 24
Finished Jul 03 05:05:23 PM PDT 24
Peak memory 250980 kb
Host smart-41b3d3cc-31b8-44c5-9a84-a0273c96deaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934090381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.934090381
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.2662975673
Short name T787
Test name
Test status
Simulation time 286968831 ps
CPU time 4.18 seconds
Started Jul 03 05:04:52 PM PDT 24
Finished Jul 03 05:04:57 PM PDT 24
Peak memory 226352 kb
Host smart-c16b064b-2448-4e7f-b596-5f1cf299c500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662975673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.2662975673
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.295787387
Short name T418
Test name
Test status
Simulation time 6283065463 ps
CPU time 57.51 seconds
Started Jul 03 05:05:14 PM PDT 24
Finished Jul 03 05:06:12 PM PDT 24
Peak memory 244232 kb
Host smart-70a362ca-9a29-4dc5-bd6d-57fee46dda8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295787387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.295787387
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.574342775
Short name T498
Test name
Test status
Simulation time 28646428 ps
CPU time 0.96 seconds
Started Jul 03 05:04:55 PM PDT 24
Finished Jul 03 05:04:56 PM PDT 24
Peak memory 212936 kb
Host smart-b56b4b6f-f1a6-4e2b-b77f-eb883184e157
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574342775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ct
rl_volatile_unlock_smoke.574342775
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3229245280
Short name T782
Test name
Test status
Simulation time 78249243 ps
CPU time 0.98 seconds
Started Jul 03 05:05:14 PM PDT 24
Finished Jul 03 05:05:16 PM PDT 24
Peak memory 208964 kb
Host smart-2b79cb0e-f17a-4814-ad16-b3d3d8436979
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229245280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3229245280
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2686312424
Short name T443
Test name
Test status
Simulation time 462142820 ps
CPU time 13.17 seconds
Started Jul 03 05:05:03 PM PDT 24
Finished Jul 03 05:05:16 PM PDT 24
Peak memory 225988 kb
Host smart-c524223b-e872-4df9-a90a-550bb0eae9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686312424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2686312424
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.2468528462
Short name T701
Test name
Test status
Simulation time 551073745 ps
CPU time 4.34 seconds
Started Jul 03 05:05:14 PM PDT 24
Finished Jul 03 05:05:18 PM PDT 24
Peak memory 217120 kb
Host smart-5493a414-0422-4114-a757-37bf08d44fbc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468528462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.2468528462
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3335800239
Short name T479
Test name
Test status
Simulation time 737329492 ps
CPU time 3.24 seconds
Started Jul 03 05:05:11 PM PDT 24
Finished Jul 03 05:05:15 PM PDT 24
Peak memory 222236 kb
Host smart-60b6ccc8-817d-4dea-8168-be6878cef753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335800239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3335800239
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.3339255782
Short name T839
Test name
Test status
Simulation time 1189634615 ps
CPU time 23.04 seconds
Started Jul 03 05:05:16 PM PDT 24
Finished Jul 03 05:05:41 PM PDT 24
Peak memory 225964 kb
Host smart-1c313abf-fdc2-4575-bf75-b12ebad1bd45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339255782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.3339255782
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1228144434
Short name T171
Test name
Test status
Simulation time 312807136 ps
CPU time 9.67 seconds
Started Jul 03 05:04:59 PM PDT 24
Finished Jul 03 05:05:09 PM PDT 24
Peak memory 225972 kb
Host smart-aa822094-3c5b-48d9-a64a-35898f8e09a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228144434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.1228144434
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.2974331865
Short name T703
Test name
Test status
Simulation time 947940881 ps
CPU time 15.42 seconds
Started Jul 03 05:05:11 PM PDT 24
Finished Jul 03 05:05:27 PM PDT 24
Peak memory 225988 kb
Host smart-b9e46057-9e1b-4f1e-b82e-6ed538d5806c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974331865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
2974331865
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2993953085
Short name T292
Test name
Test status
Simulation time 1468290734 ps
CPU time 13.96 seconds
Started Jul 03 05:05:12 PM PDT 24
Finished Jul 03 05:05:26 PM PDT 24
Peak memory 218212 kb
Host smart-4da601f3-220b-4e52-8732-ff748eb3d6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993953085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2993953085
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.1303485704
Short name T88
Test name
Test status
Simulation time 54060596 ps
CPU time 2.17 seconds
Started Jul 03 05:04:56 PM PDT 24
Finished Jul 03 05:04:59 PM PDT 24
Peak memory 214048 kb
Host smart-322bef06-745e-4329-b4aa-f6db1a324751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303485704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.1303485704
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.353536031
Short name T504
Test name
Test status
Simulation time 79473336 ps
CPU time 6.54 seconds
Started Jul 03 05:05:10 PM PDT 24
Finished Jul 03 05:05:17 PM PDT 24
Peak memory 244484 kb
Host smart-11d3bd32-646a-48a2-b04e-369b0ca399a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353536031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.353536031
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.2847761415
Short name T82
Test name
Test status
Simulation time 931905466 ps
CPU time 17.38 seconds
Started Jul 03 05:04:58 PM PDT 24
Finished Jul 03 05:05:16 PM PDT 24
Peak memory 225956 kb
Host smart-0ac945ee-5194-4656-bd3d-0371441dc827
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847761415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.2847761415
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.741122401
Short name T844
Test name
Test status
Simulation time 11020022 ps
CPU time 1.01 seconds
Started Jul 03 05:05:11 PM PDT 24
Finished Jul 03 05:05:13 PM PDT 24
Peak memory 211676 kb
Host smart-870aa5ed-b2ff-412c-bb7c-1cf23dfdd619
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741122401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.741122401
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1718389709
Short name T868
Test name
Test status
Simulation time 51053689 ps
CPU time 0.94 seconds
Started Jul 03 05:05:11 PM PDT 24
Finished Jul 03 05:05:13 PM PDT 24
Peak memory 208772 kb
Host smart-a245e4ec-64d3-4139-9122-86768df12094
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718389709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1718389709
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.524553947
Short name T529
Test name
Test status
Simulation time 405452028 ps
CPU time 10.29 seconds
Started Jul 03 05:05:15 PM PDT 24
Finished Jul 03 05:05:26 PM PDT 24
Peak memory 218236 kb
Host smart-e2f1e022-c259-4928-b137-0dba22aae9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524553947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.524553947
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3130664026
Short name T9
Test name
Test status
Simulation time 156272503 ps
CPU time 4.99 seconds
Started Jul 03 05:05:20 PM PDT 24
Finished Jul 03 05:05:28 PM PDT 24
Peak memory 217048 kb
Host smart-badbc782-108e-47df-b43d-0fbeebc8163d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130664026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3130664026
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.2957026670
Short name T840
Test name
Test status
Simulation time 104882712 ps
CPU time 2.83 seconds
Started Jul 03 05:05:05 PM PDT 24
Finished Jul 03 05:05:08 PM PDT 24
Peak memory 218112 kb
Host smart-a3fd192e-1cb5-489c-a5ea-1ddfca466927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957026670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.2957026670
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.2466837098
Short name T818
Test name
Test status
Simulation time 2217933342 ps
CPU time 17.68 seconds
Started Jul 03 05:05:14 PM PDT 24
Finished Jul 03 05:05:33 PM PDT 24
Peak memory 226060 kb
Host smart-4d890c17-b8e7-418f-8da4-4e4d475c9412
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466837098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.2466837098
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3419269737
Short name T635
Test name
Test status
Simulation time 1601039843 ps
CPU time 13 seconds
Started Jul 03 05:05:18 PM PDT 24
Finished Jul 03 05:05:33 PM PDT 24
Peak memory 225940 kb
Host smart-1cb00ac5-6e76-4e25-be91-9b0d093433aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419269737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3419269737
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3014371737
Short name T339
Test name
Test status
Simulation time 409506472 ps
CPU time 14.18 seconds
Started Jul 03 05:05:18 PM PDT 24
Finished Jul 03 05:05:34 PM PDT 24
Peak memory 225984 kb
Host smart-4499df10-17d2-41fc-9759-d2959f134d92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014371737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
3014371737
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.2825259617
Short name T520
Test name
Test status
Simulation time 80608406 ps
CPU time 3.06 seconds
Started Jul 03 05:05:05 PM PDT 24
Finished Jul 03 05:05:09 PM PDT 24
Peak memory 217632 kb
Host smart-a56ef87b-a1bb-4280-8764-094fa450daa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825259617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.2825259617
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.1287135514
Short name T299
Test name
Test status
Simulation time 2113076218 ps
CPU time 24.47 seconds
Started Jul 03 05:05:08 PM PDT 24
Finished Jul 03 05:05:33 PM PDT 24
Peak memory 251016 kb
Host smart-f40ab160-3406-4b04-b1cb-4aa67897d7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287135514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.1287135514
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.2944755723
Short name T747
Test name
Test status
Simulation time 186871895 ps
CPU time 9.43 seconds
Started Jul 03 05:04:56 PM PDT 24
Finished Jul 03 05:05:06 PM PDT 24
Peak memory 250908 kb
Host smart-ffe3d05d-9bb9-42a6-82f1-24458040f0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944755723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.2944755723
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.3658258726
Short name T721
Test name
Test status
Simulation time 30140508676 ps
CPU time 209.36 seconds
Started Jul 03 05:05:12 PM PDT 24
Finished Jul 03 05:08:42 PM PDT 24
Peak memory 278736 kb
Host smart-6720c25e-94f2-45c1-a6b3-47640b100fdf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658258726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.3658258726
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.4204555015
Short name T744
Test name
Test status
Simulation time 34606788 ps
CPU time 0.89 seconds
Started Jul 03 05:05:09 PM PDT 24
Finished Jul 03 05:05:11 PM PDT 24
Peak memory 211660 kb
Host smart-0a7a047c-146b-4846-a623-f3196f00f5ec
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204555015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.4204555015
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.1747930071
Short name T650
Test name
Test status
Simulation time 19733014 ps
CPU time 1.25 seconds
Started Jul 03 05:04:03 PM PDT 24
Finished Jul 03 05:04:05 PM PDT 24
Peak memory 208944 kb
Host smart-2d32172d-b221-4909-b8c7-c8f58dbada06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747930071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.1747930071
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.16489828
Short name T713
Test name
Test status
Simulation time 848393150 ps
CPU time 17.99 seconds
Started Jul 03 05:03:55 PM PDT 24
Finished Jul 03 05:04:13 PM PDT 24
Peak memory 218168 kb
Host smart-39d4df05-dd37-4be6-8b19-5ecaaea9f03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16489828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.16489828
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.2573100598
Short name T641
Test name
Test status
Simulation time 402825511 ps
CPU time 9.81 seconds
Started Jul 03 05:03:39 PM PDT 24
Finished Jul 03 05:03:52 PM PDT 24
Peak memory 217316 kb
Host smart-d9023747-eab2-4c89-8f82-254ded33d01f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573100598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.2573100598
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1424424638
Short name T44
Test name
Test status
Simulation time 10980061294 ps
CPU time 73.65 seconds
Started Jul 03 05:03:53 PM PDT 24
Finished Jul 03 05:05:07 PM PDT 24
Peak memory 218892 kb
Host smart-3aaa06fa-bf83-4751-b1b5-8ad0930fae2c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424424638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1424424638
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.105668725
Short name T786
Test name
Test status
Simulation time 149122983 ps
CPU time 2.68 seconds
Started Jul 03 05:04:06 PM PDT 24
Finished Jul 03 05:04:09 PM PDT 24
Peak memory 217320 kb
Host smart-3054201b-ae9d-4655-8199-534b7ec863ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105668725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.105668725
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.3597640412
Short name T779
Test name
Test status
Simulation time 1987605878 ps
CPU time 14.42 seconds
Started Jul 03 05:03:57 PM PDT 24
Finished Jul 03 05:04:11 PM PDT 24
Peak memory 218216 kb
Host smart-120d2216-f949-499b-a57a-a85a4c13dc42
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597640412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.3597640412
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3938146625
Short name T558
Test name
Test status
Simulation time 1488580786 ps
CPU time 9.69 seconds
Started Jul 03 05:04:02 PM PDT 24
Finished Jul 03 05:04:12 PM PDT 24
Peak memory 217636 kb
Host smart-6089f439-5ade-49c5-a6a8-fd0f7779061f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938146625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3938146625
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.643090359
Short name T768
Test name
Test status
Simulation time 1798113622 ps
CPU time 4.98 seconds
Started Jul 03 05:03:54 PM PDT 24
Finished Jul 03 05:03:59 PM PDT 24
Peak memory 217656 kb
Host smart-306526dd-c803-4603-ba7b-b25db850f0b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643090359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.643090359
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1375576092
Short name T375
Test name
Test status
Simulation time 898416005 ps
CPU time 24.31 seconds
Started Jul 03 05:04:01 PM PDT 24
Finished Jul 03 05:04:26 PM PDT 24
Peak memory 250896 kb
Host smart-4a1d4c12-144e-4f04-9849-59b57b363f7c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375576092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.1375576092
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.4129452339
Short name T831
Test name
Test status
Simulation time 1087802456 ps
CPU time 20.53 seconds
Started Jul 03 05:03:48 PM PDT 24
Finished Jul 03 05:04:09 PM PDT 24
Peak memory 248660 kb
Host smart-ed89938e-3f2f-43c0-8269-84e9a53082c2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129452339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.4129452339
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3660398761
Short name T511
Test name
Test status
Simulation time 75863801 ps
CPU time 1.44 seconds
Started Jul 03 05:03:31 PM PDT 24
Finished Jul 03 05:03:33 PM PDT 24
Peak memory 221576 kb
Host smart-7586278f-72cd-4973-8907-118f2d662529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660398761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3660398761
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.3956954364
Short name T357
Test name
Test status
Simulation time 276688841 ps
CPU time 7.69 seconds
Started Jul 03 05:03:30 PM PDT 24
Finished Jul 03 05:03:38 PM PDT 24
Peak memory 217652 kb
Host smart-672dc3b0-8b2f-4927-ae53-17a6d134f1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956954364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.3956954364
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3994891944
Short name T59
Test name
Test status
Simulation time 1632749707 ps
CPU time 23.07 seconds
Started Jul 03 05:03:33 PM PDT 24
Finished Jul 03 05:03:56 PM PDT 24
Peak memory 281628 kb
Host smart-e80ee084-0767-42d4-a64d-6ad3763f6ace
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994891944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3994891944
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.183071035
Short name T164
Test name
Test status
Simulation time 271498563 ps
CPU time 11.29 seconds
Started Jul 03 05:04:16 PM PDT 24
Finished Jul 03 05:04:28 PM PDT 24
Peak memory 225952 kb
Host smart-e0b5ab70-1d5c-4319-9785-57256a1dfa4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183071035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.183071035
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.4253486061
Short name T551
Test name
Test status
Simulation time 363827363 ps
CPU time 10.14 seconds
Started Jul 03 05:03:59 PM PDT 24
Finished Jul 03 05:04:10 PM PDT 24
Peak memory 225984 kb
Host smart-de40335e-5617-42e8-84df-9456f0eca145
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253486061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.4253486061
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.3935029669
Short name T625
Test name
Test status
Simulation time 1365791828 ps
CPU time 8.68 seconds
Started Jul 03 05:03:46 PM PDT 24
Finished Jul 03 05:03:55 PM PDT 24
Peak memory 218132 kb
Host smart-a7af0661-6a96-4c0f-a698-cb77df075008
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935029669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.3
935029669
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.418991076
Short name T679
Test name
Test status
Simulation time 241710529 ps
CPU time 9.98 seconds
Started Jul 03 05:03:34 PM PDT 24
Finished Jul 03 05:03:45 PM PDT 24
Peak memory 218220 kb
Host smart-147f5a3d-d836-452d-81c1-71c0de5c94e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418991076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.418991076
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.27771886
Short name T85
Test name
Test status
Simulation time 35731428 ps
CPU time 2.48 seconds
Started Jul 03 05:04:00 PM PDT 24
Finished Jul 03 05:04:03 PM PDT 24
Peak memory 214396 kb
Host smart-44848033-e221-40e1-8e4d-d66b7e7b7522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27771886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.27771886
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1999257880
Short name T809
Test name
Test status
Simulation time 877617427 ps
CPU time 18.19 seconds
Started Jul 03 05:03:59 PM PDT 24
Finished Jul 03 05:04:18 PM PDT 24
Peak memory 250848 kb
Host smart-3e7feaf9-dcd9-45fe-b221-a90793bdefdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999257880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1999257880
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.407847486
Short name T491
Test name
Test status
Simulation time 86096622 ps
CPU time 8.83 seconds
Started Jul 03 05:03:33 PM PDT 24
Finished Jul 03 05:03:42 PM PDT 24
Peak memory 250880 kb
Host smart-c2624d91-4321-4711-b1f5-ec6b33e99e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407847486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.407847486
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.2111445929
Short name T606
Test name
Test status
Simulation time 50585588525 ps
CPU time 355.47 seconds
Started Jul 03 05:04:16 PM PDT 24
Finished Jul 03 05:10:12 PM PDT 24
Peak memory 251000 kb
Host smart-7fe4dc17-2e47-44ca-89d2-1ffd4cf6e9ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111445929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.2111445929
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.2369215516
Short name T148
Test name
Test status
Simulation time 357872392933 ps
CPU time 894.59 seconds
Started Jul 03 05:03:59 PM PDT 24
Finished Jul 03 05:18:54 PM PDT 24
Peak memory 496704 kb
Host smart-f99a3863-5726-4d5e-9e49-6612c795b509
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2369215516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.2369215516
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1696791761
Short name T652
Test name
Test status
Simulation time 45673354 ps
CPU time 0.9 seconds
Started Jul 03 05:03:46 PM PDT 24
Finished Jul 03 05:03:48 PM PDT 24
Peak memory 211836 kb
Host smart-07b13fc0-33df-4315-8694-f28c09b1eb5e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696791761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.1696791761
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.3545311845
Short name T39
Test name
Test status
Simulation time 65626867 ps
CPU time 1.13 seconds
Started Jul 03 05:05:18 PM PDT 24
Finished Jul 03 05:05:22 PM PDT 24
Peak memory 208904 kb
Host smart-9ee66089-b2cc-4f50-a854-a4605a19da76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545311845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3545311845
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.283568456
Short name T823
Test name
Test status
Simulation time 1027990523 ps
CPU time 13.29 seconds
Started Jul 03 05:05:18 PM PDT 24
Finished Jul 03 05:05:33 PM PDT 24
Peak memory 225984 kb
Host smart-9602a283-1446-4c01-ad3c-1cf11166383e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283568456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.283568456
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.304496782
Short name T187
Test name
Test status
Simulation time 269730698 ps
CPU time 3.83 seconds
Started Jul 03 05:05:15 PM PDT 24
Finished Jul 03 05:05:25 PM PDT 24
Peak memory 217216 kb
Host smart-315377c3-341b-40ac-85c1-aac889cbb1ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304496782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.304496782
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3600112911
Short name T718
Test name
Test status
Simulation time 30221468 ps
CPU time 2.02 seconds
Started Jul 03 05:04:57 PM PDT 24
Finished Jul 03 05:05:00 PM PDT 24
Peak memory 218172 kb
Host smart-40f0b52c-75b7-4fe7-86cb-fb9f1d1b5410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600112911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3600112911
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3663513444
Short name T338
Test name
Test status
Simulation time 318563265 ps
CPU time 10.89 seconds
Started Jul 03 05:05:11 PM PDT 24
Finished Jul 03 05:05:23 PM PDT 24
Peak memory 225988 kb
Host smart-e35121bb-0268-4018-b040-01105efdb09d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663513444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.3663513444
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1225407483
Short name T855
Test name
Test status
Simulation time 346328870 ps
CPU time 11.63 seconds
Started Jul 03 05:05:12 PM PDT 24
Finished Jul 03 05:05:24 PM PDT 24
Peak memory 218180 kb
Host smart-19270dd3-ac11-4a72-bf56-88ef3cdfb06d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225407483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1225407483
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.4151741835
Short name T624
Test name
Test status
Simulation time 6705807685 ps
CPU time 10.63 seconds
Started Jul 03 05:05:11 PM PDT 24
Finished Jul 03 05:05:22 PM PDT 24
Peak memory 226052 kb
Host smart-b5c2316a-380f-4ba4-8d07-314370049e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151741835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.4151741835
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.629513090
Short name T539
Test name
Test status
Simulation time 406837752 ps
CPU time 4.99 seconds
Started Jul 03 05:05:16 PM PDT 24
Finished Jul 03 05:05:23 PM PDT 24
Peak memory 217664 kb
Host smart-8bac7230-b76a-4b96-a31b-451beb2f7107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629513090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.629513090
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.35808403
Short name T285
Test name
Test status
Simulation time 230181091 ps
CPU time 18.1 seconds
Started Jul 03 05:05:07 PM PDT 24
Finished Jul 03 05:05:25 PM PDT 24
Peak memory 250928 kb
Host smart-f4b98b87-883f-44d9-9ff1-cd38dc6456fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35808403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.35808403
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.1625171670
Short name T824
Test name
Test status
Simulation time 112009507 ps
CPU time 6.26 seconds
Started Jul 03 05:05:16 PM PDT 24
Finished Jul 03 05:05:24 PM PDT 24
Peak memory 248660 kb
Host smart-9a7d1293-94eb-496a-9867-58cc04e64325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625171670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.1625171670
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.3780787893
Short name T81
Test name
Test status
Simulation time 3335285329 ps
CPU time 59.05 seconds
Started Jul 03 05:05:14 PM PDT 24
Finished Jul 03 05:06:14 PM PDT 24
Peak memory 275576 kb
Host smart-66ca752a-fdf7-4d44-8e89-6d61707a30ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780787893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.3780787893
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.372304698
Short name T672
Test name
Test status
Simulation time 133296141642 ps
CPU time 10720.1 seconds
Started Jul 03 05:05:06 PM PDT 24
Finished Jul 03 08:03:47 PM PDT 24
Peak memory 1201340 kb
Host smart-f8c2d3f6-44cc-4f1c-8776-d5ff09f6282b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=372304698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.372304698
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3205472176
Short name T430
Test name
Test status
Simulation time 35432715 ps
CPU time 1.38 seconds
Started Jul 03 05:05:18 PM PDT 24
Finished Jul 03 05:05:22 PM PDT 24
Peak memory 217632 kb
Host smart-401596d0-a7b6-47e3-9858-45485f8432a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205472176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3205472176
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2244450538
Short name T75
Test name
Test status
Simulation time 115926140 ps
CPU time 1.18 seconds
Started Jul 03 05:05:17 PM PDT 24
Finished Jul 03 05:05:19 PM PDT 24
Peak memory 208912 kb
Host smart-e31efac9-a19a-42ce-8ada-189e7f912513
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244450538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2244450538
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.695009510
Short name T560
Test name
Test status
Simulation time 298753612 ps
CPU time 11.33 seconds
Started Jul 03 05:05:15 PM PDT 24
Finished Jul 03 05:05:27 PM PDT 24
Peak memory 218164 kb
Host smart-983589c8-2468-4c24-833c-e3152b22189f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695009510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.695009510
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3957464454
Short name T32
Test name
Test status
Simulation time 186221910 ps
CPU time 5.39 seconds
Started Jul 03 05:05:16 PM PDT 24
Finished Jul 03 05:05:22 PM PDT 24
Peak memory 217104 kb
Host smart-a6139baa-fe61-4d91-971c-1c1d82508ced
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957464454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.3957464454
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.2010230000
Short name T749
Test name
Test status
Simulation time 163894918 ps
CPU time 1.48 seconds
Started Jul 03 05:05:16 PM PDT 24
Finished Jul 03 05:05:20 PM PDT 24
Peak memory 221728 kb
Host smart-47cafb71-bf29-435d-a495-2c55254c4cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010230000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2010230000
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.1573388656
Short name T711
Test name
Test status
Simulation time 1200305219 ps
CPU time 14.49 seconds
Started Jul 03 05:05:13 PM PDT 24
Finished Jul 03 05:05:28 PM PDT 24
Peak memory 225932 kb
Host smart-dd037547-8970-47f8-8a8a-51184431aef0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573388656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1573388656
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.1673182398
Short name T661
Test name
Test status
Simulation time 337722288 ps
CPU time 10.17 seconds
Started Jul 03 05:05:07 PM PDT 24
Finished Jul 03 05:05:18 PM PDT 24
Peak memory 225896 kb
Host smart-9d806c35-63d3-49eb-89bc-3d3751f5bae7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673182398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.1673182398
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.1087324487
Short name T21
Test name
Test status
Simulation time 385309455 ps
CPU time 8.41 seconds
Started Jul 03 05:05:15 PM PDT 24
Finished Jul 03 05:05:24 PM PDT 24
Peak memory 218100 kb
Host smart-2d702e0d-b2af-4dad-bdb1-7b8b0ed91521
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087324487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
1087324487
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.1151523164
Short name T475
Test name
Test status
Simulation time 1481840002 ps
CPU time 7.72 seconds
Started Jul 03 05:05:30 PM PDT 24
Finished Jul 03 05:05:38 PM PDT 24
Peak memory 224884 kb
Host smart-563ad2cb-15d3-43a8-a474-92d5b97b74e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151523164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.1151523164
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.274579664
Short name T488
Test name
Test status
Simulation time 232620877 ps
CPU time 2.89 seconds
Started Jul 03 05:05:11 PM PDT 24
Finished Jul 03 05:05:14 PM PDT 24
Peak memory 214584 kb
Host smart-7d6445fb-a2c4-412e-ba22-9af6b5b6881c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274579664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.274579664
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.1631837934
Short name T402
Test name
Test status
Simulation time 1296054649 ps
CPU time 37.39 seconds
Started Jul 03 05:05:05 PM PDT 24
Finished Jul 03 05:05:43 PM PDT 24
Peak memory 250912 kb
Host smart-1ecb7a55-5f3e-46b4-9f46-7fd894b45496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631837934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1631837934
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.2990432168
Short name T612
Test name
Test status
Simulation time 426377515 ps
CPU time 8.35 seconds
Started Jul 03 05:05:12 PM PDT 24
Finished Jul 03 05:05:21 PM PDT 24
Peak memory 247272 kb
Host smart-4ea39a78-c6d8-446d-a3b2-3e59a7e67960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990432168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.2990432168
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1399212623
Short name T67
Test name
Test status
Simulation time 27000483978 ps
CPU time 219.7 seconds
Started Jul 03 05:05:10 PM PDT 24
Finished Jul 03 05:08:50 PM PDT 24
Peak memory 271844 kb
Host smart-8a3a872e-5856-4181-97c7-89432f6e5d65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399212623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1399212623
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.229267785
Short name T109
Test name
Test status
Simulation time 25969961073 ps
CPU time 549.48 seconds
Started Jul 03 05:05:09 PM PDT 24
Finished Jul 03 05:14:19 PM PDT 24
Peak memory 372976 kb
Host smart-5a96bb7b-139f-4aea-b88a-3074da39f44e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=229267785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.229267785
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1893226234
Short name T562
Test name
Test status
Simulation time 11224325 ps
CPU time 1.01 seconds
Started Jul 03 05:05:16 PM PDT 24
Finished Jul 03 05:05:18 PM PDT 24
Peak memory 211956 kb
Host smart-511f3bb4-9ab5-4372-b48f-cd7c095151c4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893226234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1893226234
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.4148531193
Short name T585
Test name
Test status
Simulation time 49368323 ps
CPU time 0.85 seconds
Started Jul 03 05:05:25 PM PDT 24
Finished Jul 03 05:05:26 PM PDT 24
Peak memory 208744 kb
Host smart-afdccb8f-9842-486c-ac47-7094d9dc8c1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148531193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.4148531193
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.604545072
Short name T802
Test name
Test status
Simulation time 1115406607 ps
CPU time 11.58 seconds
Started Jul 03 05:05:16 PM PDT 24
Finished Jul 03 05:05:30 PM PDT 24
Peak memory 218040 kb
Host smart-83bb039a-a611-4dcb-9944-2604b28eecd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604545072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.604545072
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.307012013
Short name T27
Test name
Test status
Simulation time 2023895346 ps
CPU time 4.98 seconds
Started Jul 03 05:05:18 PM PDT 24
Finished Jul 03 05:05:26 PM PDT 24
Peak memory 217024 kb
Host smart-49c2f51c-f256-4fc1-a90f-cee9a6257cdb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307012013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.307012013
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.3151281864
Short name T584
Test name
Test status
Simulation time 81800852 ps
CPU time 3.13 seconds
Started Jul 03 05:05:17 PM PDT 24
Finished Jul 03 05:05:21 PM PDT 24
Peak memory 218172 kb
Host smart-7f1012e0-9fb2-4ae7-b411-18136303a8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151281864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.3151281864
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.4241795019
Short name T830
Test name
Test status
Simulation time 1987300175 ps
CPU time 22.13 seconds
Started Jul 03 05:05:18 PM PDT 24
Finished Jul 03 05:05:42 PM PDT 24
Peak memory 225940 kb
Host smart-b56f9d5f-c2fc-4c8f-9f5a-5ba8c9da592f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241795019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.4241795019
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2576747300
Short name T228
Test name
Test status
Simulation time 742920693 ps
CPU time 8.02 seconds
Started Jul 03 05:05:11 PM PDT 24
Finished Jul 03 05:05:20 PM PDT 24
Peak memory 226108 kb
Host smart-2f73876e-7f3e-423c-b13d-7c101a6f04c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576747300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2576747300
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.1203766830
Short name T262
Test name
Test status
Simulation time 358900370 ps
CPU time 11.85 seconds
Started Jul 03 05:05:18 PM PDT 24
Finished Jul 03 05:05:32 PM PDT 24
Peak memory 218148 kb
Host smart-6c0a26f2-0283-4831-b3aa-c8ae442d7b33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203766830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
1203766830
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.1587301002
Short name T14
Test name
Test status
Simulation time 771861368 ps
CPU time 13.91 seconds
Started Jul 03 05:05:17 PM PDT 24
Finished Jul 03 05:05:32 PM PDT 24
Peak memory 225932 kb
Host smart-ff88482b-1622-4ef8-abdf-14d9b0827acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587301002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.1587301002
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.1200828396
Short name T645
Test name
Test status
Simulation time 342096877 ps
CPU time 2.6 seconds
Started Jul 03 05:05:16 PM PDT 24
Finished Jul 03 05:05:20 PM PDT 24
Peak memory 214444 kb
Host smart-b75f4166-c758-4b6c-b2b8-bb9163d5b341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200828396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1200828396
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3327638440
Short name T761
Test name
Test status
Simulation time 1444005637 ps
CPU time 31.82 seconds
Started Jul 03 05:05:15 PM PDT 24
Finished Jul 03 05:05:48 PM PDT 24
Peak memory 246488 kb
Host smart-ca99de04-c545-4459-baba-19baa785e43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327638440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3327638440
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.2877898518
Short name T708
Test name
Test status
Simulation time 112820022 ps
CPU time 9.24 seconds
Started Jul 03 05:05:12 PM PDT 24
Finished Jul 03 05:05:22 PM PDT 24
Peak memory 250840 kb
Host smart-c04a4832-321a-4800-aeb9-2e961f12bc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877898518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2877898518
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.1358315618
Short name T495
Test name
Test status
Simulation time 40672808092 ps
CPU time 655.96 seconds
Started Jul 03 05:05:16 PM PDT 24
Finished Jul 03 05:16:13 PM PDT 24
Peak memory 283696 kb
Host smart-a9b8fa46-fbe7-4472-8b68-0bb1c1c2797e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358315618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.1358315618
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3654858955
Short name T154
Test name
Test status
Simulation time 19777153 ps
CPU time 1.36 seconds
Started Jul 03 05:05:15 PM PDT 24
Finished Jul 03 05:05:17 PM PDT 24
Peak memory 212936 kb
Host smart-0ffc192a-1b5c-4437-a844-8084c61ba7b6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654858955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.3654858955
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.3147265788
Short name T526
Test name
Test status
Simulation time 202433288 ps
CPU time 1.06 seconds
Started Jul 03 05:05:17 PM PDT 24
Finished Jul 03 05:05:21 PM PDT 24
Peak memory 208928 kb
Host smart-638d5f09-2156-46d7-887e-7ab31e9d1f37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147265788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.3147265788
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2735756239
Short name T342
Test name
Test status
Simulation time 528460171 ps
CPU time 13.97 seconds
Started Jul 03 05:05:16 PM PDT 24
Finished Jul 03 05:05:31 PM PDT 24
Peak memory 218172 kb
Host smart-db5dd438-f692-4a81-b35e-0e0a781b409e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735756239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2735756239
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.1526513320
Short name T723
Test name
Test status
Simulation time 54155530 ps
CPU time 1.21 seconds
Started Jul 03 05:05:11 PM PDT 24
Finished Jul 03 05:05:13 PM PDT 24
Peak memory 216896 kb
Host smart-983c5fd3-f4d4-44f0-a86b-b4fac32ea1b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526513320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.1526513320
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.29657934
Short name T34
Test name
Test status
Simulation time 113795209 ps
CPU time 3.04 seconds
Started Jul 03 05:05:22 PM PDT 24
Finished Jul 03 05:05:27 PM PDT 24
Peak memory 218148 kb
Host smart-3017ac27-9a34-4c4f-8320-58575f2f13fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29657934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.29657934
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.3042614178
Short name T653
Test name
Test status
Simulation time 316354491 ps
CPU time 14.55 seconds
Started Jul 03 05:05:16 PM PDT 24
Finished Jul 03 05:05:32 PM PDT 24
Peak memory 225940 kb
Host smart-ca273a91-af74-42a1-b01a-b337ce1b039d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042614178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.3042614178
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1151655493
Short name T343
Test name
Test status
Simulation time 1284836083 ps
CPU time 13.42 seconds
Started Jul 03 05:05:11 PM PDT 24
Finished Jul 03 05:05:25 PM PDT 24
Peak memory 225940 kb
Host smart-5165121e-e9aa-4be9-af68-10aff4efba17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151655493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.1151655493
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2393908749
Short name T99
Test name
Test status
Simulation time 870392294 ps
CPU time 6.99 seconds
Started Jul 03 05:05:10 PM PDT 24
Finished Jul 03 05:05:17 PM PDT 24
Peak memory 218156 kb
Host smart-ac3b6ce8-cbeb-459f-a81e-865df15ffda4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393908749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2393908749
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.4032762481
Short name T222
Test name
Test status
Simulation time 353055669 ps
CPU time 13.03 seconds
Started Jul 03 05:05:15 PM PDT 24
Finished Jul 03 05:05:28 PM PDT 24
Peak memory 218284 kb
Host smart-677438e0-110f-4e4c-ae1c-b7660fc637cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032762481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.4032762481
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.90395774
Short name T482
Test name
Test status
Simulation time 54892345 ps
CPU time 1.52 seconds
Started Jul 03 05:05:16 PM PDT 24
Finished Jul 03 05:05:18 PM PDT 24
Peak memory 213756 kb
Host smart-e197451f-30d8-4a13-8c21-fb3f51ff104f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90395774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.90395774
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.3476121478
Short name T852
Test name
Test status
Simulation time 356535710 ps
CPU time 27.24 seconds
Started Jul 03 05:05:14 PM PDT 24
Finished Jul 03 05:05:42 PM PDT 24
Peak memory 250928 kb
Host smart-f9d6704e-f61b-4c60-8b89-33e5f93e1baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476121478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3476121478
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.3142966730
Short name T609
Test name
Test status
Simulation time 80035675 ps
CPU time 6.73 seconds
Started Jul 03 05:05:15 PM PDT 24
Finished Jul 03 05:05:23 PM PDT 24
Peak memory 250640 kb
Host smart-68751009-bfa0-4d3a-9586-f5480991d078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142966730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3142966730
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.2366770049
Short name T803
Test name
Test status
Simulation time 13031286448 ps
CPU time 198.36 seconds
Started Jul 03 05:05:21 PM PDT 24
Finished Jul 03 05:08:42 PM PDT 24
Peak memory 246196 kb
Host smart-a18a7c72-e691-474a-8777-a42f9be73fb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366770049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.2366770049
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1025209650
Short name T798
Test name
Test status
Simulation time 12771517 ps
CPU time 1 seconds
Started Jul 03 05:05:15 PM PDT 24
Finished Jul 03 05:05:17 PM PDT 24
Peak memory 211868 kb
Host smart-e6671fbe-1c40-4aa5-b5a7-fb0b3ff36f5b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025209650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1025209650
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.2095643515
Short name T618
Test name
Test status
Simulation time 210204690 ps
CPU time 1.11 seconds
Started Jul 03 05:05:14 PM PDT 24
Finished Jul 03 05:05:16 PM PDT 24
Peak memory 208892 kb
Host smart-385365d7-3ca9-4964-9c2f-459e7d7a1a73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095643515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.2095643515
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.990249775
Short name T486
Test name
Test status
Simulation time 249804448 ps
CPU time 9.18 seconds
Started Jul 03 05:05:17 PM PDT 24
Finished Jul 03 05:05:28 PM PDT 24
Peak memory 218112 kb
Host smart-c777a68d-d8d9-416b-b866-1a4506590dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990249775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.990249775
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.3107592940
Short name T29
Test name
Test status
Simulation time 1445379039 ps
CPU time 5.95 seconds
Started Jul 03 05:05:22 PM PDT 24
Finished Jul 03 05:05:30 PM PDT 24
Peak memory 217304 kb
Host smart-51cfb7ce-0973-48db-9020-d3a352f64fbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107592940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.3107592940
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.3986932711
Short name T350
Test name
Test status
Simulation time 30327832 ps
CPU time 1.88 seconds
Started Jul 03 05:05:14 PM PDT 24
Finished Jul 03 05:05:17 PM PDT 24
Peak memory 221988 kb
Host smart-31c9d981-1a7c-4b49-921d-f88475325698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986932711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.3986932711
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.1127987188
Short name T459
Test name
Test status
Simulation time 711954190 ps
CPU time 11.71 seconds
Started Jul 03 05:05:13 PM PDT 24
Finished Jul 03 05:05:25 PM PDT 24
Peak memory 225940 kb
Host smart-785de01e-e946-44cc-be13-8148a99c95b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127987188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.1127987188
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1409935220
Short name T734
Test name
Test status
Simulation time 229256329 ps
CPU time 5.99 seconds
Started Jul 03 05:05:21 PM PDT 24
Finished Jul 03 05:05:29 PM PDT 24
Peak memory 218176 kb
Host smart-04b014cd-a011-48cc-b084-c2a32b93822c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409935220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1409935220
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1948928273
Short name T321
Test name
Test status
Simulation time 1699041946 ps
CPU time 6.62 seconds
Started Jul 03 05:05:24 PM PDT 24
Finished Jul 03 05:05:31 PM PDT 24
Peak memory 218192 kb
Host smart-3a757cd9-f101-411e-940e-336fb80407b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948928273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1948928273
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.2945519300
Short name T104
Test name
Test status
Simulation time 228933390 ps
CPU time 2.93 seconds
Started Jul 03 05:05:17 PM PDT 24
Finished Jul 03 05:05:21 PM PDT 24
Peak memory 214972 kb
Host smart-f43abf56-f8d0-464a-bb6f-2fb8eb9d0aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945519300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2945519300
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.140475042
Short name T733
Test name
Test status
Simulation time 445430842 ps
CPU time 26.32 seconds
Started Jul 03 05:05:17 PM PDT 24
Finished Jul 03 05:05:45 PM PDT 24
Peak memory 250928 kb
Host smart-afbd21e1-3799-40b7-82ae-06e244ce7fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140475042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.140475042
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.2835652228
Short name T226
Test name
Test status
Simulation time 688487782 ps
CPU time 8.62 seconds
Started Jul 03 05:05:19 PM PDT 24
Finished Jul 03 05:05:31 PM PDT 24
Peak memory 250892 kb
Host smart-0ec15ccd-b7df-4f87-8ec3-2f2024768ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835652228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.2835652228
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.3207919963
Short name T251
Test name
Test status
Simulation time 1934050005 ps
CPU time 41.38 seconds
Started Jul 03 05:05:20 PM PDT 24
Finished Jul 03 05:06:04 PM PDT 24
Peak memory 252832 kb
Host smart-18e827e9-104a-4fe5-82fb-2d8c00948422
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207919963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.3207919963
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3128935868
Short name T461
Test name
Test status
Simulation time 46837377 ps
CPU time 0.91 seconds
Started Jul 03 05:05:19 PM PDT 24
Finished Jul 03 05:05:22 PM PDT 24
Peak memory 212996 kb
Host smart-25490110-3ec2-415d-a557-438272f3600f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128935868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3128935868
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.4135113626
Short name T167
Test name
Test status
Simulation time 32977176 ps
CPU time 0.88 seconds
Started Jul 03 05:05:19 PM PDT 24
Finished Jul 03 05:05:23 PM PDT 24
Peak memory 208884 kb
Host smart-c92358a6-bab0-4d70-9545-53638f48d900
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135113626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.4135113626
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.3736821675
Short name T785
Test name
Test status
Simulation time 915348915 ps
CPU time 8.98 seconds
Started Jul 03 05:05:20 PM PDT 24
Finished Jul 03 05:05:32 PM PDT 24
Peak memory 218128 kb
Host smart-890d6c7c-a8bf-4467-b76c-d64c83e87e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736821675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.3736821675
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.1741713875
Short name T664
Test name
Test status
Simulation time 1209054510 ps
CPU time 7.08 seconds
Started Jul 03 05:05:15 PM PDT 24
Finished Jul 03 05:05:23 PM PDT 24
Peak memory 217472 kb
Host smart-b81f4a4f-7fa1-4110-bc10-07284d0e2017
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741713875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.1741713875
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.540094330
Short name T421
Test name
Test status
Simulation time 85881573 ps
CPU time 2.35 seconds
Started Jul 03 05:05:14 PM PDT 24
Finished Jul 03 05:05:17 PM PDT 24
Peak memory 218108 kb
Host smart-1d3799fb-fc77-4bf2-bdb4-05bb4ada41c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540094330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.540094330
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.3007666465
Short name T516
Test name
Test status
Simulation time 764234250 ps
CPU time 18.9 seconds
Started Jul 03 05:05:18 PM PDT 24
Finished Jul 03 05:05:39 PM PDT 24
Peak memory 225976 kb
Host smart-8cad7a29-b2f3-4cdd-9c48-0a2bf49abf6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007666465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.3007666465
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3216314118
Short name T368
Test name
Test status
Simulation time 493951620 ps
CPU time 16.92 seconds
Started Jul 03 05:05:16 PM PDT 24
Finished Jul 03 05:05:35 PM PDT 24
Peak memory 225856 kb
Host smart-9f77f79c-afca-42e3-a625-1a13384e93e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216314118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3216314118
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.4107213497
Short name T541
Test name
Test status
Simulation time 5267501149 ps
CPU time 10.67 seconds
Started Jul 03 05:05:22 PM PDT 24
Finished Jul 03 05:05:35 PM PDT 24
Peak memory 226024 kb
Host smart-7a86fe76-ec89-45ec-a8e0-1bc4e29285b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107213497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
4107213497
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.3653980042
Short name T568
Test name
Test status
Simulation time 1555977931 ps
CPU time 9.15 seconds
Started Jul 03 05:05:18 PM PDT 24
Finished Jul 03 05:05:29 PM PDT 24
Peak memory 218208 kb
Host smart-ba861ac5-e8eb-482c-b418-90e0a869257f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653980042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.3653980042
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.2511877329
Short name T435
Test name
Test status
Simulation time 37741193 ps
CPU time 2.82 seconds
Started Jul 03 05:05:14 PM PDT 24
Finished Jul 03 05:05:17 PM PDT 24
Peak memory 217724 kb
Host smart-45e27946-f938-44a8-9c77-28270ab03b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511877329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2511877329
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.2925871241
Short name T781
Test name
Test status
Simulation time 658238009 ps
CPU time 21.81 seconds
Started Jul 03 05:05:19 PM PDT 24
Finished Jul 03 05:05:43 PM PDT 24
Peak memory 251064 kb
Host smart-fe35929d-86cf-4fc9-baad-f73cac2d3202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925871241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.2925871241
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.445032722
Short name T335
Test name
Test status
Simulation time 1066145823 ps
CPU time 6.36 seconds
Started Jul 03 05:05:20 PM PDT 24
Finished Jul 03 05:05:29 PM PDT 24
Peak memory 250912 kb
Host smart-124fb9b6-5db1-45f0-bb84-c0a7562aac4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445032722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.445032722
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.3714963998
Short name T792
Test name
Test status
Simulation time 2117095457 ps
CPU time 68.17 seconds
Started Jul 03 05:05:19 PM PDT 24
Finished Jul 03 05:06:30 PM PDT 24
Peak memory 279412 kb
Host smart-0e10f85f-42da-48e4-9e61-b81077e5f23c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714963998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.3714963998
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.3185603689
Short name T265
Test name
Test status
Simulation time 24354960 ps
CPU time 1.05 seconds
Started Jul 03 05:05:19 PM PDT 24
Finished Jul 03 05:05:23 PM PDT 24
Peak memory 212968 kb
Host smart-f5b85fe3-a2e7-4584-95e4-776845a7bd1e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185603689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.3185603689
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.1245927706
Short name T629
Test name
Test status
Simulation time 71067798 ps
CPU time 1.13 seconds
Started Jul 03 05:05:16 PM PDT 24
Finished Jul 03 05:05:18 PM PDT 24
Peak memory 208924 kb
Host smart-0eb66681-23cb-4800-96d2-429fc5b867a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245927706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1245927706
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2743771949
Short name T750
Test name
Test status
Simulation time 993263279 ps
CPU time 21.18 seconds
Started Jul 03 05:05:19 PM PDT 24
Finished Jul 03 05:05:43 PM PDT 24
Peak memory 225972 kb
Host smart-19a7c0fd-f664-472a-a22e-3cf18fa21c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743771949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2743771949
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.3960089318
Short name T390
Test name
Test status
Simulation time 153627645 ps
CPU time 2.68 seconds
Started Jul 03 05:05:36 PM PDT 24
Finished Jul 03 05:05:39 PM PDT 24
Peak memory 217124 kb
Host smart-43542981-24c8-4536-afdc-a1b45369a9bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960089318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.3960089318
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3711381896
Short name T642
Test name
Test status
Simulation time 111014092 ps
CPU time 3.64 seconds
Started Jul 03 05:05:24 PM PDT 24
Finished Jul 03 05:05:28 PM PDT 24
Peak memory 218188 kb
Host smart-77d6d728-d341-46c1-9381-60ec1b8a524c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711381896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3711381896
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.2313401532
Short name T223
Test name
Test status
Simulation time 288366901 ps
CPU time 10.83 seconds
Started Jul 03 05:05:18 PM PDT 24
Finished Jul 03 05:05:31 PM PDT 24
Peak memory 225936 kb
Host smart-23de3684-49a1-485b-a55f-2da463d7987f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313401532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.2313401532
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.375592902
Short name T234
Test name
Test status
Simulation time 1047908867 ps
CPU time 10.26 seconds
Started Jul 03 05:05:22 PM PDT 24
Finished Jul 03 05:05:34 PM PDT 24
Peak memory 225932 kb
Host smart-cf1f6d04-5bcc-49f6-8fe2-8b09e7088b41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375592902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_di
gest.375592902
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3476870510
Short name T480
Test name
Test status
Simulation time 519204134 ps
CPU time 9.91 seconds
Started Jul 03 05:05:19 PM PDT 24
Finished Jul 03 05:05:32 PM PDT 24
Peak memory 218152 kb
Host smart-08d9432f-f786-4fa9-9688-675a8b68b6a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476870510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3476870510
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.3333785897
Short name T230
Test name
Test status
Simulation time 208670341 ps
CPU time 6.28 seconds
Started Jul 03 05:05:15 PM PDT 24
Finished Jul 03 05:05:21 PM PDT 24
Peak memory 224900 kb
Host smart-580a62b1-01e7-4096-abfa-87e4aa934d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333785897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3333785897
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.103872187
Short name T841
Test name
Test status
Simulation time 32420395 ps
CPU time 2.3 seconds
Started Jul 03 05:05:19 PM PDT 24
Finished Jul 03 05:05:24 PM PDT 24
Peak memory 214216 kb
Host smart-fec8dc30-7d80-48e7-871d-9aaba7e5c9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103872187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.103872187
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.1550889280
Short name T542
Test name
Test status
Simulation time 1352286274 ps
CPU time 28.7 seconds
Started Jul 03 05:05:21 PM PDT 24
Finished Jul 03 05:05:52 PM PDT 24
Peak memory 250896 kb
Host smart-1de20e43-61bd-411f-b1dc-9ec24ef5ebdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550889280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1550889280
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.3403536962
Short name T564
Test name
Test status
Simulation time 54505839 ps
CPU time 6.83 seconds
Started Jul 03 05:05:16 PM PDT 24
Finished Jul 03 05:05:26 PM PDT 24
Peak memory 250404 kb
Host smart-8368775c-613c-4f2a-80bd-e6433faabaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403536962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3403536962
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.3851472531
Short name T683
Test name
Test status
Simulation time 7308741392 ps
CPU time 36.43 seconds
Started Jul 03 05:05:19 PM PDT 24
Finished Jul 03 05:05:58 PM PDT 24
Peak memory 224952 kb
Host smart-17804499-26a8-45f1-847d-d6d36395b222
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851472531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.3851472531
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2974991053
Short name T693
Test name
Test status
Simulation time 10716114 ps
CPU time 0.99 seconds
Started Jul 03 05:05:19 PM PDT 24
Finished Jul 03 05:05:23 PM PDT 24
Peak memory 211844 kb
Host smart-04c131a3-83ac-46ee-bdd0-caff9c8ba7bf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974991053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.2974991053
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.241523191
Short name T454
Test name
Test status
Simulation time 27351677 ps
CPU time 0.99 seconds
Started Jul 03 05:05:18 PM PDT 24
Finished Jul 03 05:05:22 PM PDT 24
Peak memory 208900 kb
Host smart-46e592d6-5eb9-4735-b2d0-0f01a0038ee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241523191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.241523191
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.436795516
Short name T300
Test name
Test status
Simulation time 668263909 ps
CPU time 11.52 seconds
Started Jul 03 05:05:13 PM PDT 24
Finished Jul 03 05:05:25 PM PDT 24
Peak memory 225992 kb
Host smart-60efd9f4-d87c-4d55-80bf-f6cc924c9c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436795516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.436795516
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3237866158
Short name T8
Test name
Test status
Simulation time 81374811 ps
CPU time 1.66 seconds
Started Jul 03 05:05:12 PM PDT 24
Finished Jul 03 05:05:14 PM PDT 24
Peak memory 217008 kb
Host smart-34734a82-3fe2-4c64-9bdb-be07e7cd52df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237866158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3237866158
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2296779697
Short name T566
Test name
Test status
Simulation time 142791371 ps
CPU time 3.56 seconds
Started Jul 03 05:05:16 PM PDT 24
Finished Jul 03 05:05:21 PM PDT 24
Peak memory 218168 kb
Host smart-e0f429de-f50d-4438-857d-7408093cdc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296779697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2296779697
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.498204239
Short name T394
Test name
Test status
Simulation time 392655417 ps
CPU time 10.26 seconds
Started Jul 03 05:05:16 PM PDT 24
Finished Jul 03 05:05:28 PM PDT 24
Peak memory 225940 kb
Host smart-c0b8afa1-cf82-48d4-bc20-a84c683a207a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498204239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di
gest.498204239
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3862657425
Short name T250
Test name
Test status
Simulation time 1391141781 ps
CPU time 6.81 seconds
Started Jul 03 05:05:16 PM PDT 24
Finished Jul 03 05:05:24 PM PDT 24
Peak memory 225964 kb
Host smart-1244d2ae-2ec1-4e38-91ba-82f8b64994d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862657425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3862657425
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.2786735740
Short name T319
Test name
Test status
Simulation time 736444163 ps
CPU time 9.91 seconds
Started Jul 03 05:05:18 PM PDT 24
Finished Jul 03 05:05:30 PM PDT 24
Peak memory 225980 kb
Host smart-ecdae558-34bf-4e4d-8bc8-fef27019c8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786735740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.2786735740
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2533253073
Short name T777
Test name
Test status
Simulation time 74689256 ps
CPU time 1.37 seconds
Started Jul 03 05:05:18 PM PDT 24
Finished Jul 03 05:05:21 PM PDT 24
Peak memory 217552 kb
Host smart-cb369638-f982-42a3-ba6b-221aa078ed8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533253073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2533253073
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.2085516427
Short name T496
Test name
Test status
Simulation time 1616998667 ps
CPU time 27.42 seconds
Started Jul 03 05:05:23 PM PDT 24
Finished Jul 03 05:05:51 PM PDT 24
Peak memory 250880 kb
Host smart-ab12b9f6-467d-4715-85ea-13a82ecc5805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085516427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.2085516427
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3366938100
Short name T301
Test name
Test status
Simulation time 365876522 ps
CPU time 7.56 seconds
Started Jul 03 05:05:19 PM PDT 24
Finished Jul 03 05:05:30 PM PDT 24
Peak memory 250924 kb
Host smart-e2ca920d-0b79-4bf7-a7fb-b5e601a82ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366938100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3366938100
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.3825895304
Short name T867
Test name
Test status
Simulation time 6228328756 ps
CPU time 84.21 seconds
Started Jul 03 05:05:14 PM PDT 24
Finished Jul 03 05:06:39 PM PDT 24
Peak memory 276844 kb
Host smart-2bd5e505-0b37-4efe-b082-90a3d41e4d17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825895304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.3825895304
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3332911198
Short name T169
Test name
Test status
Simulation time 14150046 ps
CPU time 0.92 seconds
Started Jul 03 05:05:35 PM PDT 24
Finished Jul 03 05:05:36 PM PDT 24
Peak memory 208596 kb
Host smart-a566f6d0-252b-4531-9d51-abb5d5d74958
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332911198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.3332911198
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.2444068196
Short name T94
Test name
Test status
Simulation time 80038224 ps
CPU time 1.02 seconds
Started Jul 03 05:05:25 PM PDT 24
Finished Jul 03 05:05:27 PM PDT 24
Peak memory 208916 kb
Host smart-bee4fd09-bd0e-440e-bd32-983d4e89edb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444068196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.2444068196
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1374967884
Short name T236
Test name
Test status
Simulation time 1534100809 ps
CPU time 15.57 seconds
Started Jul 03 05:05:21 PM PDT 24
Finished Jul 03 05:05:39 PM PDT 24
Peak memory 225948 kb
Host smart-195a7ecd-3f91-474c-9613-b8d7bc6aabda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374967884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1374967884
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.943810001
Short name T800
Test name
Test status
Simulation time 523399769 ps
CPU time 3.89 seconds
Started Jul 03 05:05:16 PM PDT 24
Finished Jul 03 05:05:21 PM PDT 24
Peak memory 217028 kb
Host smart-28bae699-7f4f-4bda-9466-52d64d7b8f8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943810001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.943810001
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.1515778870
Short name T549
Test name
Test status
Simulation time 222097234 ps
CPU time 2.65 seconds
Started Jul 03 05:05:38 PM PDT 24
Finished Jul 03 05:05:41 PM PDT 24
Peak memory 222272 kb
Host smart-2c3f8043-f0e4-41ad-86b6-7d6ec3e8cae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515778870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.1515778870
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.2245269011
Short name T555
Test name
Test status
Simulation time 264593411 ps
CPU time 11.9 seconds
Started Jul 03 05:05:45 PM PDT 24
Finished Jul 03 05:05:57 PM PDT 24
Peak memory 225892 kb
Host smart-86c95fa2-4465-4699-9586-88f5cba5b199
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245269011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2245269011
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.4207771296
Short name T332
Test name
Test status
Simulation time 1725686483 ps
CPU time 12.85 seconds
Started Jul 03 05:05:24 PM PDT 24
Finished Jul 03 05:05:38 PM PDT 24
Peak memory 225956 kb
Host smart-f029e5d9-c589-49f6-8d66-c36f2e2ee89c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207771296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.4207771296
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1548504348
Short name T398
Test name
Test status
Simulation time 760722715 ps
CPU time 15.05 seconds
Started Jul 03 05:05:16 PM PDT 24
Finished Jul 03 05:05:33 PM PDT 24
Peak memory 218176 kb
Host smart-52b8125e-f569-4026-8d2d-1e489813b819
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548504348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1548504348
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.2608855271
Short name T730
Test name
Test status
Simulation time 341059653 ps
CPU time 9.26 seconds
Started Jul 03 05:05:19 PM PDT 24
Finished Jul 03 05:05:31 PM PDT 24
Peak memory 224692 kb
Host smart-371773b2-1cba-4f0d-902d-444c2234a5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608855271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.2608855271
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.942246275
Short name T1
Test name
Test status
Simulation time 55297867 ps
CPU time 1.63 seconds
Started Jul 03 05:05:16 PM PDT 24
Finished Jul 03 05:05:18 PM PDT 24
Peak memory 213976 kb
Host smart-fc4a4fd0-edc7-41a4-a773-15b76a00b54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942246275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.942246275
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.176199466
Short name T231
Test name
Test status
Simulation time 1676168463 ps
CPU time 20.28 seconds
Started Jul 03 05:05:17 PM PDT 24
Finished Jul 03 05:05:39 PM PDT 24
Peak memory 250932 kb
Host smart-263e176e-cc19-4ab1-bf35-430d5374063f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176199466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.176199466
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.2683452423
Short name T91
Test name
Test status
Simulation time 43872014 ps
CPU time 6.03 seconds
Started Jul 03 05:05:18 PM PDT 24
Finished Jul 03 05:05:27 PM PDT 24
Peak memory 244404 kb
Host smart-ea35a060-f1c2-4269-adff-ba2811312110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683452423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2683452423
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.1232532264
Short name T79
Test name
Test status
Simulation time 6911092955 ps
CPU time 107.22 seconds
Started Jul 03 05:05:17 PM PDT 24
Finished Jul 03 05:07:06 PM PDT 24
Peak memory 270768 kb
Host smart-ede9ffcc-d3fa-4f49-bd0d-e9232c894e6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232532264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.1232532264
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2580172405
Short name T862
Test name
Test status
Simulation time 49206610 ps
CPU time 0.97 seconds
Started Jul 03 05:05:17 PM PDT 24
Finished Jul 03 05:05:20 PM PDT 24
Peak memory 211812 kb
Host smart-8a1b05d2-f490-4068-856f-607593fdb293
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580172405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.2580172405
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.4198588839
Short name T598
Test name
Test status
Simulation time 29544053 ps
CPU time 1.08 seconds
Started Jul 03 05:05:19 PM PDT 24
Finished Jul 03 05:05:22 PM PDT 24
Peak memory 208924 kb
Host smart-d74e16b1-40e6-44d5-b054-0e9c66b24dc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198588839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.4198588839
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.70061871
Short name T499
Test name
Test status
Simulation time 2425052976 ps
CPU time 13.57 seconds
Started Jul 03 05:05:19 PM PDT 24
Finished Jul 03 05:05:35 PM PDT 24
Peak memory 225996 kb
Host smart-b16c4ade-8c77-4989-8f88-0d1dc91a5eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70061871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.70061871
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.3580926027
Short name T31
Test name
Test status
Simulation time 346183655 ps
CPU time 8.63 seconds
Started Jul 03 05:05:21 PM PDT 24
Finished Jul 03 05:05:32 PM PDT 24
Peak memory 217148 kb
Host smart-4209e6e8-34b7-40a1-a4b1-a674f4a18ca9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580926027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.3580926027
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3822937655
Short name T552
Test name
Test status
Simulation time 66340978 ps
CPU time 1.78 seconds
Started Jul 03 05:05:19 PM PDT 24
Finished Jul 03 05:05:24 PM PDT 24
Peak memory 218052 kb
Host smart-a52991c2-7206-4bf0-a7d3-47f451fb9dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822937655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3822937655
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1426712260
Short name T103
Test name
Test status
Simulation time 1161104720 ps
CPU time 8.73 seconds
Started Jul 03 05:05:18 PM PDT 24
Finished Jul 03 05:05:28 PM PDT 24
Peak memory 225916 kb
Host smart-dbeedbf1-f196-4ffe-bb46-f10e930a6ad4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426712260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1426712260
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.1241218837
Short name T681
Test name
Test status
Simulation time 3654174116 ps
CPU time 9.46 seconds
Started Jul 03 05:05:17 PM PDT 24
Finished Jul 03 05:05:28 PM PDT 24
Peak memory 226060 kb
Host smart-be36850e-1261-4bfb-9685-51c12e2d9ded
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241218837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
1241218837
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3735491450
Short name T318
Test name
Test status
Simulation time 564317612 ps
CPU time 7.58 seconds
Started Jul 03 05:05:19 PM PDT 24
Finished Jul 03 05:05:29 PM PDT 24
Peak memory 225240 kb
Host smart-05be07d0-486a-48df-bbda-728af03d9e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735491450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3735491450
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.307725061
Short name T439
Test name
Test status
Simulation time 44655709 ps
CPU time 2.05 seconds
Started Jul 03 05:05:18 PM PDT 24
Finished Jul 03 05:05:23 PM PDT 24
Peak memory 214324 kb
Host smart-38f2c355-1488-4290-8026-351fb5141174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307725061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.307725061
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.2318382742
Short name T444
Test name
Test status
Simulation time 291209371 ps
CPU time 28.77 seconds
Started Jul 03 05:05:17 PM PDT 24
Finished Jul 03 05:05:48 PM PDT 24
Peak memory 250932 kb
Host smart-aeedfcd9-3941-49fd-ae38-ffc3d417e4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318382742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.2318382742
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1871152813
Short name T241
Test name
Test status
Simulation time 347110342 ps
CPU time 3.58 seconds
Started Jul 03 05:05:19 PM PDT 24
Finished Jul 03 05:05:26 PM PDT 24
Peak memory 222216 kb
Host smart-67783dbe-7f85-48c2-b578-510dea62d202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871152813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1871152813
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2185673354
Short name T846
Test name
Test status
Simulation time 4131376221 ps
CPU time 130.67 seconds
Started Jul 03 05:05:16 PM PDT 24
Finished Jul 03 05:07:28 PM PDT 24
Peak memory 283184 kb
Host smart-6a1e1be8-faa7-4f8a-9a6b-d252042b31cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185673354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2185673354
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.4129967758
Short name T492
Test name
Test status
Simulation time 39658849 ps
CPU time 0.93 seconds
Started Jul 03 05:05:33 PM PDT 24
Finished Jul 03 05:05:34 PM PDT 24
Peak memory 211860 kb
Host smart-28873e37-555d-4b9f-85da-64fdf2f5c7b7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129967758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.4129967758
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.2372255282
Short name T848
Test name
Test status
Simulation time 33033923 ps
CPU time 0.88 seconds
Started Jul 03 05:04:02 PM PDT 24
Finished Jul 03 05:04:03 PM PDT 24
Peak memory 208892 kb
Host smart-2060e43f-54fa-41e1-92fa-c5f0e94cec3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372255282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.2372255282
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.4224591870
Short name T266
Test name
Test status
Simulation time 37118962 ps
CPU time 0.9 seconds
Started Jul 03 05:03:58 PM PDT 24
Finished Jul 03 05:03:59 PM PDT 24
Peak memory 208792 kb
Host smart-5b5a05bd-064a-47c6-a377-97c544fc7ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224591870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.4224591870
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3530786464
Short name T763
Test name
Test status
Simulation time 170206475 ps
CPU time 2.77 seconds
Started Jul 03 05:04:00 PM PDT 24
Finished Jul 03 05:04:03 PM PDT 24
Peak memory 216880 kb
Host smart-74aeab6c-4df2-4bbf-9d6e-4c5a3cc81414
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530786464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3530786464
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.348705404
Short name T43
Test name
Test status
Simulation time 8422287846 ps
CPU time 79.87 seconds
Started Jul 03 05:04:04 PM PDT 24
Finished Jul 03 05:05:29 PM PDT 24
Peak memory 218812 kb
Host smart-21f7a142-5d35-48eb-9c95-75ddd2b7aef3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348705404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.348705404
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.533796571
Short name T397
Test name
Test status
Simulation time 4332620626 ps
CPU time 10.29 seconds
Started Jul 03 05:04:08 PM PDT 24
Finished Jul 03 05:04:19 PM PDT 24
Peak memory 217788 kb
Host smart-2b7f7a37-964a-41e8-b4b9-dc54315ec055
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533796571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.533796571
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.829145023
Short name T595
Test name
Test status
Simulation time 1728644417 ps
CPU time 12.18 seconds
Started Jul 03 05:03:58 PM PDT 24
Finished Jul 03 05:04:11 PM PDT 24
Peak memory 218168 kb
Host smart-4cd30f9b-d07f-48a2-9d94-bdb77a16e80f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829145023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
prog_failure.829145023
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2727142013
Short name T716
Test name
Test status
Simulation time 5199610664 ps
CPU time 21.97 seconds
Started Jul 03 05:03:54 PM PDT 24
Finished Jul 03 05:04:17 PM PDT 24
Peak memory 217676 kb
Host smart-c3f2c93f-6561-47e7-a51e-98450be0b712
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727142013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.2727142013
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.751392999
Short name T485
Test name
Test status
Simulation time 404598745 ps
CPU time 4.08 seconds
Started Jul 03 05:04:09 PM PDT 24
Finished Jul 03 05:04:14 PM PDT 24
Peak memory 217652 kb
Host smart-311a6f58-19ab-4be2-933a-d9c5af9d8a59
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751392999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.751392999
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3410595618
Short name T356
Test name
Test status
Simulation time 11367924856 ps
CPU time 50.87 seconds
Started Jul 03 05:04:03 PM PDT 24
Finished Jul 03 05:04:54 PM PDT 24
Peak memory 250980 kb
Host smart-cfc472db-9aad-4f21-a828-ac3b75640b24
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410595618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3410595618
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.4029069930
Short name T801
Test name
Test status
Simulation time 656209343 ps
CPU time 15.78 seconds
Started Jul 03 05:03:40 PM PDT 24
Finished Jul 03 05:03:58 PM PDT 24
Peak memory 250908 kb
Host smart-53e97988-9e85-4311-b2a6-16601a3ccd28
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029069930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.4029069930
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.2632771260
Short name T808
Test name
Test status
Simulation time 126914249 ps
CPU time 2.53 seconds
Started Jul 03 05:03:48 PM PDT 24
Finished Jul 03 05:03:50 PM PDT 24
Peak memory 222308 kb
Host smart-b20c3c61-e50d-4de4-9d36-a01ec363adbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632771260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.2632771260
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.825247675
Short name T86
Test name
Test status
Simulation time 213418639 ps
CPU time 7.93 seconds
Started Jul 03 05:03:31 PM PDT 24
Finished Jul 03 05:03:39 PM PDT 24
Peak memory 214576 kb
Host smart-56220ea8-4a6c-4221-a70b-f8fe4919bd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825247675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.825247675
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.1840621194
Short name T699
Test name
Test status
Simulation time 870016077 ps
CPU time 15.02 seconds
Started Jul 03 05:04:00 PM PDT 24
Finished Jul 03 05:04:15 PM PDT 24
Peak memory 225972 kb
Host smart-228866a7-3639-4146-b98e-e43f42fcda5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840621194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1840621194
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.96191384
Short name T553
Test name
Test status
Simulation time 382070843 ps
CPU time 10.73 seconds
Started Jul 03 05:03:49 PM PDT 24
Finished Jul 03 05:04:00 PM PDT 24
Peak memory 225952 kb
Host smart-e2d8f10e-a38c-46af-9291-f761b65d9e81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96191384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dige
st.96191384
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3972969962
Short name T550
Test name
Test status
Simulation time 1467027804 ps
CPU time 9.28 seconds
Started Jul 03 05:04:08 PM PDT 24
Finished Jul 03 05:04:18 PM PDT 24
Peak memory 225924 kb
Host smart-bed2c648-ed73-4b42-9ca0-49813e328fae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972969962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
972969962
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.915385796
Short name T55
Test name
Test status
Simulation time 3516948085 ps
CPU time 10.99 seconds
Started Jul 03 05:04:09 PM PDT 24
Finished Jul 03 05:04:20 PM PDT 24
Peak memory 226028 kb
Host smart-ca5a179f-6a13-4863-9692-3ce5df838de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915385796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.915385796
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.440747556
Short name T78
Test name
Test status
Simulation time 72798723 ps
CPU time 1.91 seconds
Started Jul 03 05:04:00 PM PDT 24
Finished Jul 03 05:04:02 PM PDT 24
Peak memory 214108 kb
Host smart-e3dfd550-cbd3-458c-8aac-88879b657b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440747556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.440747556
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.4087403529
Short name T825
Test name
Test status
Simulation time 817596480 ps
CPU time 36.07 seconds
Started Jul 03 05:03:50 PM PDT 24
Finished Jul 03 05:04:27 PM PDT 24
Peak memory 250940 kb
Host smart-4e1425a8-aa03-4748-bd9e-7415e3016b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087403529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.4087403529
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.2271373900
Short name T845
Test name
Test status
Simulation time 351792947 ps
CPU time 7.9 seconds
Started Jul 03 05:03:59 PM PDT 24
Finished Jul 03 05:04:07 PM PDT 24
Peak memory 250780 kb
Host smart-46d5f405-30b5-4238-b43e-da84f15d4d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271373900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2271373900
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1976152705
Short name T591
Test name
Test status
Simulation time 2098892796 ps
CPU time 52.3 seconds
Started Jul 03 05:04:00 PM PDT 24
Finished Jul 03 05:04:53 PM PDT 24
Peak memory 250784 kb
Host smart-ff4e4879-d78c-4971-a241-a901231a61a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976152705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1976152705
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.2724315642
Short name T144
Test name
Test status
Simulation time 20205356971 ps
CPU time 800.26 seconds
Started Jul 03 05:04:00 PM PDT 24
Finished Jul 03 05:17:21 PM PDT 24
Peak memory 422028 kb
Host smart-cdcd17dd-befa-4ef2-afc3-98db693c0a97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2724315642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.2724315642
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2263219752
Short name T246
Test name
Test status
Simulation time 29308457 ps
CPU time 0.89 seconds
Started Jul 03 05:03:57 PM PDT 24
Finished Jul 03 05:03:58 PM PDT 24
Peak memory 211956 kb
Host smart-6c4a18ca-1b8a-443c-b9ae-7acc96e16fc8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263219752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.2263219752
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.29464010
Short name T706
Test name
Test status
Simulation time 81847966 ps
CPU time 1.21 seconds
Started Jul 03 05:03:55 PM PDT 24
Finished Jul 03 05:03:56 PM PDT 24
Peak memory 208972 kb
Host smart-c1a781fd-c52f-4de3-b230-99c3fae9cace
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29464010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.29464010
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3825014725
Short name T216
Test name
Test status
Simulation time 18048088 ps
CPU time 0.79 seconds
Started Jul 03 05:03:42 PM PDT 24
Finished Jul 03 05:03:43 PM PDT 24
Peak memory 208756 kb
Host smart-76a7ccb0-a224-43d0-8024-e3fe71df57ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825014725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3825014725
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.3643175547
Short name T157
Test name
Test status
Simulation time 2975177075 ps
CPU time 12.12 seconds
Started Jul 03 05:04:04 PM PDT 24
Finished Jul 03 05:04:17 PM PDT 24
Peak memory 218172 kb
Host smart-33c3bfc5-53e9-441e-8577-d0387bd3c168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643175547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3643175547
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.856132914
Short name T643
Test name
Test status
Simulation time 104974312 ps
CPU time 2.02 seconds
Started Jul 03 05:04:15 PM PDT 24
Finished Jul 03 05:04:18 PM PDT 24
Peak memory 217108 kb
Host smart-6bc0401b-e384-4528-97f1-524e946525a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856132914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.856132914
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.3149174009
Short name T599
Test name
Test status
Simulation time 2740080033 ps
CPU time 36.3 seconds
Started Jul 03 05:04:05 PM PDT 24
Finished Jul 03 05:04:42 PM PDT 24
Peak memory 218900 kb
Host smart-06867e74-7608-4d05-a554-93c909526af1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149174009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.3149174009
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1612646615
Short name T186
Test name
Test status
Simulation time 252042037 ps
CPU time 4.14 seconds
Started Jul 03 05:04:05 PM PDT 24
Finished Jul 03 05:04:09 PM PDT 24
Peak memory 217668 kb
Host smart-a6ef9fe8-1b1c-492e-befa-4101fcb97187
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612646615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
612646615
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.737370067
Short name T559
Test name
Test status
Simulation time 289763415 ps
CPU time 9.07 seconds
Started Jul 03 05:03:54 PM PDT 24
Finished Jul 03 05:04:03 PM PDT 24
Peak memory 218168 kb
Host smart-12cf6214-d611-420b-9dd1-3ba00f80496d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737370067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
prog_failure.737370067
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1076983276
Short name T794
Test name
Test status
Simulation time 4345862092 ps
CPU time 20.34 seconds
Started Jul 03 05:04:04 PM PDT 24
Finished Jul 03 05:04:25 PM PDT 24
Peak memory 217752 kb
Host smart-7f105ecd-35fe-497c-8bcd-28f7475789a2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076983276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1076983276
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.1689426848
Short name T746
Test name
Test status
Simulation time 788825098 ps
CPU time 5.71 seconds
Started Jul 03 05:04:03 PM PDT 24
Finished Jul 03 05:04:10 PM PDT 24
Peak memory 217668 kb
Host smart-497aa945-a701-4fdf-9bd3-d46139ff7533
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689426848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
1689426848
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2198810563
Short name T490
Test name
Test status
Simulation time 11023141001 ps
CPU time 60.96 seconds
Started Jul 03 05:04:02 PM PDT 24
Finished Jul 03 05:05:03 PM PDT 24
Peak memory 282744 kb
Host smart-f4b21940-530c-4f12-940d-ffb1357f3600
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198810563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.2198810563
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.757826571
Short name T736
Test name
Test status
Simulation time 325610684 ps
CPU time 11.11 seconds
Started Jul 03 05:03:53 PM PDT 24
Finished Jul 03 05:04:10 PM PDT 24
Peak memory 226308 kb
Host smart-470d2e19-5551-4328-afb6-cd9dd19dca86
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757826571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_state_post_trans.757826571
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1366449549
Short name T320
Test name
Test status
Simulation time 26850092 ps
CPU time 1.83 seconds
Started Jul 03 05:03:56 PM PDT 24
Finished Jul 03 05:03:58 PM PDT 24
Peak memory 221880 kb
Host smart-847b82e6-85c0-47d4-925a-49d5e2633f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366449549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1366449549
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2171873836
Short name T548
Test name
Test status
Simulation time 848527109 ps
CPU time 15.78 seconds
Started Jul 03 05:03:57 PM PDT 24
Finished Jul 03 05:04:13 PM PDT 24
Peak memory 214672 kb
Host smart-8c24459e-6e66-41cd-8755-6b587498bccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171873836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2171873836
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.370525387
Short name T47
Test name
Test status
Simulation time 397914618 ps
CPU time 14.12 seconds
Started Jul 03 05:03:58 PM PDT 24
Finished Jul 03 05:04:12 PM PDT 24
Peak memory 218744 kb
Host smart-0ef70cb2-2075-492d-b26c-2f6fb109d5d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370525387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.370525387
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.1429914099
Short name T462
Test name
Test status
Simulation time 2711865700 ps
CPU time 15.3 seconds
Started Jul 03 05:04:05 PM PDT 24
Finished Jul 03 05:04:21 PM PDT 24
Peak memory 226008 kb
Host smart-e3b75de9-f6df-4714-8ab7-690e8a186fc7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429914099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.1429914099
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2740438949
Short name T687
Test name
Test status
Simulation time 2252034505 ps
CPU time 12.72 seconds
Started Jul 03 05:03:48 PM PDT 24
Finished Jul 03 05:04:02 PM PDT 24
Peak memory 218248 kb
Host smart-e2d0fc62-3f7f-4938-bf24-40d752dd5290
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740438949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
740438949
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.1124989877
Short name T353
Test name
Test status
Simulation time 321555628 ps
CPU time 8.57 seconds
Started Jul 03 05:03:50 PM PDT 24
Finished Jul 03 05:04:00 PM PDT 24
Peak memory 225928 kb
Host smart-6aea08f5-8b5d-4dfa-9c85-18fbf23319f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124989877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1124989877
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.2159356566
Short name T71
Test name
Test status
Simulation time 43641016 ps
CPU time 2.06 seconds
Started Jul 03 05:04:09 PM PDT 24
Finished Jul 03 05:04:12 PM PDT 24
Peak memory 214228 kb
Host smart-a1f872b7-0bce-4443-862b-074392c2376e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159356566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.2159356566
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.1573146805
Short name T396
Test name
Test status
Simulation time 225917551 ps
CPU time 21.2 seconds
Started Jul 03 05:04:04 PM PDT 24
Finished Jul 03 05:04:26 PM PDT 24
Peak memory 250912 kb
Host smart-0f9a8886-15c2-4b0f-9689-8c15105e8a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573146805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1573146805
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.616920718
Short name T578
Test name
Test status
Simulation time 76580601 ps
CPU time 3.65 seconds
Started Jul 03 05:04:02 PM PDT 24
Finished Jul 03 05:04:06 PM PDT 24
Peak memory 222284 kb
Host smart-574a9081-9844-4492-b353-f5c7cc1554bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616920718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.616920718
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.384670852
Short name T160
Test name
Test status
Simulation time 11746783415 ps
CPU time 117.64 seconds
Started Jul 03 05:04:11 PM PDT 24
Finished Jul 03 05:06:10 PM PDT 24
Peak memory 226088 kb
Host smart-a6743ea8-8d75-44e3-bd5b-c331ce6d64e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384670852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.384670852
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2015231683
Short name T348
Test name
Test status
Simulation time 33736819 ps
CPU time 0.88 seconds
Started Jul 03 05:03:48 PM PDT 24
Finished Jul 03 05:03:50 PM PDT 24
Peak memory 217696 kb
Host smart-554f64bd-7dff-4105-938a-ed710d9a9729
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015231683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2015231683
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.1217462687
Short name T283
Test name
Test status
Simulation time 27174820 ps
CPU time 1 seconds
Started Jul 03 05:04:06 PM PDT 24
Finished Jul 03 05:04:07 PM PDT 24
Peak memory 208932 kb
Host smart-6c17e14e-30ab-440d-84ad-8ef92b1996f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217462687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1217462687
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.4170023037
Short name T215
Test name
Test status
Simulation time 10878390 ps
CPU time 0.92 seconds
Started Jul 03 05:04:00 PM PDT 24
Finished Jul 03 05:04:01 PM PDT 24
Peak memory 208968 kb
Host smart-ff110fa9-95a4-491a-a640-2a43d802a09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170023037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.4170023037
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.3309554660
Short name T25
Test name
Test status
Simulation time 797814353 ps
CPU time 10.65 seconds
Started Jul 03 05:03:57 PM PDT 24
Finished Jul 03 05:04:08 PM PDT 24
Peak memory 218148 kb
Host smart-eb7bfeed-e69e-4d66-b1dd-896f7f1bb1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309554660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3309554660
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.2950317192
Short name T10
Test name
Test status
Simulation time 2233578841 ps
CPU time 13.76 seconds
Started Jul 03 05:03:53 PM PDT 24
Finished Jul 03 05:04:08 PM PDT 24
Peak memory 217424 kb
Host smart-62e647c0-7600-499c-9739-9692db195779
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950317192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.2950317192
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.1497902019
Short name T4
Test name
Test status
Simulation time 5297582829 ps
CPU time 35.65 seconds
Started Jul 03 05:03:58 PM PDT 24
Finished Jul 03 05:04:34 PM PDT 24
Peak memory 218640 kb
Host smart-f302d0d2-84e9-49f7-b896-e7ff122d8aaa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497902019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.1497902019
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.1670729220
Short name T409
Test name
Test status
Simulation time 7752232666 ps
CPU time 4.58 seconds
Started Jul 03 05:04:07 PM PDT 24
Finished Jul 03 05:04:12 PM PDT 24
Peak memory 217704 kb
Host smart-bb94fded-13f4-4446-822f-f39697e236a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670729220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.1
670729220
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.706746057
Short name T255
Test name
Test status
Simulation time 858928923 ps
CPU time 12.62 seconds
Started Jul 03 05:04:04 PM PDT 24
Finished Jul 03 05:04:17 PM PDT 24
Peak memory 218812 kb
Host smart-d58171b2-31ca-48f7-9e02-45b940384c92
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706746057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
prog_failure.706746057
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1797752031
Short name T677
Test name
Test status
Simulation time 1279846187 ps
CPU time 36.25 seconds
Started Jul 03 05:04:02 PM PDT 24
Finished Jul 03 05:04:39 PM PDT 24
Peak memory 217656 kb
Host smart-8214229c-c73f-4b14-85e5-c1c1b8858421
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797752031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.1797752031
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.580025028
Short name T83
Test name
Test status
Simulation time 333286642 ps
CPU time 6.09 seconds
Started Jul 03 05:03:50 PM PDT 24
Finished Jul 03 05:03:57 PM PDT 24
Peak memory 217632 kb
Host smart-b30550a0-fc39-4cb8-963a-639f25f44505
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580025028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.580025028
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.3309693925
Short name T281
Test name
Test status
Simulation time 3289736985 ps
CPU time 83.08 seconds
Started Jul 03 05:04:08 PM PDT 24
Finished Jul 03 05:05:32 PM PDT 24
Peak memory 283548 kb
Host smart-595c827a-3c17-4d32-be2e-e2858c51894b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309693925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.3309693925
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2216936673
Short name T811
Test name
Test status
Simulation time 745932532 ps
CPU time 17.79 seconds
Started Jul 03 05:04:00 PM PDT 24
Finished Jul 03 05:04:18 PM PDT 24
Peak memory 250940 kb
Host smart-63503fef-7f2a-4d97-9528-f6abc5d8b2f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216936673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2216936673
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.3304648077
Short name T403
Test name
Test status
Simulation time 216079387 ps
CPU time 2.4 seconds
Started Jul 03 05:04:12 PM PDT 24
Finished Jul 03 05:04:15 PM PDT 24
Peak memory 218140 kb
Host smart-263b4d1f-67d5-40df-a5f9-589d6cbb5e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304648077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.3304648077
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3763785756
Short name T331
Test name
Test status
Simulation time 1101893204 ps
CPU time 18.58 seconds
Started Jul 03 05:03:54 PM PDT 24
Finished Jul 03 05:04:13 PM PDT 24
Peak memory 214648 kb
Host smart-78c81515-0df9-4974-b25e-ee3353176327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763785756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3763785756
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2736276461
Short name T790
Test name
Test status
Simulation time 1642415079 ps
CPU time 12.65 seconds
Started Jul 03 05:04:14 PM PDT 24
Finished Jul 03 05:04:27 PM PDT 24
Peak memory 225920 kb
Host smart-0cefc6e5-9044-4b62-a430-5e86e5420e94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736276461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2736276461
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2109427248
Short name T843
Test name
Test status
Simulation time 670016130 ps
CPU time 13.84 seconds
Started Jul 03 05:04:05 PM PDT 24
Finished Jul 03 05:04:19 PM PDT 24
Peak memory 218164 kb
Host smart-c11f3088-5387-49a7-b9f3-9f38705cbd0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109427248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2
109427248
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2255796173
Short name T646
Test name
Test status
Simulation time 342912784 ps
CPU time 12.2 seconds
Started Jul 03 05:03:48 PM PDT 24
Finished Jul 03 05:04:01 PM PDT 24
Peak memory 218292 kb
Host smart-758212a7-8c75-4f99-8c53-5dd1384582fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255796173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2255796173
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2929845026
Short name T592
Test name
Test status
Simulation time 323269718 ps
CPU time 3.5 seconds
Started Jul 03 05:04:24 PM PDT 24
Finished Jul 03 05:04:29 PM PDT 24
Peak memory 217652 kb
Host smart-1cce56a0-166e-492a-aa0b-aab4ef76e7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929845026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2929845026
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.2031330258
Short name T249
Test name
Test status
Simulation time 196152104 ps
CPU time 27.15 seconds
Started Jul 03 05:04:09 PM PDT 24
Finished Jul 03 05:04:37 PM PDT 24
Peak memory 250908 kb
Host smart-6bf31732-4a2e-4034-af22-027708f79946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031330258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.2031330258
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.996057382
Short name T738
Test name
Test status
Simulation time 262325652 ps
CPU time 7.04 seconds
Started Jul 03 05:04:01 PM PDT 24
Finished Jul 03 05:04:08 PM PDT 24
Peak memory 250444 kb
Host smart-10c05c5b-968b-4565-b21c-9e9e1d873f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996057382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.996057382
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.2591840841
Short name T806
Test name
Test status
Simulation time 6890066461 ps
CPU time 219.39 seconds
Started Jul 03 05:03:53 PM PDT 24
Finished Jul 03 05:07:33 PM PDT 24
Peak memory 316524 kb
Host smart-316ef0fb-b6fc-45c0-ae9b-59eb1dae5542
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591840841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.2591840841
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.4266479933
Short name T149
Test name
Test status
Simulation time 58965670270 ps
CPU time 455.51 seconds
Started Jul 03 05:04:08 PM PDT 24
Finished Jul 03 05:11:45 PM PDT 24
Peak memory 283876 kb
Host smart-089a79bc-daa8-4009-bad1-e99ada82eebf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4266479933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.4266479933
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.717271424
Short name T316
Test name
Test status
Simulation time 33957692 ps
CPU time 0.92 seconds
Started Jul 03 05:04:04 PM PDT 24
Finished Jul 03 05:04:05 PM PDT 24
Peak memory 211832 kb
Host smart-847053d3-4b15-48cf-b273-244a66432529
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717271424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.717271424
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1292470225
Short name T695
Test name
Test status
Simulation time 15002096 ps
CPU time 0.93 seconds
Started Jul 03 05:04:13 PM PDT 24
Finished Jul 03 05:04:14 PM PDT 24
Peak memory 208900 kb
Host smart-c7148158-43c5-45fb-9bf5-c1a175f6e857
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292470225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1292470225
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.222382279
Short name T381
Test name
Test status
Simulation time 631930374 ps
CPU time 11.48 seconds
Started Jul 03 05:04:06 PM PDT 24
Finished Jul 03 05:04:18 PM PDT 24
Peak memory 218128 kb
Host smart-2bfbef4d-0c08-4d29-8cc9-f1c91c5af307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222382279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.222382279
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.3223196675
Short name T621
Test name
Test status
Simulation time 28670131473 ps
CPU time 12.16 seconds
Started Jul 03 05:03:56 PM PDT 24
Finished Jul 03 05:04:08 PM PDT 24
Peak memory 217712 kb
Host smart-0fa089b7-a2b2-46ba-869f-6747d5620324
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223196675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3223196675
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1162303932
Short name T433
Test name
Test status
Simulation time 2336369098 ps
CPU time 20.99 seconds
Started Jul 03 05:04:16 PM PDT 24
Finished Jul 03 05:04:38 PM PDT 24
Peak memory 218164 kb
Host smart-99d2652b-d36b-4c95-a45d-b2594e6caa25
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162303932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1162303932
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2018172866
Short name T814
Test name
Test status
Simulation time 382059389 ps
CPU time 4.83 seconds
Started Jul 03 05:04:18 PM PDT 24
Finished Jul 03 05:04:24 PM PDT 24
Peak memory 217720 kb
Host smart-a278ff93-fbdb-4f9a-b982-d91fa68ca078
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018172866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
018172866
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.940868659
Short name T587
Test name
Test status
Simulation time 973287662 ps
CPU time 14.92 seconds
Started Jul 03 05:03:57 PM PDT 24
Finished Jul 03 05:04:12 PM PDT 24
Peak memory 224288 kb
Host smart-5f51be8c-a25e-4ab8-87ef-812d48ddc474
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940868659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
prog_failure.940868659
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.247324501
Short name T388
Test name
Test status
Simulation time 751295352 ps
CPU time 20.73 seconds
Started Jul 03 05:04:17 PM PDT 24
Finished Jul 03 05:04:40 PM PDT 24
Peak memory 217652 kb
Host smart-71730726-925e-4744-adcb-0e0f5c05b3d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247324501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_regwen_during_op.247324501
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1136558060
Short name T833
Test name
Test status
Simulation time 322429126 ps
CPU time 2.88 seconds
Started Jul 03 05:04:07 PM PDT 24
Finished Jul 03 05:04:10 PM PDT 24
Peak memory 217512 kb
Host smart-5695724c-e388-49db-af34-5c713d2d3b71
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136558060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
1136558060
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.1433624825
Short name T494
Test name
Test status
Simulation time 1907013930 ps
CPU time 46.16 seconds
Started Jul 03 05:04:12 PM PDT 24
Finished Jul 03 05:04:59 PM PDT 24
Peak memory 280204 kb
Host smart-da13d26b-7feb-4d41-976e-a95d45f92797
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433624825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.1433624825
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3220360351
Short name T295
Test name
Test status
Simulation time 331436984 ps
CPU time 14.93 seconds
Started Jul 03 05:04:07 PM PDT 24
Finished Jul 03 05:04:23 PM PDT 24
Peak memory 250232 kb
Host smart-0bb6d138-b228-453f-86ab-383237024fb1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220360351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.3220360351
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.1753571419
Short name T544
Test name
Test status
Simulation time 127244278 ps
CPU time 1.83 seconds
Started Jul 03 05:04:07 PM PDT 24
Finished Jul 03 05:04:09 PM PDT 24
Peak memory 218148 kb
Host smart-1e714509-6cd7-4083-9c85-040937f7bbf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753571419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1753571419
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.837030894
Short name T170
Test name
Test status
Simulation time 519588438 ps
CPU time 13.36 seconds
Started Jul 03 05:04:01 PM PDT 24
Finished Jul 03 05:04:15 PM PDT 24
Peak memory 214544 kb
Host smart-ae2551cf-2395-4b34-a2db-7d1679840282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837030894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.837030894
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.1136951114
Short name T325
Test name
Test status
Simulation time 6486735164 ps
CPU time 12.88 seconds
Started Jul 03 05:04:16 PM PDT 24
Finished Jul 03 05:04:30 PM PDT 24
Peak memory 226044 kb
Host smart-8719683c-2c3d-49f0-a1be-99e15d8e2cc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136951114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.1136951114
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.492073925
Short name T279
Test name
Test status
Simulation time 201247673 ps
CPU time 7.49 seconds
Started Jul 03 05:04:15 PM PDT 24
Finished Jul 03 05:04:23 PM PDT 24
Peak memory 226044 kb
Host smart-96e20ec4-c8c4-4efb-8ffd-024d9bf157c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492073925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_dig
est.492073925
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.2620839603
Short name T601
Test name
Test status
Simulation time 493005933 ps
CPU time 10.32 seconds
Started Jul 03 05:03:57 PM PDT 24
Finished Jul 03 05:04:08 PM PDT 24
Peak memory 218192 kb
Host smart-7a8eabe5-da95-4513-8958-d83c65fdaee9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620839603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.2
620839603
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.2729094177
Short name T517
Test name
Test status
Simulation time 1768290935 ps
CPU time 9.86 seconds
Started Jul 03 05:04:01 PM PDT 24
Finished Jul 03 05:04:11 PM PDT 24
Peak memory 225948 kb
Host smart-5e7ea3cf-e9f3-4c5a-9eca-9845eadf2fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729094177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2729094177
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.3325338192
Short name T248
Test name
Test status
Simulation time 20745454 ps
CPU time 1.53 seconds
Started Jul 03 05:04:06 PM PDT 24
Finished Jul 03 05:04:08 PM PDT 24
Peak memory 213608 kb
Host smart-24d1ab9a-087a-47c7-b5ae-28158fcdc033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325338192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3325338192
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.946833947
Short name T419
Test name
Test status
Simulation time 1214878407 ps
CPU time 27.12 seconds
Started Jul 03 05:04:05 PM PDT 24
Finished Jul 03 05:04:33 PM PDT 24
Peak memory 250880 kb
Host smart-6c5d8c0b-6ea2-49cc-bde3-67bea8f15bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946833947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.946833947
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.2930354967
Short name T477
Test name
Test status
Simulation time 76572532 ps
CPU time 6.42 seconds
Started Jul 03 05:04:05 PM PDT 24
Finished Jul 03 05:04:12 PM PDT 24
Peak memory 247304 kb
Host smart-613da704-09a2-4111-b755-38421b5fe7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930354967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2930354967
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.1278411854
Short name T537
Test name
Test status
Simulation time 697040620 ps
CPU time 46.48 seconds
Started Jul 03 05:03:55 PM PDT 24
Finished Jul 03 05:04:42 PM PDT 24
Peak memory 250732 kb
Host smart-2a0adc75-baae-453d-bf79-57d09fbcc7e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278411854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.1278411854
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.1443224859
Short name T172
Test name
Test status
Simulation time 11781288881 ps
CPU time 235.16 seconds
Started Jul 03 05:04:06 PM PDT 24
Finished Jul 03 05:08:01 PM PDT 24
Peak memory 283108 kb
Host smart-d2cdd1fc-e669-4871-a39e-6b4e5ccc0074
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1443224859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.1443224859
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1501680896
Short name T710
Test name
Test status
Simulation time 21976049 ps
CPU time 0.98 seconds
Started Jul 03 05:04:13 PM PDT 24
Finished Jul 03 05:04:15 PM PDT 24
Peak memory 211800 kb
Host smart-ea834848-d793-43b2-81db-c8cef7600b6e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501680896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.1501680896
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3433296808
Short name T579
Test name
Test status
Simulation time 69988186 ps
CPU time 0.83 seconds
Started Jul 03 05:04:14 PM PDT 24
Finished Jul 03 05:04:15 PM PDT 24
Peak memory 209012 kb
Host smart-93e69b70-071f-448f-ab3b-093b2266d79f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433296808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3433296808
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.3554653690
Short name T260
Test name
Test status
Simulation time 1487932749 ps
CPU time 8.35 seconds
Started Jul 03 05:04:21 PM PDT 24
Finished Jul 03 05:04:30 PM PDT 24
Peak memory 225948 kb
Host smart-8f0d583c-32fe-4af1-872b-8c066c08a0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554653690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.3554653690
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3167712139
Short name T783
Test name
Test status
Simulation time 386225301 ps
CPU time 3.02 seconds
Started Jul 03 05:04:19 PM PDT 24
Finished Jul 03 05:04:24 PM PDT 24
Peak memory 217052 kb
Host smart-4d6bf2ce-6d4a-458f-ac2a-837768602a25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167712139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3167712139
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1772131065
Short name T620
Test name
Test status
Simulation time 11161882669 ps
CPU time 36 seconds
Started Jul 03 05:04:17 PM PDT 24
Finished Jul 03 05:04:53 PM PDT 24
Peak memory 218880 kb
Host smart-4a124e61-d5eb-40e7-911d-06b348e2c81c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772131065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1772131065
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.5065504
Short name T789
Test name
Test status
Simulation time 107880682 ps
CPU time 3.64 seconds
Started Jul 03 05:04:18 PM PDT 24
Finished Jul 03 05:04:23 PM PDT 24
Peak memory 217648 kb
Host smart-ce24af2c-559e-4182-bb41-5706c6dcb434
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5065504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.5065504
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.129390030
Short name T760
Test name
Test status
Simulation time 1730841304 ps
CPU time 12.59 seconds
Started Jul 03 05:04:11 PM PDT 24
Finished Jul 03 05:04:24 PM PDT 24
Peak memory 223120 kb
Host smart-2bb15b82-b04d-414d-9dc0-fc8a0e619601
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129390030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
prog_failure.129390030
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3586681634
Short name T303
Test name
Test status
Simulation time 1078270140 ps
CPU time 16.34 seconds
Started Jul 03 05:04:17 PM PDT 24
Finished Jul 03 05:04:34 PM PDT 24
Peak memory 217676 kb
Host smart-01b40a0a-002f-43bd-9cb9-2d41913e26d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586681634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3586681634
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.1759198581
Short name T70
Test name
Test status
Simulation time 608836529 ps
CPU time 5.2 seconds
Started Jul 03 05:04:18 PM PDT 24
Finished Jul 03 05:04:24 PM PDT 24
Peak memory 217600 kb
Host smart-85957b93-394f-4795-82ae-829d59cf2f73
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759198581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
1759198581
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.923390033
Short name T254
Test name
Test status
Simulation time 3590286788 ps
CPU time 70.96 seconds
Started Jul 03 05:04:17 PM PDT 24
Finished Jul 03 05:05:29 PM PDT 24
Peak memory 283712 kb
Host smart-f0d1d4ff-62bc-456f-9751-c398a750f450
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923390033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_state_failure.923390033
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.4294592065
Short name T247
Test name
Test status
Simulation time 1649021295 ps
CPU time 10.27 seconds
Started Jul 03 05:04:04 PM PDT 24
Finished Jul 03 05:04:15 PM PDT 24
Peak memory 247368 kb
Host smart-66230eb2-dc14-48b9-9af2-8fadce0510a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294592065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.4294592065
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.684072868
Short name T678
Test name
Test status
Simulation time 296687497 ps
CPU time 2.44 seconds
Started Jul 03 05:04:07 PM PDT 24
Finished Jul 03 05:04:10 PM PDT 24
Peak memory 218020 kb
Host smart-f02c128e-1fe1-406a-b3bf-69364ebf1b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684072868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.684072868
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1930190567
Short name T89
Test name
Test status
Simulation time 6811784493 ps
CPU time 12.34 seconds
Started Jul 03 05:04:20 PM PDT 24
Finished Jul 03 05:04:33 PM PDT 24
Peak memory 217728 kb
Host smart-e16ec9f8-fe45-4932-bfaf-baa826d35740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930190567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1930190567
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.995804480
Short name T696
Test name
Test status
Simulation time 5162486894 ps
CPU time 10.56 seconds
Started Jul 03 05:04:01 PM PDT 24
Finished Jul 03 05:04:12 PM PDT 24
Peak memory 225988 kb
Host smart-5d6aa479-955a-48e2-a442-2cabfcced1dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995804480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dig
est.995804480
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.2324011448
Short name T514
Test name
Test status
Simulation time 426988241 ps
CPU time 11.77 seconds
Started Jul 03 05:04:22 PM PDT 24
Finished Jul 03 05:04:35 PM PDT 24
Peak memory 225984 kb
Host smart-de048c38-c88e-4ed1-8c8e-2bf86a11cd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324011448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2324011448
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1703082188
Short name T502
Test name
Test status
Simulation time 157033034 ps
CPU time 4.75 seconds
Started Jul 03 05:04:20 PM PDT 24
Finished Jul 03 05:04:26 PM PDT 24
Peak memory 217708 kb
Host smart-92c57c48-7669-485e-aa7b-b2559284a9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703082188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1703082188
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.517426712
Short name T452
Test name
Test status
Simulation time 986503353 ps
CPU time 34.03 seconds
Started Jul 03 05:04:22 PM PDT 24
Finished Jul 03 05:04:58 PM PDT 24
Peak memory 247496 kb
Host smart-3f490373-6ad8-44fc-9258-35a0c265df5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517426712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.517426712
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.721445039
Short name T815
Test name
Test status
Simulation time 67330874 ps
CPU time 6.01 seconds
Started Jul 03 05:04:13 PM PDT 24
Finished Jul 03 05:04:20 PM PDT 24
Peak memory 246936 kb
Host smart-5c529517-5faa-4a1c-9007-f04456c94a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721445039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.721445039
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.498546357
Short name T101
Test name
Test status
Simulation time 2151467075 ps
CPU time 55.14 seconds
Started Jul 03 05:04:20 PM PDT 24
Finished Jul 03 05:05:16 PM PDT 24
Peak memory 275544 kb
Host smart-cc88c978-b504-4b54-a1ef-ba01dbe87f71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498546357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.498546357
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3247952508
Short name T684
Test name
Test status
Simulation time 12858434 ps
CPU time 1.08 seconds
Started Jul 03 05:04:20 PM PDT 24
Finished Jul 03 05:04:22 PM PDT 24
Peak memory 212892 kb
Host smart-fbad5238-e4e3-4190-8dd4-2aacf01d8699
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247952508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.3247952508
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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