Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1371301	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1569909

1

T1

2338

T2

6

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2632211	1			T1	3576		T2	10		T3	2
values[0x0]	153798	1			T1	358		T2	4		T3	6
values[0x1]	155201	1			T1	354		T2	4		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1088149	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1853061

1

T1

2724

T2

9

T3

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13235	1			T6	5		T9	3		T19	1
valid_sources[0x01]	10099	1			T13	17		T9	1		T19	1
valid_sources[0x02]	12277	1			T6	3		T9	2		T18	7
valid_sources[0x03]	10986	1			T16	3		T9	2		T19	1
valid_sources[0x04]	10624	1			T6	1		T16	2		T9	3
valid_sources[0x05]	10113	1			T13	17		T9	4		T14	5
valid_sources[0x06]	10436	1			T6	2		T16	2		T18	5
valid_sources[0x07]	9824	1			T6	6		T13	17		T14	6
valid_sources[0x08]	9692	1			T6	2		T16	2		T19	2
valid_sources[0x09]	10920	1			T16	5		T9	3		T18	1
valid_sources[0x0a]	11031	1			T9	1		T19	4		T14	9
valid_sources[0x0b]	11535	1			T5	23		T16	4		T14	4
valid_sources[0x0c]	12482	1			T19	1		T14	1		T15	665
valid_sources[0x0d]	25471	1			T6	2		T11	738		T9	2
valid_sources[0x0e]	9559	1			T9	2		T18	2		T19	2
valid_sources[0x0f]	9622	1			T6	2		T18	1		T19	1
valid_sources[0x10]	10189	1			T6	4		T9	2		T19	1
valid_sources[0x11]	11630	1			T6	1		T5	27		T16	3
valid_sources[0x12]	30007	1			T16	3		T9	1		T14	3
valid_sources[0x13]	9708	1			T9	2		T14	2		T15	330
valid_sources[0x14]	10642	1			T6	2		T9	1		T19	1
valid_sources[0x15]	10706	1			T3	1		T16	3		T9	1
valid_sources[0x16]	11142	1			T6	1		T14	2		T15	373
valid_sources[0x17]	25715	1			T16	2		T9	1		T14	2
valid_sources[0x18]	10144	1			T9	1		T19	5		T14	7
valid_sources[0x19]	10841	1			T6	7		T9	1		T14	3
valid_sources[0x1a]	12530	1			T5	8		T9	2		T19	7
valid_sources[0x1b]	10517	1			T6	3		T9	1		T19	1
valid_sources[0x1c]	10913	1			T16	1		T9	4		T14	1
valid_sources[0x1d]	10438	1			T16	5		T9	3		T19	2
valid_sources[0x1e]	10981	1			T6	1		T14	1		T55	5
valid_sources[0x1f]	10203	1			T9	3		T19	2		T14	7
valid_sources[0x20]	12042	1			T5	2		T16	1		T9	3
valid_sources[0x21]	31291	1			T57	1		T9	1		T19	2
valid_sources[0x22]	9657	1			T6	2		T5	8		T14	1
valid_sources[0x23]	9839	1			T6	1		T16	1		T9	1
valid_sources[0x24]	10408	1			T2	1		T9	2		T19	2
valid_sources[0x25]	13188	1			T16	5		T24	4		T9	6
valid_sources[0x26]	10007	1			T16	1		T24	1		T57	1
valid_sources[0x27]	10548	1			T9	2		T14	8		T15	453
valid_sources[0x28]	9810	1			T14	2		T15	32		T83	3
valid_sources[0x29]	10002	1			T5	15		T9	1		T19	3
valid_sources[0x2a]	16177	1			T16	1		T9	3		T19	2
valid_sources[0x2b]	10577	1			T9	1		T14	3		T55	1
valid_sources[0x2c]	11021	1			T6	1		T9	3		T14	2
valid_sources[0x2d]	9707	1			T16	1		T9	1		T55	6
valid_sources[0x2e]	10373	1			T16	2		T14	4		T55	2
valid_sources[0x2f]	11718	1			T16	3		T19	2		T14	6
valid_sources[0x30]	10672	1			T2	1		T16	2		T9	2
valid_sources[0x31]	11026	1			T5	3		T9	2		T14	2
valid_sources[0x32]	10150	1			T2	1		T18	1		T19	1
valid_sources[0x33]	9703	1			T6	3		T5	17		T9	1
valid_sources[0x34]	10792	1			T5	2		T16	1		T9	1
valid_sources[0x35]	10159	1			T6	1		T57	1		T19	1
valid_sources[0x36]	10430	1			T6	2		T19	2		T14	4
valid_sources[0x37]	10634	1			T9	1		T18	1		T14	2
valid_sources[0x38]	15692	1			T13	17		T9	1		T19	1
valid_sources[0x39]	10653	1			T6	1		T16	3		T9	2
valid_sources[0x3a]	13724	1			T9	2		T14	5		T15	186
valid_sources[0x3b]	36426	1			T9	1		T14	3		T15	189
valid_sources[0x3c]	10170	1			T6	2		T5	2		T9	3
valid_sources[0x3d]	9956	1			T6	3		T14	3		T82	1
valid_sources[0x3e]	11194	1			T6	3		T9	1		T19	1
valid_sources[0x3f]	9950	1			T5	1		T19	2		T14	2
valid_sources[0x40]	9918	1			T16	2		T14	4		T15	462
valid_sources[0x41]	11248	1			T3	1		T6	6		T5	9
valid_sources[0x42]	10127	1			T6	5		T5	8		T18	2
valid_sources[0x43]	12263	1			T6	4		T5	1		T16	1
valid_sources[0x44]	12687	1			T9	3		T19	4		T14	4
valid_sources[0x45]	11204	1			T6	3		T16	2		T24	4
valid_sources[0x46]	10681	1			T16	3		T9	2		T18	4
valid_sources[0x47]	11263	1			T6	4		T9	1		T19	1
valid_sources[0x48]	10294	1			T9	2		T14	1		T55	3
valid_sources[0x49]	17595	1			T9	1		T18	2		T19	1
valid_sources[0x4a]	11070	1			T5	10		T23	2		T9	2
valid_sources[0x4b]	11439	1			T16	8		T9	5		T14	5
valid_sources[0x4c]	9588	1			T6	3		T9	3		T19	1
valid_sources[0x4d]	10841	1			T6	7		T9	5		T19	2
valid_sources[0x4e]	11189	1			T2	1		T6	2		T9	1
valid_sources[0x4f]	11207	1			T6	3		T16	3		T14	5
valid_sources[0x50]	12581	1			T5	22		T16	3		T9	4
valid_sources[0x51]	10917	1			T9	2		T55	3		T15	1022
valid_sources[0x52]	10402	1			T19	1		T14	7		T55	1
valid_sources[0x53]	10324	1			T6	1		T13	17		T9	1
valid_sources[0x54]	11567	1			T3	1		T6	1		T16	1
valid_sources[0x55]	10513	1			T6	1		T9	2		T18	3
valid_sources[0x56]	9881	1			T16	1		T9	1		T14	4
valid_sources[0x57]	11060	1			T16	3		T9	2		T19	2
valid_sources[0x58]	9870	1			T9	2		T19	2		T14	3
valid_sources[0x59]	9962	1			T9	3		T19	1		T14	5
valid_sources[0x5a]	10071	1			T9	4		T19	1		T14	1
valid_sources[0x5b]	10122	1			T16	1		T19	1		T14	3
valid_sources[0x5c]	12600	1			T16	4		T9	1		T14	3
valid_sources[0x5d]	32283	1			T2	1		T9	1		T19	2
valid_sources[0x5e]	17388	1			T9	1		T14	1		T22	7828
valid_sources[0x5f]	11752	1			T6	3		T18	1		T19	1
valid_sources[0x60]	11090	1			T5	5		T16	4		T9	3
valid_sources[0x61]	12237	1			T5	17		T16	7		T9	1
valid_sources[0x62]	10600	1			T6	5		T9	2		T19	1
valid_sources[0x63]	11515	1			T5	8		T19	5		T14	3
valid_sources[0x64]	10194	1			T9	1		T19	5		T14	2
valid_sources[0x65]	10588	1			T18	1		T19	2		T14	2
valid_sources[0x66]	9959	1			T6	2		T5	9		T16	1
valid_sources[0x67]	11889	1			T19	1		T14	4		T55	3
valid_sources[0x68]	10442	1			T5	17		T9	3		T14	2
valid_sources[0x69]	10553	1			T16	1		T9	3		T14	3
valid_sources[0x6a]	10631	1			T6	3		T9	1		T19	2
valid_sources[0x6b]	10218	1			T16	3		T14	6		T55	1
valid_sources[0x6c]	10017	1			T6	2		T16	5		T14	5
valid_sources[0x6d]	9933	1			T16	5		T9	4		T19	2
valid_sources[0x6e]	10566	1			T14	2		T55	2		T15	333
valid_sources[0x6f]	9762	1			T16	7		T24	9		T19	1
valid_sources[0x70]	19355	1			T2	1		T57	1		T9	2
valid_sources[0x71]	10263	1			T6	6		T9	3		T18	3
valid_sources[0x72]	10369	1			T6	2		T16	14		T14	5
valid_sources[0x73]	11897	1			T9	2		T19	1		T14	2
valid_sources[0x74]	10740	1			T24	4		T9	1		T19	1
valid_sources[0x75]	9991	1			T9	2		T19	3		T14	4
valid_sources[0x76]	10465	1			T6	10		T9	1		T14	1
valid_sources[0x77]	10094	1			T6	1		T16	1		T9	2
valid_sources[0x78]	11551	1			T9	1		T14	2		T55	2
valid_sources[0x79]	10106	1			T6	8		T16	15		T9	1
valid_sources[0x7a]	9819	1			T9	2		T19	1		T14	1
valid_sources[0x7b]	10415	1			T16	6		T9	2		T14	3
valid_sources[0x7c]	11362	1			T16	4		T9	1		T19	1
valid_sources[0x7d]	10583	1			T9	2		T14	1		T55	3
valid_sources[0x7e]	9543	1			T3	2		T5	8		T9	3
valid_sources[0x7f]	10392	1			T14	3		T15	156		T83	7
valid_sources[0x80]	10106	1			T6	1		T16	3		T9	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1303902

1

T1

1732

T4

1108

T6

71

values[0x0]

all_enables

biggest_size

133331

1

T1

308

T2

4

T3

4

values[0x1]

all_enables

biggest_size

132676

1

T1

298

T2

2

T3

2