Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	93318107	14208	0	0
claim_transition_if_regwen_rd_A	93318107	2302	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93318107	14208	0	0
T25	36572	0	0	0
T26	40649	0	0	0
T39	181118	11	0	0
T60	141626	0	0	0
T87	0	8	0	0
T89	0	6	0	0
T107	0	2	0	0
T112	0	6	0	0
T138	0	10	0	0
T139	0	10	0	0
T140	0	2	0	0
T141	0	4	0	0
T142	0	11	0	0
T143	21067	0	0	0
T144	94424	0	0	0
T145	124785	0	0	0
T146	20102	0	0	0
T147	9438	0	0	0
T148	3010	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	93318107	2302	0	0
T109	0	49	0	0
T118	0	8	0	0
T122	0	72	0	0
T124	0	5	0	0
T141	275986	14	0	0
T149	0	5	0	0
T150	0	17	0	0
T151	0	39	0	0
T152	0	71	0	0
T153	0	284	0	0
T154	15119	0	0	0
T155	86322	0	0	0
T156	31101	0	0	0
T157	26365	0	0	0
T158	23520	0	0	0
T159	90856	0	0	0
T160	25832	0	0	0
T161	228956	0	0	0
T162	1941	0	0	0