Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1744771	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1960197

1

T1

1075

T2

413

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3368034	1			T1	846		T2	353		T3	6
values[0x0]	168023	1			T1	369		T2	145		T3	5
values[0x1]	168911	1			T1	375		T2	167		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1386332	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2318636

1

T1

1194

T2

474

T3

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10161	1			T1	9		T2	2		T4	1
valid_sources[0x01]	56181	1			T1	6		T11	5		T6	1
valid_sources[0x02]	10696	1			T1	4		T2	3		T11	1
valid_sources[0x03]	9887	1			T1	7		T2	1		T5	1
valid_sources[0x04]	10489	1			T1	15		T2	2		T11	2
valid_sources[0x05]	10340	1			T1	7		T2	5		T4	2
valid_sources[0x06]	10517	1			T1	5		T2	2		T4	1
valid_sources[0x07]	10242	1			T1	6		T4	2		T5	4
valid_sources[0x08]	10528	1			T1	5		T2	2		T11	6
valid_sources[0x09]	10609	1			T1	8		T11	7		T6	1
valid_sources[0x0a]	192053	1			T1	2		T2	2		T11	2
valid_sources[0x0b]	10609	1			T1	6		T2	4		T11	8
valid_sources[0x0c]	10092	1			T1	7		T2	3		T4	4
valid_sources[0x0d]	9672	1			T1	6		T2	1		T11	2
valid_sources[0x0e]	10116	1			T1	4		T2	3		T11	1
valid_sources[0x0f]	9905	1			T1	4		T2	3		T4	1
valid_sources[0x10]	11553	1			T1	3		T11	4		T19	2
valid_sources[0x11]	9933	1			T1	11		T2	4		T11	3
valid_sources[0x12]	10356	1			T1	4		T2	5		T11	2
valid_sources[0x13]	12162	1			T1	9		T2	3		T4	4
valid_sources[0x14]	10398	1			T1	4		T2	1		T4	5
valid_sources[0x15]	11313	1			T1	2		T2	4		T11	10
valid_sources[0x16]	10476	1			T1	3		T2	2		T5	2
valid_sources[0x17]	12310	1			T1	13		T2	2		T11	1
valid_sources[0x18]	56010	1			T1	7		T2	2		T11	3
valid_sources[0x19]	11814	1			T1	4		T2	1		T11	1
valid_sources[0x1a]	12606	1			T1	5		T11	1		T6	4
valid_sources[0x1b]	10234	1			T1	5		T2	1		T4	1
valid_sources[0x1c]	11015	1			T1	5		T2	2		T4	1
valid_sources[0x1d]	10037	1			T1	4		T2	7		T11	7
valid_sources[0x1e]	12751	1			T1	8		T2	4		T11	3
valid_sources[0x1f]	10210	1			T1	5		T2	1		T4	3
valid_sources[0x20]	12646	1			T1	9		T2	5		T17	7
valid_sources[0x21]	15659	1			T1	11		T2	2		T11	5
valid_sources[0x22]	10287	1			T1	4		T2	2		T11	3
valid_sources[0x23]	9979	1			T1	6		T11	4		T6	1
valid_sources[0x24]	10356	1			T1	12		T2	2		T11	5
valid_sources[0x25]	10213	1			T1	12		T2	3		T5	2
valid_sources[0x26]	10227	1			T1	8		T4	2		T11	2
valid_sources[0x27]	9813	1			T1	6		T2	1		T11	3
valid_sources[0x28]	10730	1			T1	1		T2	1		T11	3
valid_sources[0x29]	10452	1			T1	3		T2	5		T11	5
valid_sources[0x2a]	10274	1			T1	7		T2	1		T4	2
valid_sources[0x2b]	11584	1			T1	8		T2	6		T11	4
valid_sources[0x2c]	12132	1			T1	7		T2	6		T11	4
valid_sources[0x2d]	10332	1			T1	6		T2	2		T11	1
valid_sources[0x2e]	10166	1			T1	4		T2	1		T4	1
valid_sources[0x2f]	9986	1			T1	5		T2	4		T11	1
valid_sources[0x30]	10476	1			T1	7		T2	1		T4	1
valid_sources[0x31]	10432	1			T1	3		T2	2		T4	1
valid_sources[0x32]	10537	1			T1	2		T2	4		T11	5
valid_sources[0x33]	10370	1			T1	7		T2	1		T11	2
valid_sources[0x34]	10290	1			T1	5		T2	4		T4	1
valid_sources[0x35]	10579	1			T1	8		T2	5		T11	10
valid_sources[0x36]	10146	1			T1	4		T2	3		T11	1
valid_sources[0x37]	57411	1			T1	11		T2	2		T3	2
valid_sources[0x38]	12453	1			T1	7		T2	1		T5	6
valid_sources[0x39]	9950	1			T1	9		T2	5		T4	2
valid_sources[0x3a]	9980	1			T1	4		T2	2		T11	5
valid_sources[0x3b]	12528	1			T1	6		T2	3		T4	1
valid_sources[0x3c]	11647	1			T1	3		T2	4		T11	2
valid_sources[0x3d]	11444	1			T1	1		T2	2		T5	1
valid_sources[0x3e]	11490	1			T1	6		T2	3		T4	1
valid_sources[0x3f]	11989	1			T1	4		T2	2		T11	8
valid_sources[0x40]	9973	1			T1	6		T2	2		T11	3
valid_sources[0x41]	10620	1			T1	11		T2	2		T11	4
valid_sources[0x42]	10438	1			T1	12		T2	3		T4	1
valid_sources[0x43]	12525	1			T1	8		T2	1		T4	1
valid_sources[0x44]	10384	1			T1	6		T5	2		T11	4
valid_sources[0x45]	10639	1			T1	6		T2	3		T11	3
valid_sources[0x46]	10502	1			T1	5		T2	5		T11	8
valid_sources[0x47]	9869	1			T1	4		T2	3		T4	1
valid_sources[0x48]	14648	1			T1	1		T2	5		T5	1
valid_sources[0x49]	17264	1			T1	6		T2	2		T11	3
valid_sources[0x4a]	10532	1			T1	6		T2	2		T4	4
valid_sources[0x4b]	17254	1			T1	9		T2	2		T4	1
valid_sources[0x4c]	10024	1			T1	6		T2	2		T11	4
valid_sources[0x4d]	10770	1			T1	3		T2	2		T11	3
valid_sources[0x4e]	9962	1			T1	5		T2	1		T4	1
valid_sources[0x4f]	10832	1			T1	5		T2	5		T11	7
valid_sources[0x50]	10980	1			T1	7		T2	2		T4	1
valid_sources[0x51]	10006	1			T1	4		T11	3		T19	3
valid_sources[0x52]	9924	1			T1	5		T4	1		T11	3
valid_sources[0x53]	10029	1			T1	8		T2	4		T4	4
valid_sources[0x54]	10204	1			T1	6		T2	1		T11	3
valid_sources[0x55]	10685	1			T1	5		T2	1		T4	1
valid_sources[0x56]	173710	1			T1	2		T2	4		T11	3
valid_sources[0x57]	9965	1			T1	11		T2	4		T4	5
valid_sources[0x58]	11741	1			T1	8		T2	4		T11	4
valid_sources[0x59]	10409	1			T1	6		T2	4		T4	2
valid_sources[0x5a]	11851	1			T1	8		T2	1		T11	4
valid_sources[0x5b]	10032	1			T1	5		T2	1		T11	5
valid_sources[0x5c]	11021	1			T1	7		T2	4		T4	2
valid_sources[0x5d]	11927	1			T1	4		T2	3		T4	1
valid_sources[0x5e]	10163	1			T1	9		T2	2		T5	4
valid_sources[0x5f]	11089	1			T1	10		T2	6		T4	1
valid_sources[0x60]	11244	1			T1	5		T2	3		T11	3
valid_sources[0x61]	10486	1			T1	3		T2	3		T4	1
valid_sources[0x62]	10138	1			T1	6		T2	3		T19	2
valid_sources[0x63]	10132	1			T1	5		T2	2		T4	1
valid_sources[0x64]	10371	1			T1	5		T2	3		T5	1
valid_sources[0x65]	10428	1			T1	4		T2	1		T11	8
valid_sources[0x66]	10274	1			T1	7		T2	1		T4	1
valid_sources[0x67]	10259	1			T1	7		T2	5		T4	1
valid_sources[0x68]	10009	1			T1	9		T2	3		T4	1
valid_sources[0x69]	10778	1			T1	7		T4	1		T5	3
valid_sources[0x6a]	10227	1			T1	7		T2	2		T11	4
valid_sources[0x6b]	11632	1			T1	4		T2	1		T11	3
valid_sources[0x6c]	10919	1			T1	5		T2	5		T11	5
valid_sources[0x6d]	16385	1			T1	9		T2	3		T4	2
valid_sources[0x6e]	11664	1			T1	11		T2	4		T4	1
valid_sources[0x6f]	12575	1			T1	9		T2	1		T4	2
valid_sources[0x70]	29607	1			T1	10		T2	3		T4	1
valid_sources[0x71]	56922	1			T1	1		T4	3		T11	3
valid_sources[0x72]	11007	1			T1	4		T2	2		T4	1
valid_sources[0x73]	9724	1			T1	3		T2	5		T4	1
valid_sources[0x74]	10142	1			T1	5		T2	6		T11	3
valid_sources[0x75]	10899	1			T1	5		T2	1		T11	4
valid_sources[0x76]	10366	1			T1	5		T2	3		T11	2
valid_sources[0x77]	16818	1			T1	5		T2	3		T4	2
valid_sources[0x78]	11741	1			T1	3		T2	2		T4	1
valid_sources[0x79]	10250	1			T1	7		T2	5		T6	2
valid_sources[0x7a]	9467	1			T1	8		T2	2		T4	1
valid_sources[0x7b]	9955	1			T1	7		T2	4		T3	12
valid_sources[0x7c]	10482	1			T1	5		T2	6		T4	1
valid_sources[0x7d]	10629	1			T1	4		T2	5		T6	5
valid_sources[0x7e]	10233	1			T1	3		T2	7		T4	3
valid_sources[0x7f]	10030	1			T1	9		T2	5		T11	2
valid_sources[0x80]	11341	1			T1	3		T2	2		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1669762

1

T1

430

T2

141

T4

48

values[0x0]

all_enables

biggest_size

145841

1

T1

325

T2

119

T3

4

values[0x1]

all_enables

biggest_size

144594

1

T1

320

T2

153

T3

2