Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	106533082	16024	0	0
claim_transition_if_regwen_rd_A	106533082	1874	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106533082	16024	0	0
T39	0	4	0	0
T40	0	4	0	0
T43	0	9	0	0
T54	273702	4	0	0
T75	3358	0	0	0
T76	90299	0	0	0
T103	0	1	0	0
T152	0	1	0	0
T153	0	14	0	0
T154	0	13	0	0
T155	0	4	0	0
T156	0	9	0	0
T157	28237	0	0	0
T158	6560	0	0	0
T159	30576	0	0	0
T160	19442	0	0	0
T161	19681	0	0	0
T162	20280	0	0	0
T163	25396	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	106533082	1874	0	0
T27	81589	0	0	0
T38	36600	0	0	0
T46	30062	0	0	0
T53	252646	18	0	0
T58	328685	0	0	0
T103	0	4	0	0
T116	0	9	0	0
T121	0	240	0	0
T122	0	494	0	0
T152	0	9	0	0
T155	0	21	0	0
T164	0	2	0	0
T165	0	3	0	0
T166	0	3	0	0
T167	53639	0	0	0
T168	31198	0	0	0
T169	2917	0	0	0
T170	48519	0	0	0
T171	26789	0	0	0