Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1466600	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1666850

1

T1

944

T2

937

T3

41

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2820052	1			T1	975		T2	981		T3	53
values[0x0]	156053	1			T1	289		T2	272		T3	27
values[0x1]	157345	1			T1	271		T2	288		T3	24

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1164361	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1969089

1

T1

1070

T2

1053

T3

49

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9974	1			T1	5		T2	5		T4	1
valid_sources[0x01]	8442	1			T1	6		T2	4		T3	2
valid_sources[0x02]	9646	1			T1	4		T2	11		T3	2
valid_sources[0x03]	8598	1			T1	8		T2	2		T20	5
valid_sources[0x04]	8958	1			T1	3		T2	10		T3	1
valid_sources[0x05]	8439	1			T1	5		T20	2		T6	213
valid_sources[0x06]	8552	1			T1	7		T2	3		T13	21
valid_sources[0x07]	12049	1			T1	4		T2	5		T4	1
valid_sources[0x08]	8921	1			T1	4		T2	8		T4	2
valid_sources[0x09]	8709	1			T1	6		T4	2		T20	6
valid_sources[0x0a]	10781	1			T1	10		T2	1		T5	6
valid_sources[0x0b]	9723	1			T1	8		T2	10		T4	1
valid_sources[0x0c]	8512	1			T1	10		T2	16		T4	1
valid_sources[0x0d]	8806	1			T1	7		T2	13		T4	2
valid_sources[0x0e]	8998	1			T1	6		T2	5		T12	1
valid_sources[0x0f]	9238	1			T1	2		T13	45		T20	3
valid_sources[0x10]	8281	1			T1	11		T2	13		T3	2
valid_sources[0x11]	8670	1			T1	6		T2	3		T4	2
valid_sources[0x12]	9070	1			T1	6		T2	7		T4	1
valid_sources[0x13]	9480	1			T1	12		T2	4		T4	1
valid_sources[0x14]	8381	1			T1	6		T2	7		T4	4
valid_sources[0x15]	9873	1			T1	10		T2	8		T3	1
valid_sources[0x16]	8404	1			T1	4		T2	2		T3	1
valid_sources[0x17]	10124	1			T1	8		T2	2		T4	1
valid_sources[0x18]	10951	1			T1	7		T2	4		T4	1
valid_sources[0x19]	9952	1			T1	10		T2	12		T20	1
valid_sources[0x1a]	8774	1			T1	4		T2	6		T3	1
valid_sources[0x1b]	9713	1			T1	4		T2	1		T20	1
valid_sources[0x1c]	8491	1			T1	8		T2	11		T4	2
valid_sources[0x1d]	9728	1			T1	8		T2	1		T3	3
valid_sources[0x1e]	10313	1			T1	2		T2	6		T4	1
valid_sources[0x1f]	8488	1			T1	4		T2	5		T3	2
valid_sources[0x20]	19760	1			T1	3		T4	1		T6	185
valid_sources[0x21]	8792	1			T1	5		T2	5		T4	1
valid_sources[0x22]	8803	1			T1	11		T2	3		T3	2
valid_sources[0x23]	8360	1			T1	14		T2	2		T4	2
valid_sources[0x24]	8908	1			T1	5		T2	7		T4	1
valid_sources[0x25]	8832	1			T1	4		T2	4		T4	3
valid_sources[0x26]	9181	1			T1	3		T2	1		T4	1
valid_sources[0x27]	8654	1			T1	2		T4	5		T20	2
valid_sources[0x28]	8613	1			T1	8		T2	11		T4	1
valid_sources[0x29]	8658	1			T1	10		T2	14		T4	2
valid_sources[0x2a]	8406	1			T1	4		T2	3		T4	1
valid_sources[0x2b]	90885	1			T1	5		T2	12		T4	1
valid_sources[0x2c]	8715	1			T1	8		T2	9		T4	3
valid_sources[0x2d]	10365	1			T1	7		T4	2		T13	152
valid_sources[0x2e]	78476	1			T1	8		T5	1		T12	1
valid_sources[0x2f]	10110	1			T1	7		T2	3		T3	1
valid_sources[0x30]	8497	1			T1	8		T2	21		T20	8
valid_sources[0x31]	8559	1			T1	5		T2	1		T3	3
valid_sources[0x32]	11717	1			T2	16		T4	1		T5	2
valid_sources[0x33]	8174	1			T1	6		T2	1		T4	2
valid_sources[0x34]	9745	1			T1	7		T2	4		T4	2
valid_sources[0x35]	9979	1			T1	2		T2	3		T12	1
valid_sources[0x36]	8555	1			T1	5		T2	12		T3	3
valid_sources[0x37]	8795	1			T1	4		T2	13		T4	2
valid_sources[0x38]	8686	1			T1	9		T2	9		T20	4
valid_sources[0x39]	8524	1			T1	10		T2	1		T4	3
valid_sources[0x3a]	8632	1			T1	3		T2	11		T4	1
valid_sources[0x3b]	9894	1			T1	10		T2	6		T13	10
valid_sources[0x3c]	8529	1			T1	1		T2	9		T3	1
valid_sources[0x3d]	8842	1			T1	1		T2	4		T4	1
valid_sources[0x3e]	10233	1			T1	5		T2	3		T4	1
valid_sources[0x3f]	8591	1			T1	12		T2	2		T4	2
valid_sources[0x40]	9848	1			T1	6		T2	7		T20	3
valid_sources[0x41]	11655	1			T1	7		T2	3		T20	8
valid_sources[0x42]	8650	1			T1	4		T4	1		T20	1
valid_sources[0x43]	8859	1			T1	8		T4	3		T20	3
valid_sources[0x44]	9174	1			T1	3		T2	11		T3	2
valid_sources[0x45]	8489	1			T1	9		T2	14		T20	4
valid_sources[0x46]	8999	1			T1	7		T2	5		T3	1
valid_sources[0x47]	8500	1			T1	7		T2	4		T3	1
valid_sources[0x48]	8520	1			T1	4		T2	2		T4	2
valid_sources[0x49]	8919	1			T1	8		T2	12		T20	2
valid_sources[0x4a]	8486	1			T1	7		T2	3		T4	3
valid_sources[0x4b]	8437	1			T1	9		T2	6		T4	2
valid_sources[0x4c]	8294	1			T1	2		T2	6		T3	1
valid_sources[0x4d]	8527	1			T1	10		T2	4		T3	1
valid_sources[0x4e]	10351	1			T1	9		T2	4		T20	4
valid_sources[0x4f]	8606	1			T1	5		T2	3		T4	2
valid_sources[0x50]	9320	1			T1	4		T2	14		T3	3
valid_sources[0x51]	8602	1			T1	8		T2	10		T3	2
valid_sources[0x52]	8512	1			T1	6		T2	7		T4	2
valid_sources[0x53]	8884	1			T1	6		T2	5		T20	7
valid_sources[0x54]	8570	1			T1	4		T2	22		T4	3
valid_sources[0x55]	8700	1			T1	6		T2	4		T4	1
valid_sources[0x56]	9657	1			T1	4		T2	3		T4	1
valid_sources[0x57]	8994	1			T1	7		T2	4		T3	2
valid_sources[0x58]	8765	1			T1	6		T4	1		T20	5
valid_sources[0x59]	9996	1			T1	4		T2	1		T4	3
valid_sources[0x5a]	10412	1			T1	4		T2	4		T3	1
valid_sources[0x5b]	9893	1			T1	2		T2	5		T3	1
valid_sources[0x5c]	10944	1			T1	6		T2	3		T4	1
valid_sources[0x5d]	8920	1			T1	8		T2	2		T4	2
valid_sources[0x5e]	9687	1			T1	7		T3	1		T4	1
valid_sources[0x5f]	8503	1			T1	5		T2	10		T4	1
valid_sources[0x60]	8954	1			T1	2		T2	15		T3	1
valid_sources[0x61]	8564	1			T1	5		T2	5		T4	3
valid_sources[0x62]	12087	1			T1	10		T2	15		T4	4
valid_sources[0x63]	8337	1			T1	11		T2	8		T3	1
valid_sources[0x64]	8567	1			T1	8		T2	2		T4	2
valid_sources[0x65]	9433	1			T1	8		T2	19		T3	1
valid_sources[0x66]	8254	1			T1	15		T2	11		T3	3
valid_sources[0x67]	8770	1			T1	1		T2	7		T4	3
valid_sources[0x68]	8716	1			T1	5		T2	6		T4	1
valid_sources[0x69]	8447	1			T1	2		T2	6		T20	9
valid_sources[0x6a]	8865	1			T1	9		T2	2		T20	5
valid_sources[0x6b]	8771	1			T1	5		T2	10		T4	2
valid_sources[0x6c]	8949	1			T1	7		T4	2		T20	1
valid_sources[0x6d]	8382	1			T1	7		T2	3		T4	4
valid_sources[0x6e]	23057	1			T1	8		T2	5		T4	2
valid_sources[0x6f]	8351	1			T1	3		T2	5		T4	1
valid_sources[0x70]	8288	1			T1	4		T3	1		T20	5
valid_sources[0x71]	10275	1			T1	6		T2	10		T4	2
valid_sources[0x72]	8682	1			T1	5		T3	1		T4	3
valid_sources[0x73]	10611	1			T1	8		T2	6		T4	1
valid_sources[0x74]	8873	1			T1	4		T2	2		T4	4
valid_sources[0x75]	9753	1			T1	4		T2	1		T3	1
valid_sources[0x76]	9706	1			T1	2		T2	1		T3	1
valid_sources[0x77]	11114	1			T1	5		T2	3		T4	1
valid_sources[0x78]	11196	1			T1	6		T4	1		T13	41
valid_sources[0x79]	10116	1			T1	11		T2	2		T4	1
valid_sources[0x7a]	8669	1			T1	10		T2	3		T20	4
valid_sources[0x7b]	9939	1			T1	10		T2	8		T3	1
valid_sources[0x7c]	9444	1			T1	5		T2	3		T20	1
valid_sources[0x7d]	9613	1			T1	10		T2	12		T4	1
valid_sources[0x7e]	10623	1			T1	6		T4	2		T20	4
valid_sources[0x7f]	8668	1			T1	11		T4	2		T20	3
valid_sources[0x80]	43383	1			T1	5		T2	1		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1397237

1

T1

457

T2

459

T3

27

values[0x0]

all_enables

biggest_size

135163

1

T1

253

T2

228

T3

10

values[0x1]

all_enables

biggest_size

134450

1

T1

234

T2

250

T3

4