Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.95	100.00	82.35	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	94846442	12624	0	0
claim_transition_if_regwen_rd_A	94846442	1224	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94846442	12624	0	0
T7	21273	0	0	0
T18	348517	2	0	0
T19	28870	0	0	0
T21	50065	0	0	0
T26	85619	0	0	0
T38	0	2	0	0
T57	0	12	0	0
T60	37290	0	0	0
T80	0	5	0	0
T82	28688	0	0	0
T85	3064	0	0	0
T86	2382	0	0	0
T143	0	2	0	0
T144	0	4	0	0
T145	0	2	0	0
T146	0	2	0	0
T147	0	7	0	0
T148	0	2	0	0
T149	1695	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94846442	1224	0	0
T118	0	10	0	0
T125	0	22	0	0
T126	0	35	0	0
T144	342628	6	0	0
T145	0	9	0	0
T150	0	18	0	0
T151	0	41	0	0
T152	0	3	0	0
T153	0	23	0	0
T154	0	23	0	0
T155	19728	0	0	0
T156	156123	0	0	0
T157	142817	0	0	0
T158	151609	0	0	0
T159	773	0	0	0
T160	93871	0	0	0
T161	940	0	0	0
T162	32896	0	0	0
T163	22196	0	0	0