Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1274291	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1474672

1

T1

189

T2

34

T3

751

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2435420	1			T1	160		T2	36		T3	718
values[0x0]	155804	1			T1	56		T2	10		T3	285
values[0x1]	157739	1			T1	88		T2	6		T3	219

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1010126	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1738837

1

T1

219

T2

40

T3

858

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7430	1			T1	3		T3	1		T11	1
valid_sources[0x01]	9281	1			T3	6		T11	2		T14	3
valid_sources[0x02]	16754	1			T1	12		T3	4		T11	2
valid_sources[0x03]	8532	1			T3	3		T11	2		T14	6
valid_sources[0x04]	7360	1			T3	6		T14	2		T6	4
valid_sources[0x05]	8187	1			T3	6		T11	3		T5	1
valid_sources[0x06]	8056	1			T3	4		T11	9		T5	1
valid_sources[0x07]	9398	1			T1	3		T3	4		T11	2
valid_sources[0x08]	40819	1			T3	4		T14	1		T15	3
valid_sources[0x09]	9675	1			T1	9		T3	3		T11	13
valid_sources[0x0a]	7754	1			T1	7		T3	10		T11	5
valid_sources[0x0b]	14187	1			T1	2		T2	52		T3	7
valid_sources[0x0c]	8465	1			T3	5		T11	15		T5	1
valid_sources[0x0d]	13743	1			T3	6		T11	8		T14	1
valid_sources[0x0e]	7341	1			T3	3		T11	5		T14	3
valid_sources[0x0f]	9796	1			T3	5		T11	9		T14	7
valid_sources[0x10]	8064	1			T3	8		T11	7		T14	4
valid_sources[0x11]	8866	1			T1	1		T3	8		T11	15
valid_sources[0x12]	7816	1			T1	1		T3	5		T14	3
valid_sources[0x13]	7883	1			T1	2		T3	5		T11	5
valid_sources[0x14]	7998	1			T1	7		T3	2		T11	8
valid_sources[0x15]	7829	1			T3	8		T11	4		T14	2
valid_sources[0x16]	7849	1			T3	6		T11	4		T5	2
valid_sources[0x17]	7756	1			T3	3		T11	12		T14	7
valid_sources[0x18]	7569	1			T3	7		T11	3		T4	6
valid_sources[0x19]	8095	1			T3	5		T11	10		T14	4
valid_sources[0x1a]	7795	1			T3	5		T11	4		T14	6
valid_sources[0x1b]	7852	1			T1	5		T3	9		T11	7
valid_sources[0x1c]	8144	1			T1	5		T3	1		T11	7
valid_sources[0x1d]	7773	1			T3	5		T11	10		T14	7
valid_sources[0x1e]	7666	1			T3	5		T14	5		T15	3
valid_sources[0x1f]	7825	1			T3	3		T11	3		T5	1
valid_sources[0x20]	7801	1			T3	4		T11	14		T4	6
valid_sources[0x21]	14102	1			T1	8		T3	4		T14	3
valid_sources[0x22]	7793	1			T1	3		T3	3		T11	5
valid_sources[0x23]	8997	1			T3	9		T11	5		T14	5
valid_sources[0x24]	7564	1			T3	5		T11	1		T5	1
valid_sources[0x25]	14195	1			T3	5		T11	8		T5	1
valid_sources[0x26]	9385	1			T1	2		T3	8		T11	1
valid_sources[0x27]	7427	1			T11	4		T5	2		T14	4
valid_sources[0x28]	8147	1			T3	3		T11	5		T4	2
valid_sources[0x29]	7884	1			T3	8		T11	3		T14	2
valid_sources[0x2a]	8724	1			T1	2		T3	2		T11	9
valid_sources[0x2b]	7794	1			T3	4		T11	1		T14	5
valid_sources[0x2c]	7882	1			T3	2		T14	4		T15	2
valid_sources[0x2d]	7704	1			T3	4		T11	11		T14	6
valid_sources[0x2e]	8520	1			T3	6		T11	5		T14	2
valid_sources[0x2f]	8289	1			T1	10		T3	6		T11	14
valid_sources[0x30]	8977	1			T3	2		T11	1		T5	1
valid_sources[0x31]	45232	1			T1	1		T3	9		T14	3
valid_sources[0x32]	9794	1			T3	5		T11	1		T14	3
valid_sources[0x33]	7791	1			T3	3		T11	7		T14	3
valid_sources[0x34]	7739	1			T3	7		T11	5		T4	22
valid_sources[0x35]	7930	1			T3	6		T11	5		T5	1
valid_sources[0x36]	9007	1			T3	4		T11	8		T4	8
valid_sources[0x37]	7862	1			T1	3		T3	6		T11	6
valid_sources[0x38]	7810	1			T3	4		T11	11		T14	6
valid_sources[0x39]	7915	1			T3	4		T11	3		T14	3
valid_sources[0x3a]	7786	1			T1	4		T3	7		T11	1
valid_sources[0x3b]	8080	1			T3	8		T11	3		T14	6
valid_sources[0x3c]	9056	1			T3	9		T11	6		T14	5
valid_sources[0x3d]	7847	1			T3	2		T11	23		T14	5
valid_sources[0x3e]	7414	1			T1	1		T3	5		T11	4
valid_sources[0x3f]	9157	1			T3	6		T14	1		T15	2
valid_sources[0x40]	7946	1			T3	6		T11	4		T14	4
valid_sources[0x41]	7819	1			T3	6		T11	16		T14	4
valid_sources[0x42]	77894	1			T1	1		T3	2		T11	1
valid_sources[0x43]	33490	1			T3	6		T11	3		T14	2
valid_sources[0x44]	8616	1			T1	8		T3	10		T11	14
valid_sources[0x45]	8625	1			T1	12		T3	3		T11	4
valid_sources[0x46]	12154	1			T3	4		T11	6		T14	1
valid_sources[0x47]	7769	1			T3	5		T14	1		T15	6
valid_sources[0x48]	9598	1			T3	3		T11	4		T5	1
valid_sources[0x49]	7870	1			T3	5		T11	7		T14	4
valid_sources[0x4a]	7756	1			T1	6		T3	3		T11	6
valid_sources[0x4b]	7789	1			T1	2		T3	6		T11	1
valid_sources[0x4c]	7838	1			T3	3		T11	12		T14	4
valid_sources[0x4d]	7587	1			T1	1		T3	3		T11	4
valid_sources[0x4e]	7850	1			T1	2		T3	7		T11	6
valid_sources[0x4f]	7840	1			T3	3		T11	2		T5	2
valid_sources[0x50]	9628	1			T3	6		T11	6		T4	4
valid_sources[0x51]	7835	1			T3	4		T11	2		T5	1
valid_sources[0x52]	9871	1			T1	3		T3	7		T11	12
valid_sources[0x53]	7661	1			T3	5		T11	3		T15	3
valid_sources[0x54]	7741	1			T3	3		T11	6		T5	1
valid_sources[0x55]	10270	1			T3	5		T11	6		T14	3
valid_sources[0x56]	7787	1			T3	4		T11	5		T14	6
valid_sources[0x57]	10707	1			T3	6		T11	1		T14	4
valid_sources[0x58]	7289	1			T3	6		T11	6		T5	1
valid_sources[0x59]	8178	1			T3	2		T14	3		T15	2
valid_sources[0x5a]	44785	1			T3	4		T11	10		T14	4
valid_sources[0x5b]	7759	1			T3	5		T11	3		T14	3
valid_sources[0x5c]	26212	1			T1	3		T3	5		T11	1
valid_sources[0x5d]	7909	1			T3	4		T11	6		T14	3
valid_sources[0x5e]	7627	1			T3	2		T11	1		T14	2
valid_sources[0x5f]	7921	1			T1	1		T3	5		T11	2
valid_sources[0x60]	7763	1			T3	7		T11	6		T4	24
valid_sources[0x61]	7896	1			T3	6		T5	1		T14	6
valid_sources[0x62]	8940	1			T3	5		T11	10		T4	2
valid_sources[0x63]	7940	1			T3	8		T11	1		T14	3
valid_sources[0x64]	7941	1			T3	2		T11	10		T14	7
valid_sources[0x65]	11047	1			T3	2		T11	6		T14	4
valid_sources[0x66]	7710	1			T3	8		T11	12		T4	1
valid_sources[0x67]	8155	1			T1	8		T3	4		T11	7
valid_sources[0x68]	8761	1			T3	7		T11	8		T5	1
valid_sources[0x69]	7882	1			T3	3		T11	12		T14	2
valid_sources[0x6a]	8683	1			T3	4		T14	5		T15	3
valid_sources[0x6b]	7599	1			T3	3		T11	2		T5	1
valid_sources[0x6c]	7833	1			T3	3		T11	3		T14	8
valid_sources[0x6d]	9198	1			T3	3		T11	8		T14	3
valid_sources[0x6e]	7631	1			T3	8		T11	9		T4	1
valid_sources[0x6f]	24396	1			T1	2		T3	4		T11	2
valid_sources[0x70]	7489	1			T3	7		T11	2		T5	1
valid_sources[0x71]	12555	1			T1	4		T3	1		T11	5
valid_sources[0x72]	7623	1			T1	1		T3	1		T11	5
valid_sources[0x73]	10329	1			T1	6		T3	3		T11	20
valid_sources[0x74]	7760	1			T3	8		T11	22		T14	2
valid_sources[0x75]	7344	1			T3	11		T11	20		T14	4
valid_sources[0x76]	8848	1			T3	6		T11	17		T14	10
valid_sources[0x77]	7741	1			T3	4		T11	3		T14	6
valid_sources[0x78]	7623	1			T1	7		T3	6		T11	5
valid_sources[0x79]	7545	1			T3	5		T11	2		T5	1
valid_sources[0x7a]	9463	1			T3	7		T4	9		T14	3
valid_sources[0x7b]	9282	1			T3	3		T11	9		T14	3
valid_sources[0x7c]	7631	1			T3	5		T11	2		T5	1
valid_sources[0x7d]	8134	1			T1	1		T3	5		T11	1
valid_sources[0x7e]	9576	1			T1	2		T3	3		T11	6
valid_sources[0x7f]	8895	1			T3	4		T11	10		T14	2
valid_sources[0x80]	8515	1			T3	6		T11	1		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1204475

1

T1

64

T2

20

T3

322

values[0x0]

all_enables

biggest_size

135067

1

T1

49

T2

10

T3

242

values[0x1]

all_enables

biggest_size

135130

1

T1

76

T2

4

T3

187