Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	100.00	82.35	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	94908898	14146	0	0
claim_transition_if_regwen_rd_A	94908898	2160	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94908898	14146	0	0
T7	12003	0	0	0
T29	176731	2	0	0
T38	0	13	0	0
T44	24038	0	0	0
T47	47142	0	0	0
T57	0	6	0	0
T75	0	5	0	0
T84	0	1	0	0
T151	0	5	0	0
T152	0	4	0	0
T153	0	9	0	0
T154	0	1	0	0
T155	0	8	0	0
T156	70211	0	0	0
T157	2233	0	0	0
T158	25186	0	0	0
T159	79676	0	0	0
T160	5368	0	0	0
T161	1414	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	94908898	2160	0	0
T69	895	0	0	0
T117	0	40	0	0
T125	0	10	0	0
T162	266340	2	0	0
T163	0	6	0	0
T164	0	5	0	0
T165	0	22	0	0
T166	0	9	0	0
T167	0	19	0	0
T168	0	34	0	0
T169	0	1	0	0
T170	27276	0	0	0
T171	5859	0	0	0
T172	5623	0	0	0
T173	26370	0	0	0
T174	960669	0	0	0
T175	1187	0	0	0
T176	7257	0	0	0
T177	42647	0	0	0