Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1540653	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1746355

1

T1

3517

T3

875

T10

267

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2968349	1			T1	6111		T3	729		T10	194
values[0x0]	158933	1			T1	348		T3	302		T10	103
values[0x1]	159726	1			T1	338		T3	306		T10	105

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1224998	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2062010

1

T1

4207

T3

972

T10

294

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16547	1			T1	6627		T3	6		T10	1
valid_sources[0x01]	8048	1			T3	4		T10	1		T11	156
valid_sources[0x02]	10645	1			T3	1		T10	2		T11	162
valid_sources[0x03]	7875	1			T3	4		T10	1		T11	174
valid_sources[0x04]	8452	1			T3	6		T11	146		T12	3
valid_sources[0x05]	7908	1			T11	142		T12	11		T15	8
valid_sources[0x06]	9439	1			T3	8		T11	180		T15	1
valid_sources[0x07]	7807	1			T3	6		T10	2		T11	153
valid_sources[0x08]	7671	1			T3	5		T10	5		T11	172
valid_sources[0x09]	8413	1			T3	2		T11	215		T12	23
valid_sources[0x0a]	8097	1			T3	5		T11	161		T12	5
valid_sources[0x0b]	9590	1			T10	1		T11	171		T12	21
valid_sources[0x0c]	8617	1			T3	7		T10	2		T11	145
valid_sources[0x0d]	8504	1			T3	3		T10	3		T11	142
valid_sources[0x0e]	7914	1			T3	4		T10	1		T11	182
valid_sources[0x0f]	19387	1			T3	5		T11	134		T12	4
valid_sources[0x10]	7832	1			T1	17		T3	2		T10	2
valid_sources[0x11]	8256	1			T3	3		T11	167		T12	4
valid_sources[0x12]	26184	1			T3	8		T11	182		T12	15
valid_sources[0x13]	8272	1			T3	3		T10	3		T11	208
valid_sources[0x14]	7952	1			T3	10		T10	2		T11	181
valid_sources[0x15]	7966	1			T3	6		T10	2		T11	164
valid_sources[0x16]	8386	1			T10	8		T11	135		T12	9
valid_sources[0x17]	8025	1			T3	9		T10	3		T11	122
valid_sources[0x18]	7808	1			T3	5		T10	3		T11	119
valid_sources[0x19]	9361	1			T1	17		T3	2		T10	1
valid_sources[0x1a]	7857	1			T3	7		T11	164		T12	10
valid_sources[0x1b]	10406	1			T3	2		T10	2		T11	142
valid_sources[0x1c]	7705	1			T3	8		T10	2		T11	145
valid_sources[0x1d]	8153	1			T3	7		T10	1		T11	140
valid_sources[0x1e]	8153	1			T3	4		T11	159		T15	5
valid_sources[0x1f]	11116	1			T3	5		T10	3		T11	191
valid_sources[0x20]	8031	1			T3	5		T11	126		T12	2
valid_sources[0x21]	11671	1			T3	8		T11	141		T12	14
valid_sources[0x22]	100626	1			T3	3		T11	177		T15	6
valid_sources[0x23]	8168	1			T3	6		T10	2		T11	154
valid_sources[0x24]	19484	1			T3	8		T11	172		T12	9
valid_sources[0x25]	7793	1			T3	5		T10	1		T11	137
valid_sources[0x26]	12082	1			T3	7		T10	3		T11	173
valid_sources[0x27]	24282	1			T3	1		T10	2		T11	141
valid_sources[0x28]	7868	1			T3	5		T11	140		T12	1
valid_sources[0x29]	10540	1			T3	8		T10	1		T11	162
valid_sources[0x2a]	7454	1			T3	6		T10	3		T11	184
valid_sources[0x2b]	10856	1			T3	6		T11	179		T12	6
valid_sources[0x2c]	8044	1			T3	6		T11	170		T15	1
valid_sources[0x2d]	7990	1			T3	6		T10	1		T11	173
valid_sources[0x2e]	8047	1			T3	8		T11	111		T12	1
valid_sources[0x2f]	11170	1			T3	3		T10	1		T11	143
valid_sources[0x30]	11040	1			T3	6		T11	126		T12	15
valid_sources[0x31]	11885	1			T11	191		T12	11		T15	6
valid_sources[0x32]	9347	1			T3	2		T10	2		T11	141
valid_sources[0x33]	8166	1			T3	7		T10	2		T11	135
valid_sources[0x34]	7798	1			T3	6		T10	1		T11	130
valid_sources[0x35]	8245	1			T3	11		T10	1		T11	184
valid_sources[0x36]	7961	1			T3	4		T10	1		T11	147
valid_sources[0x37]	9221	1			T3	2		T10	2		T11	166
valid_sources[0x38]	8059	1			T3	7		T10	5		T11	151
valid_sources[0x39]	9970	1			T3	5		T11	128		T12	1
valid_sources[0x3a]	11073	1			T3	6		T11	110		T12	8
valid_sources[0x3b]	74859	1			T3	4		T10	1		T11	128
valid_sources[0x3c]	8004	1			T3	3		T11	168		T12	9
valid_sources[0x3d]	7870	1			T1	17		T3	8		T10	1
valid_sources[0x3e]	8223	1			T3	5		T11	187		T12	10
valid_sources[0x3f]	18680	1			T3	6		T10	1		T11	150
valid_sources[0x40]	8158	1			T3	9		T11	164		T12	9
valid_sources[0x41]	8236	1			T3	9		T10	1		T11	167
valid_sources[0x42]	21147	1			T3	13		T10	2		T11	175
valid_sources[0x43]	8151	1			T3	8		T10	2		T11	168
valid_sources[0x44]	8030	1			T3	5		T10	3		T11	161
valid_sources[0x45]	9775	1			T3	4		T10	3		T11	141
valid_sources[0x46]	7866	1			T3	8		T11	123		T12	9
valid_sources[0x47]	9631	1			T3	2		T10	1		T11	152
valid_sources[0x48]	8058	1			T3	8		T11	144		T12	2
valid_sources[0x49]	7799	1			T3	3		T10	3		T11	144
valid_sources[0x4a]	12958	1			T3	6		T10	9		T11	168
valid_sources[0x4b]	8306	1			T3	5		T10	1		T11	183
valid_sources[0x4c]	8619	1			T3	3		T11	128		T12	6
valid_sources[0x4d]	8474	1			T3	2		T11	172		T15	3
valid_sources[0x4e]	7906	1			T3	4		T11	164		T12	5
valid_sources[0x4f]	8281	1			T3	6		T10	1		T11	114
valid_sources[0x50]	13537	1			T3	8		T10	4		T11	115
valid_sources[0x51]	8412	1			T3	1		T10	3		T11	161
valid_sources[0x52]	9421	1			T3	5		T11	172		T12	7
valid_sources[0x53]	8841	1			T3	5		T11	200		T12	5
valid_sources[0x54]	8282	1			T3	4		T10	2		T11	160
valid_sources[0x55]	7843	1			T3	9		T10	2		T11	152
valid_sources[0x56]	7925	1			T3	2		T10	3		T11	203
valid_sources[0x57]	8170	1			T3	10		T10	2		T11	119
valid_sources[0x58]	9538	1			T3	7		T10	2		T11	157
valid_sources[0x59]	8369	1			T3	5		T10	1		T11	150
valid_sources[0x5a]	8017	1			T3	4		T10	2		T11	167
valid_sources[0x5b]	7662	1			T3	9		T11	146		T12	6
valid_sources[0x5c]	9620	1			T3	3		T10	6		T11	168
valid_sources[0x5d]	8034	1			T3	7		T10	1		T11	127
valid_sources[0x5e]	7899	1			T3	6		T10	2		T11	133
valid_sources[0x5f]	7839	1			T3	7		T10	1		T11	154
valid_sources[0x60]	8230	1			T3	15		T10	1		T11	163
valid_sources[0x61]	9461	1			T1	17		T3	13		T10	2
valid_sources[0x62]	42698	1			T3	5		T11	139		T12	7
valid_sources[0x63]	8241	1			T3	2		T10	2		T11	177
valid_sources[0x64]	8107	1			T3	6		T11	186		T15	3
valid_sources[0x65]	8058	1			T3	1		T10	4		T11	152
valid_sources[0x66]	8148	1			T3	4		T11	147		T72	10
valid_sources[0x67]	44486	1			T3	8		T10	5		T11	189
valid_sources[0x68]	9178	1			T3	5		T10	1		T11	168
valid_sources[0x69]	11244	1			T3	4		T10	1		T11	156
valid_sources[0x6a]	7870	1			T3	8		T10	1		T11	153
valid_sources[0x6b]	8171	1			T3	5		T10	2		T11	138
valid_sources[0x6c]	8227	1			T3	7		T11	124		T15	3
valid_sources[0x6d]	7951	1			T3	4		T10	2		T11	160
valid_sources[0x6e]	8357	1			T3	4		T10	1		T11	132
valid_sources[0x6f]	100826	1			T3	4		T10	3		T11	155
valid_sources[0x70]	9027	1			T3	11		T10	2		T11	142
valid_sources[0x71]	7869	1			T3	6		T10	2		T11	136
valid_sources[0x72]	8129	1			T3	5		T10	2		T11	157
valid_sources[0x73]	8015	1			T3	10		T10	3		T11	144
valid_sources[0x74]	8305	1			T1	17		T3	8		T11	166
valid_sources[0x75]	7846	1			T3	13		T10	4		T11	152
valid_sources[0x76]	8188	1			T3	4		T10	3		T11	104
valid_sources[0x77]	128836	1			T3	5		T10	5		T11	160
valid_sources[0x78]	65087	1			T3	7		T10	1		T11	139
valid_sources[0x79]	8007	1			T3	4		T10	1		T11	139
valid_sources[0x7a]	7714	1			T3	9		T11	134		T12	2
valid_sources[0x7b]	8135	1			T3	10		T10	2		T11	151
valid_sources[0x7c]	7713	1			T3	4		T10	1		T11	183
valid_sources[0x7d]	43415	1			T3	5		T10	6		T11	121
valid_sources[0x7e]	153039	1			T3	3		T11	120		T12	19
valid_sources[0x7f]	8004	1			T3	2		T10	1		T11	172
valid_sources[0x80]	9444	1			T3	2		T10	8		T11	146

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1471407

1

T1

2919

T3

340

T10

91

values[0x0]

all_enables

biggest_size

137719

1

T1

306

T3

265

T10

87

values[0x1]

all_enables

biggest_size

137229

1

T1

292

T3

270

T10

89