Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.32	100.00	82.35	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	95539768	14072	0	0
claim_transition_if_regwen_rd_A	95539768	778	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95539768	14072	0	0
T18	276973	4	0	0
T33	0	2	0	0
T35	255657	0	0	0
T45	0	16	0	0
T48	26985	0	0	0
T60	0	11	0	0
T62	20418	0	0	0
T67	81636	0	0	0
T92	1896	0	0	0
T93	1552	0	0	0
T95	0	3	0	0
T141	0	1	0	0
T142	0	4	0	0
T143	0	1	0	0
T144	0	3	0	0
T145	0	3	0	0
T146	44568	0	0	0
T147	802	0	0	0
T148	5141	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95539768	778	0	0
T89	455850	0	0	0
T95	108144	13	0	0
T107	0	57	0	0
T108	0	82	0	0
T118	0	3	0	0
T134	0	10	0	0
T145	0	9	0	0
T149	0	18	0	0
T150	0	18	0	0
T151	0	16	0	0
T152	0	6	0	0
T153	8522	0	0	0
T154	1342	0	0	0
T155	25591	0	0	0
T156	7849	0	0	0
T157	33128	0	0	0
T158	26452	0	0	0
T159	129832	0	0	0
T160	2893	0	0	0