Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1059488	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1258796

1

T1

1672

T2

1715

T3

764

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2014020	1			T1	1989		T2	2480		T3	583
values[0x0]	152054	1			T1	393		T2	273		T3	293
values[0x1]	152210	1			T1	367		T2	255		T3	307

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	840027	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1478257

1

T1

1924

T2

1982

T3

866

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5713	1			T1	9		T2	12		T3	11
valid_sources[0x01]	5982	1			T1	8		T2	6		T3	7
valid_sources[0x02]	5748	1			T1	16		T2	12		T3	3
valid_sources[0x03]	7663	1			T1	7		T2	28		T3	8
valid_sources[0x04]	9680	1			T1	8		T2	9		T3	7
valid_sources[0x05]	6356	1			T1	8		T2	23		T8	7
valid_sources[0x06]	6102	1			T1	12		T2	7		T8	2
valid_sources[0x07]	5864	1			T1	13		T2	4		T3	1
valid_sources[0x08]	29224	1			T1	20		T2	6		T8	6
valid_sources[0x09]	8426	1			T1	7		T2	6		T8	6
valid_sources[0x0a]	6471	1			T1	6		T2	4		T3	3
valid_sources[0x0b]	5866	1			T1	12		T2	11		T3	10
valid_sources[0x0c]	6286	1			T1	12		T2	12		T3	1
valid_sources[0x0d]	5722	1			T1	15		T2	1		T3	2
valid_sources[0x0e]	5872	1			T1	5		T2	23		T3	17
valid_sources[0x0f]	7721	1			T1	8		T2	18		T3	7
valid_sources[0x10]	6055	1			T1	4		T2	16		T3	1
valid_sources[0x11]	43950	1			T1	15		T2	6		T3	2
valid_sources[0x12]	5756	1			T1	11		T2	9		T3	16
valid_sources[0x13]	6193	1			T1	10		T2	13		T3	1
valid_sources[0x14]	5756	1			T1	12		T2	18		T8	6
valid_sources[0x15]	6564	1			T1	13		T2	4		T3	8
valid_sources[0x16]	26880	1			T1	5		T2	20		T8	7
valid_sources[0x17]	6350	1			T1	11		T2	6		T3	1
valid_sources[0x18]	7226	1			T1	9		T2	12		T3	5
valid_sources[0x19]	8066	1			T1	7		T2	19		T8	8
valid_sources[0x1a]	7944	1			T1	9		T2	8		T3	4
valid_sources[0x1b]	6005	1			T1	14		T2	8		T3	2
valid_sources[0x1c]	5896	1			T1	11		T2	6		T3	3
valid_sources[0x1d]	6156	1			T1	12		T2	4		T3	4
valid_sources[0x1e]	23611	1			T1	12		T2	9		T8	5
valid_sources[0x1f]	6053	1			T1	12		T2	5		T3	8
valid_sources[0x20]	5581	1			T1	11		T2	19		T3	4
valid_sources[0x21]	5832	1			T1	12		T2	13		T3	9
valid_sources[0x22]	6592	1			T1	7		T2	5		T3	6
valid_sources[0x23]	6247	1			T1	2		T2	15		T3	17
valid_sources[0x24]	6371	1			T1	13		T2	16		T3	1
valid_sources[0x25]	7378	1			T1	9		T2	11		T3	4
valid_sources[0x26]	5938	1			T1	13		T2	10		T3	10
valid_sources[0x27]	5916	1			T1	9		T2	16		T3	4
valid_sources[0x28]	6033	1			T1	11		T2	12		T3	2
valid_sources[0x29]	9603	1			T1	15		T2	15		T3	1
valid_sources[0x2a]	5819	1			T1	6		T2	3		T8	6
valid_sources[0x2b]	19868	1			T1	12		T2	6		T3	13
valid_sources[0x2c]	6046	1			T1	6		T2	3		T3	3
valid_sources[0x2d]	6588	1			T1	13		T2	8		T3	6
valid_sources[0x2e]	6269	1			T1	10		T2	20		T3	2
valid_sources[0x2f]	6721	1			T1	9		T2	8		T3	5
valid_sources[0x30]	6001	1			T1	6		T2	13		T8	6
valid_sources[0x31]	6245	1			T1	7		T2	6		T3	2
valid_sources[0x32]	9510	1			T1	13		T2	11		T3	5
valid_sources[0x33]	6511	1			T1	14		T2	10		T8	12
valid_sources[0x34]	7407	1			T1	12		T2	16		T3	2
valid_sources[0x35]	6191	1			T1	13		T2	12		T3	8
valid_sources[0x36]	5955	1			T1	11		T2	18		T3	3
valid_sources[0x37]	7509	1			T1	11		T2	20		T3	8
valid_sources[0x38]	5790	1			T1	5		T2	3		T3	2
valid_sources[0x39]	11156	1			T1	11		T2	10		T3	1
valid_sources[0x3a]	10039	1			T1	9		T2	14		T3	7
valid_sources[0x3b]	6722	1			T1	14		T2	1		T3	4
valid_sources[0x3c]	8313	1			T1	10		T2	17		T3	5
valid_sources[0x3d]	7065	1			T1	8		T2	24		T3	2
valid_sources[0x3e]	6092	1			T1	9		T2	11		T3	2
valid_sources[0x3f]	6328	1			T1	7		T2	14		T3	3
valid_sources[0x40]	5694	1			T1	8		T2	11		T3	9
valid_sources[0x41]	5795	1			T1	2		T2	16		T3	3
valid_sources[0x42]	6990	1			T1	9		T2	13		T3	4
valid_sources[0x43]	27623	1			T1	6		T2	14		T3	4
valid_sources[0x44]	6208	1			T1	13		T2	24		T3	3
valid_sources[0x45]	20043	1			T1	11		T2	10		T3	3
valid_sources[0x46]	5911	1			T1	7		T2	8		T3	7
valid_sources[0x47]	6628	1			T1	11		T2	23		T8	8
valid_sources[0x48]	6002	1			T1	11		T2	9		T3	3
valid_sources[0x49]	6826	1			T1	13		T2	15		T8	8
valid_sources[0x4a]	6449	1			T1	11		T2	9		T3	21
valid_sources[0x4b]	6277	1			T1	12		T2	4		T3	9
valid_sources[0x4c]	10432	1			T1	9		T2	7		T3	4
valid_sources[0x4d]	5875	1			T1	8		T2	4		T8	8
valid_sources[0x4e]	5989	1			T1	12		T2	17		T3	8
valid_sources[0x4f]	6398	1			T1	15		T2	5		T8	6
valid_sources[0x50]	59468	1			T1	9		T2	10		T3	6
valid_sources[0x51]	6135	1			T1	17		T2	17		T3	7
valid_sources[0x52]	6177	1			T1	13		T2	29		T3	9
valid_sources[0x53]	5620	1			T1	15		T2	29		T3	5
valid_sources[0x54]	6132	1			T1	20		T2	14		T3	6
valid_sources[0x55]	6102	1			T1	9		T2	3		T3	7
valid_sources[0x56]	6277	1			T1	11		T2	14		T8	7
valid_sources[0x57]	5903	1			T1	10		T2	10		T3	2
valid_sources[0x58]	6043	1			T1	8		T2	10		T3	5
valid_sources[0x59]	5883	1			T1	6		T2	14		T3	4
valid_sources[0x5a]	6297	1			T1	13		T2	3		T3	1
valid_sources[0x5b]	5625	1			T1	10		T2	17		T3	4
valid_sources[0x5c]	7390	1			T1	9		T2	25		T3	3
valid_sources[0x5d]	6929	1			T1	10		T2	9		T3	4
valid_sources[0x5e]	5933	1			T1	10		T2	2		T3	15
valid_sources[0x5f]	6099	1			T1	13		T2	24		T3	10
valid_sources[0x60]	7102	1			T1	9		T2	19		T3	6
valid_sources[0x61]	6275	1			T1	11		T2	6		T3	16
valid_sources[0x62]	10421	1			T1	9		T2	6		T3	17
valid_sources[0x63]	6355	1			T1	13		T2	16		T3	6
valid_sources[0x64]	6369	1			T1	13		T2	9		T3	2
valid_sources[0x65]	5788	1			T1	6		T2	10		T3	3
valid_sources[0x66]	6244	1			T1	12		T2	25		T3	6
valid_sources[0x67]	7352	1			T1	4		T2	6		T8	5
valid_sources[0x68]	5657	1			T1	7		T2	13		T3	2
valid_sources[0x69]	7156	1			T1	8		T2	11		T3	10
valid_sources[0x6a]	6098	1			T1	5		T2	4		T3	3
valid_sources[0x6b]	6431	1			T1	7		T2	5		T3	1
valid_sources[0x6c]	37018	1			T1	12		T2	19		T3	1
valid_sources[0x6d]	25048	1			T1	14		T2	9		T3	3
valid_sources[0x6e]	6047	1			T1	15		T2	6		T3	1
valid_sources[0x6f]	6053	1			T1	11		T2	4		T3	7
valid_sources[0x70]	7339	1			T1	4		T2	8		T3	2
valid_sources[0x71]	5725	1			T1	10		T2	6		T3	2
valid_sources[0x72]	6116	1			T1	9		T2	11		T3	5
valid_sources[0x73]	6124	1			T1	10		T2	8		T11	2
valid_sources[0x74]	5787	1			T1	14		T2	11		T3	9
valid_sources[0x75]	6007	1			T1	14		T2	17		T3	5
valid_sources[0x76]	6140	1			T1	8		T2	5		T3	3
valid_sources[0x77]	131280	1			T1	8		T2	19		T3	1
valid_sources[0x78]	8337	1			T1	16		T2	17		T3	9
valid_sources[0x79]	7243	1			T1	15		T2	12		T3	20
valid_sources[0x7a]	6226	1			T1	10		T2	14		T3	8
valid_sources[0x7b]	6232	1			T1	5		T2	12		T3	8
valid_sources[0x7c]	7694	1			T1	11		T2	5		T3	11
valid_sources[0x7d]	5853	1			T1	10		T2	5		T3	1
valid_sources[0x7e]	7193	1			T1	10		T2	7		T3	5
valid_sources[0x7f]	6209	1			T1	7		T2	13		T3	1
valid_sources[0x80]	6159	1			T1	7		T2	5		T8	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

996407

1

T1

1006

T2

1251

T3

251

values[0x0]

all_enables

biggest_size

132061

1

T1

344

T2

243

T3

251

values[0x1]

all_enables

biggest_size

130328

1

T1

322

T2

221

T3

262