Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.57	100.00	82.35	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	81071619	13967	0	0
claim_transition_if_regwen_rd_A	81071619	779	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81071619	13967	0	0
T18	240244	1	0	0
T24	146532	1	0	0
T25	6370	0	0	0
T47	0	2	0	0
T51	60431	0	0	0
T55	0	1	0	0
T57	0	8	0	0
T59	0	8	0	0
T63	34816	0	0	0
T83	30156	0	0	0
T86	1415	0	0	0
T87	36877	0	0	0
T88	13259	0	0	0
T89	24552	0	0	0
T90	0	5	0	0
T93	0	3	0	0
T148	0	6	0	0
T149	0	4	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81071619	779	0	0
T7	45518	0	0	0
T24	146532	8	0	0
T25	6370	0	0	0
T26	34950	0	0	0
T51	60431	0	0	0
T63	34816	0	0	0
T73	20393	0	0	0
T83	30156	0	0	0
T88	13259	0	0	0
T89	24552	0	0	0
T111	0	89	0	0
T150	0	6	0	0
T151	0	7	0	0
T152	0	48	0	0
T153	0	26	0	0
T154	0	29	0	0
T155	0	5	0	0
T156	0	1	0	0
T157	0	3	0	0