Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1426460	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1634921

1

T1

7

T3

10

T6

236

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2738120	1			T1	13		T6	245		T10	47
values[0x0]	161208	1			T1	3		T3	23		T6	125
values[0x1]	162053	1			T1	5		T3	18		T6	94

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1132730	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1928651

1

T1

14

T3

12

T6

270

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10945	1			T11	7		T12	6		T15	3
valid_sources[0x01]	9409	1			T11	4		T12	3		T15	5
valid_sources[0x02]	10943	1			T5	1		T11	13		T15	3
valid_sources[0x03]	9579	1			T11	12		T12	3		T15	11
valid_sources[0x04]	9589	1			T3	1		T6	13		T11	6
valid_sources[0x05]	9617	1			T6	60		T12	4		T15	10
valid_sources[0x06]	9469	1			T3	1		T5	4		T11	6
valid_sources[0x07]	10210	1			T10	1		T11	6		T12	1
valid_sources[0x08]	9378	1			T11	15		T15	1		T18	2
valid_sources[0x09]	9298	1			T3	1		T11	11		T15	4
valid_sources[0x0a]	12965	1			T11	4		T15	6		T18	1
valid_sources[0x0b]	9198	1			T11	3		T12	3		T15	6
valid_sources[0x0c]	9269	1			T6	1		T11	8		T12	8
valid_sources[0x0d]	9511	1			T10	1		T11	5		T12	5
valid_sources[0x0e]	54133	1			T5	6		T11	4		T12	10
valid_sources[0x0f]	10355	1			T10	1		T11	6		T12	16
valid_sources[0x10]	13788	1			T1	3		T11	5		T12	9
valid_sources[0x11]	9283	1			T11	6		T15	6		T18	3
valid_sources[0x12]	10800	1			T11	7		T15	6		T18	2
valid_sources[0x13]	9609	1			T11	1		T12	1		T15	7
valid_sources[0x14]	9040	1			T10	1		T11	2		T15	5
valid_sources[0x15]	9626	1			T11	10		T15	9		T18	3
valid_sources[0x16]	8947	1			T5	1		T11	3		T12	8
valid_sources[0x17]	9475	1			T10	1		T11	7		T12	10
valid_sources[0x18]	9829	1			T11	8		T12	1		T18	5
valid_sources[0x19]	9546	1			T1	1		T6	2		T11	6
valid_sources[0x1a]	9526	1			T6	57		T11	4		T12	9
valid_sources[0x1b]	9350	1			T5	2		T11	17		T15	3
valid_sources[0x1c]	10365	1			T5	5		T11	5		T12	5
valid_sources[0x1d]	10297	1			T10	1		T5	1		T11	1
valid_sources[0x1e]	10977	1			T11	7		T15	1		T18	2
valid_sources[0x1f]	8784	1			T11	11		T12	14		T15	11
valid_sources[0x20]	8844	1			T3	1		T11	1		T12	5
valid_sources[0x21]	9228	1			T3	1		T11	8		T15	1
valid_sources[0x22]	9725	1			T5	2		T11	9		T12	8
valid_sources[0x23]	9131	1			T11	6		T12	4		T15	9
valid_sources[0x24]	9736	1			T3	1		T5	10		T11	2
valid_sources[0x25]	9853	1			T3	1		T6	5		T11	6
valid_sources[0x26]	9068	1			T10	1		T11	1		T20	1
valid_sources[0x27]	54403	1			T10	2		T4	1		T11	2
valid_sources[0x28]	11475	1			T11	9		T15	2		T18	8
valid_sources[0x29]	29241	1			T11	6		T15	12		T18	2
valid_sources[0x2a]	9480	1			T10	1		T11	13		T12	6
valid_sources[0x2b]	9972	1			T3	1		T11	9		T12	2
valid_sources[0x2c]	9493	1			T11	1		T15	5		T18	5
valid_sources[0x2d]	9207	1			T6	5		T11	5		T15	2
valid_sources[0x2e]	9353	1			T11	5		T12	4		T15	4
valid_sources[0x2f]	10122	1			T10	1		T11	11		T15	6
valid_sources[0x30]	67780	1			T4	6		T11	20		T15	1
valid_sources[0x31]	21723	1			T3	1		T11	4		T15	4
valid_sources[0x32]	9801	1			T11	4		T15	5		T14	92
valid_sources[0x33]	9570	1			T3	1		T11	10		T15	1
valid_sources[0x34]	9140	1			T6	3		T5	10		T11	12
valid_sources[0x35]	9693	1			T11	6		T15	2		T18	3
valid_sources[0x36]	14373	1			T6	13		T11	2		T12	3
valid_sources[0x37]	9198	1			T4	5		T11	8		T15	1
valid_sources[0x38]	9089	1			T5	8		T11	12		T12	2
valid_sources[0x39]	14083	1			T11	3		T12	1		T15	4
valid_sources[0x3a]	11942	1			T11	13		T12	4		T15	9
valid_sources[0x3b]	9929	1			T6	2		T4	4		T11	6
valid_sources[0x3c]	98158	1			T3	1		T5	2		T11	18
valid_sources[0x3d]	9535	1			T5	14		T11	8		T12	2
valid_sources[0x3e]	9820	1			T11	8		T15	7		T18	5
valid_sources[0x3f]	12500	1			T11	11		T15	9		T18	2
valid_sources[0x40]	9044	1			T10	1		T5	19		T11	13
valid_sources[0x41]	9759	1			T11	6		T12	1		T15	4
valid_sources[0x42]	9583	1			T11	15		T15	6		T18	3
valid_sources[0x43]	10745	1			T5	2		T11	8		T12	12
valid_sources[0x44]	9113	1			T4	3		T5	3		T11	4
valid_sources[0x45]	9941	1			T11	6		T12	7		T15	2
valid_sources[0x46]	9049	1			T11	7		T12	2		T15	3
valid_sources[0x47]	9412	1			T11	4		T12	5		T15	4
valid_sources[0x48]	9505	1			T11	11		T15	2		T18	4
valid_sources[0x49]	9383	1			T11	11		T15	3		T18	3
valid_sources[0x4a]	9450	1			T11	9		T12	13		T15	5
valid_sources[0x4b]	10280	1			T6	23		T10	1		T11	13
valid_sources[0x4c]	9360	1			T5	13		T11	4		T12	9
valid_sources[0x4d]	9696	1			T4	1		T11	8		T15	4
valid_sources[0x4e]	9003	1			T11	9		T15	3		T18	2
valid_sources[0x4f]	9354	1			T11	7		T12	15		T15	1
valid_sources[0x50]	9758	1			T11	4		T15	4		T18	10
valid_sources[0x51]	10330	1			T6	3		T11	3		T12	8
valid_sources[0x52]	9279	1			T3	1		T11	16		T12	4
valid_sources[0x53]	9244	1			T11	4		T12	15		T15	3
valid_sources[0x54]	14034	1			T3	1		T6	8		T11	5
valid_sources[0x55]	9533	1			T3	1		T11	5		T15	2
valid_sources[0x56]	9572	1			T1	1		T6	3		T11	14
valid_sources[0x57]	12791	1			T11	3		T15	6		T18	7
valid_sources[0x58]	9596	1			T11	4		T12	10		T15	6
valid_sources[0x59]	13997	1			T11	10		T12	2		T15	6
valid_sources[0x5a]	9015	1			T4	2		T11	12		T15	4
valid_sources[0x5b]	8968	1			T11	4		T15	7		T18	1
valid_sources[0x5c]	15780	1			T5	5		T11	5		T15	2
valid_sources[0x5d]	10157	1			T11	6		T12	1		T15	8
valid_sources[0x5e]	9348	1			T4	1		T11	4		T15	8
valid_sources[0x5f]	9453	1			T10	1		T11	10		T15	7
valid_sources[0x60]	9416	1			T3	3		T11	6		T15	1
valid_sources[0x61]	9178	1			T11	11		T12	22		T15	1
valid_sources[0x62]	9699	1			T3	1		T5	38		T11	5
valid_sources[0x63]	9057	1			T6	1		T11	4		T12	3
valid_sources[0x64]	10956	1			T11	8		T15	5		T20	2
valid_sources[0x65]	9263	1			T5	7		T11	14		T15	2
valid_sources[0x66]	10550	1			T10	1		T11	11		T12	1
valid_sources[0x67]	10744	1			T11	10		T12	1		T15	5
valid_sources[0x68]	9035	1			T10	1		T11	10		T12	19
valid_sources[0x69]	60670	1			T11	8		T15	2		T18	4
valid_sources[0x6a]	9300	1			T10	1		T11	8		T12	12
valid_sources[0x6b]	9561	1			T10	1		T11	2		T15	6
valid_sources[0x6c]	9434	1			T6	3		T11	10		T12	7
valid_sources[0x6d]	12556	1			T4	17		T11	4		T15	3
valid_sources[0x6e]	12576	1			T11	3		T15	3		T20	1
valid_sources[0x6f]	9553	1			T11	6		T15	3		T18	1
valid_sources[0x70]	13884	1			T5	10		T11	7		T15	2
valid_sources[0x71]	9234	1			T5	5		T11	13		T15	5
valid_sources[0x72]	9096	1			T11	2		T12	14		T15	2
valid_sources[0x73]	9308	1			T10	1		T11	1		T15	1
valid_sources[0x74]	11206	1			T10	2		T11	10		T12	1
valid_sources[0x75]	9402	1			T3	1		T4	11		T11	5
valid_sources[0x76]	9688	1			T10	1		T11	4		T15	3
valid_sources[0x77]	11727	1			T5	2		T11	4		T15	2
valid_sources[0x78]	9410	1			T5	12		T11	1		T15	5
valid_sources[0x79]	9784	1			T6	59		T5	2		T11	3
valid_sources[0x7a]	9295	1			T4	5		T11	3		T15	2
valid_sources[0x7b]	12979	1			T11	8		T15	4		T18	2
valid_sources[0x7c]	13678	1			T11	9		T12	12		T15	3
valid_sources[0x7d]	9718	1			T10	1		T11	8		T12	2
valid_sources[0x7e]	15608	1			T10	1		T5	3		T11	2
valid_sources[0x7f]	9720	1			T11	5		T12	20		T15	5
valid_sources[0x80]	9328	1			T11	2		T18	5		T20	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1356602

1

T6

114

T4

42

T5

78

values[0x0]

all_enables

biggest_size

139507

1

T1

3

T3

8

T6

71

values[0x1]

all_enables

biggest_size

138812

1

T1

4

T3

2

T6

51