Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105370694

1

T1

19792

T2

1617

T3

1038

auto[1]

1391876

1

T1

1485

T2

198

T12

2376

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105360931

1

T1

18703

T2

1815

T3

1038

auto[1]

1401639

1

T1

2574

T12

1485

T5

196

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6988009	1			T1	6708		T2	259		T3	100
auto[IdleSt]	22651176	1			T1	1189		T2	1059		T3	79
auto[ClkMuxSt]	36189	1			T2	2		T3	1		T4	60
auto[CntIncrSt]	35955	1			T2	2		T3	1		T4	60
auto[CntProgSt]	1697005	1			T2	111		T3	7		T4	218
auto[TransCheckSt]	27874	1			T3	1		T4	60		T12	39
auto[TokenHashSt]	44733725	1			T3	21		T4	2102		T12	841
auto[FlashRmaSt]	35404	1			T12	77		T13	209		T5	28
auto[TokenCheck0St]	12662	1			T12	31		T13	39		T5	5
auto[TokenCheck1St]	9356	1			T12	20		T13	13		T5	5
auto[TransProgSt]	409476	1			T12	681		T5	146		T6	16
auto[PostTransSt]	13390956	1			T2	112		T3	828		T4	10592
auto[ScrapSt]	335697	1			T37	3		T38	48		T39	3
auto[EscalateSt]	6466985	1			T1	5914		T2	270		T12	4835
auto[InvalidSt]	9930229	1			T1	7460		T12	1707		T5	13759

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1872	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	9930229	1			T1	7460		T12	1707		T5	13759
EscalateSt	6466985	1			T1	5914		T2	270		T12	4835
ScrapSt	335697	1			T37	3		T38	48		T39	3
PostTransSt	13390956	1			T2	112		T3	828		T4	10592
TransProgSt	409476	1			T12	681		T5	146		T6	16
TokenCheck1St	9356	1			T12	20		T13	13		T5	5
TokenCheck0St	12662	1			T12	31		T13	39		T5	5
FlashRmaSt	35404	1			T12	77		T13	209		T5	28
TokenHashSt	44733725	1			T3	21		T4	2102		T12	841
TransCheckSt	27874	1			T3	1		T4	60		T12	39
CntProgSt	1697005	1			T2	111		T3	7		T4	218
CntIncrSt	35955	1			T2	2		T3	1		T4	60
ClkMuxSt	36189	1			T2	2		T3	1		T4	60
IdleSt	22651176	1			T1	1189		T2	1059		T3	79
ResetSt	6988009	1			T1	6708		T2	259		T3	100
arcs[ResetSt=>IdleSt]	54035	1			T1	47		T2	3		T3	1
arcs[IdleSt=>ScrapSt]	298	1			T37	1		T38	1		T39	1
arcs[IdleSt=>ClkMuxSt]	36026	1			T2	2		T3	1		T4	60
arcs[ClkMuxSt=>CntIncrSt]	35955	1			T2	2		T3	1		T4	60
arcs[CntIncrSt=>PostTransSt]	1928	1			T14	4		T16	7		T17	9
arcs[CntIncrSt=>CntProgSt]	33957	1			T2	2		T3	1		T4	60
arcs[CntProgSt=>PostTransSt]	4954	1			T2	2		T12	17		T14	11
arcs[CntProgSt=>TransCheckSt]	27874	1			T3	1		T4	60		T12	39
arcs[TransCheckSt=>PostTransSt]	3854	1			T13	45		T14	6		T15	21
arcs[TransCheckSt=>TokenHashSt]	23873	1			T3	1		T4	60		T12	39
arcs[TokenHashSt=>PostTransSt]	10378	1			T3	1		T4	60		T12	8
arcs[TokenHashSt=>FlashRmaSt]	12757	1			T12	31		T13	39		T5	5
arcs[FlashRmaSt=>TokenCheck0St]	12662	1			T12	31		T13	39		T5	5
arcs[TokenCheck0St=>PostTransSt]	3270	1			T12	11		T13	26		T14	4
arcs[TokenCheck0St=>TokenCheck1St]	9356	1			T12	20		T13	13		T5	5
arcs[TokenCheck1St=>PostTransSt]	649	1			T13	13		T14	3		T15	10
arcs[TransProgSt=>PostTransSt]	7851	1			T12	20		T5	5		T6	8
arcs[IdleSt=>EscalateSt]	226	1			T18	6		T37	16		T39	4
arcs[ClkMuxSt=>EscalateSt]	71	1			T21	2		T18	1		T37	3
arcs[CntIncrSt=>EscalateSt]	70	1			T21	2		T18	2		T37	1
arcs[CntProgSt=>EscalateSt]	1129	1			T21	37		T18	17		T37	12
arcs[TransCheckSt=>EscalateSt]	147	1			T21	2		T37	11		T53	6
arcs[TokenHashSt=>EscalateSt]	738	1			T21	23		T18	6		T37	17
arcs[FlashRmaSt=>EscalateSt]	95	1			T21	4		T18	1		T37	1
arcs[TokenCheck0St=>EscalateSt]	36	1			T37	2		T39	3		T50	2
arcs[TokenCheck1St=>EscalateSt]	149	1			T21	1		T18	2		T37	3
arcs[TransProgSt=>EscalateSt]	707	1			T21	16		T18	12		T37	13
arcs[PostTransSt=>EscalateSt]	5226	1			T2	2		T12	17		T14	11
arcs[InvalidSt=>EscalateSt]	13468	1			T1	41		T12	22		T5	7

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6987852	1			T1	6708		T2	259		T3	100
auto[0]	auto[IdleSt]	22651019	1			T1	1189		T2	1059		T3	79
auto[0]	auto[ClkMuxSt]	36142	1			T2	2		T3	1		T4	60
auto[0]	auto[CntIncrSt]	35905	1			T2	2		T3	1		T4	60
auto[0]	auto[CntProgSt]	1696259	1			T2	111		T3	7		T4	218
auto[0]	auto[TransCheckSt]	27783	1			T3	1		T4	60		T12	39
auto[0]	auto[TokenHashSt]	44733240	1			T3	21		T4	2102		T12	841
auto[0]	auto[FlashRmaSt]	35337	1			T12	77		T13	209		T5	28
auto[0]	auto[TokenCheck0St]	12638	1			T12	31		T13	39		T5	5
auto[0]	auto[TokenCheck1St]	9251	1			T12	20		T13	13		T5	5
auto[0]	auto[TransProgSt]	409000	1			T12	681		T5	146		T6	16
auto[0]	auto[PostTransSt]	13388287	1			T2	110		T3	828		T4	10592
auto[0]	auto[ScrapSt]	335655	1			T37	3		T38	48		T39	2
auto[0]	auto[EscalateSt]	5086891	1			T1	4444		T2	74		T12	2483
auto[0]	auto[InvalidSt]	9923563	1			T1	7445		T12	1693		T5	13754
auto[1]	auto[ResetSt]	157	1			T21	2		T18	4		T39	3
auto[1]	auto[IdleSt]	157	1			T18	4		T37	10		T39	2
auto[1]	auto[ClkMuxSt]	47	1			T21	1		T18	1		T37	3
auto[1]	auto[CntIncrSt]	50	1			T21	2		T18	1		T37	1
auto[1]	auto[CntProgSt]	746	1			T21	24		T18	11		T37	10
auto[1]	auto[TransCheckSt]	91	1			T21	1		T37	9		T53	4
auto[1]	auto[TokenHashSt]	485	1			T21	13		T18	2		T37	11
auto[1]	auto[FlashRmaSt]	67	1			T21	4		T18	1		T37	1
auto[1]	auto[TokenCheck0St]	24	1			T37	1		T39	2		T50	2
auto[1]	auto[TokenCheck1St]	105	1			T18	1		T37	2		T39	3
auto[1]	auto[TransProgSt]	476	1			T21	13		T18	8		T37	8
auto[1]	auto[PostTransSt]	2669	1			T2	2		T12	10		T14	8
auto[1]	auto[ScrapSt]	42	1			T39	1		T50	2		T81	3
auto[1]	auto[EscalateSt]	1380094	1			T1	1470		T2	196		T12	2352
auto[1]	auto[InvalidSt]	6666	1			T1	15		T12	14		T5	5

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6987866	1			T1	6708		T2	259		T3	100
auto[0]	auto[IdleSt]	22651037	1			T1	1189		T2	1059		T3	79
auto[0]	auto[ClkMuxSt]	36144	1			T2	2		T3	1		T4	60
auto[0]	auto[CntIncrSt]	35907	1			T2	2		T3	1		T4	60
auto[0]	auto[CntProgSt]	1696232	1			T2	111		T3	7		T4	218
auto[0]	auto[TransCheckSt]	27775	1			T3	1		T4	60		T12	39
auto[0]	auto[TokenHashSt]	44733213	1			T3	21		T4	2102		T12	841
auto[0]	auto[FlashRmaSt]	35346	1			T12	77		T13	209		T5	28
auto[0]	auto[TokenCheck0St]	12641	1			T12	31		T13	39		T5	5
auto[0]	auto[TokenCheck1St]	9265	1			T12	20		T13	13		T5	5
auto[0]	auto[TransProgSt]	408999	1			T12	681		T5	146		T6	16
auto[0]	auto[PostTransSt]	13388302	1			T2	112		T3	828		T4	10592
auto[0]	auto[ScrapSt]	335661	1			T37	2		T38	48		T39	2
auto[0]	auto[EscalateSt]	5077244	1			T1	3366		T2	270		T12	3365
auto[0]	auto[InvalidSt]	9923427	1			T1	7434		T12	1699		T5	13757
auto[1]	auto[ResetSt]	143	1			T21	3		T18	4		T39	4
auto[1]	auto[IdleSt]	139	1			T18	4		T37	9		T39	4
auto[1]	auto[ClkMuxSt]	45	1			T21	2		T37	2		T39	2
auto[1]	auto[CntIncrSt]	48	1			T21	1		T18	1		T37	1
auto[1]	auto[CntProgSt]	773	1			T21	25		T18	13		T37	6
auto[1]	auto[TransCheckSt]	99	1			T21	1		T37	7		T53	4
auto[1]	auto[TokenHashSt]	512	1			T21	15		T18	5		T37	12
auto[1]	auto[FlashRmaSt]	58	1			T21	3		T18	1		T39	1
auto[1]	auto[TokenCheck0St]	21	1			T37	2		T39	2		T81	1
auto[1]	auto[TokenCheck1St]	91	1			T21	1		T18	1		T37	3
auto[1]	auto[TransProgSt]	477	1			T21	12		T18	8		T37	10
auto[1]	auto[PostTransSt]	2654	1			T12	7		T14	3		T21	1
auto[1]	auto[ScrapSt]	36	1			T37	1		T39	1		T81	2
auto[1]	auto[EscalateSt]	1389741	1			T1	2548		T12	1470		T5	194
auto[1]	auto[InvalidSt]	6802	1			T1	26		T12	8		T5	2