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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.89 97.92 96.12 93.38 97.62 98.52 98.76 95.94


Total test records in report: 990
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T815 /workspace/coverage/default/31.lc_ctrl_jtag_access.1704624530 Jul 12 05:36:45 PM PDT 24 Jul 12 05:36:47 PM PDT 24 38000636 ps
T816 /workspace/coverage/default/30.lc_ctrl_sec_mubi.1034025906 Jul 12 05:36:42 PM PDT 24 Jul 12 05:37:04 PM PDT 24 1387289957 ps
T817 /workspace/coverage/default/22.lc_ctrl_errors.3422916676 Jul 12 05:37:01 PM PDT 24 Jul 12 05:37:16 PM PDT 24 257150454 ps
T818 /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2217306558 Jul 12 05:35:33 PM PDT 24 Jul 12 05:36:50 PM PDT 24 7687006798 ps
T819 /workspace/coverage/default/12.lc_ctrl_jtag_access.629563021 Jul 12 05:35:49 PM PDT 24 Jul 12 05:35:56 PM PDT 24 104765150 ps
T820 /workspace/coverage/default/17.lc_ctrl_stress_all.1921509096 Jul 12 05:36:21 PM PDT 24 Jul 12 05:37:15 PM PDT 24 7547218297 ps
T821 /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3811968500 Jul 12 05:36:49 PM PDT 24 Jul 12 05:36:51 PM PDT 24 44178645 ps
T822 /workspace/coverage/default/44.lc_ctrl_security_escalation.61128264 Jul 12 05:37:18 PM PDT 24 Jul 12 05:37:32 PM PDT 24 3535540464 ps
T823 /workspace/coverage/default/12.lc_ctrl_alert_test.3484851773 Jul 12 05:44:11 PM PDT 24 Jul 12 05:44:13 PM PDT 24 52198142 ps
T824 /workspace/coverage/default/25.lc_ctrl_alert_test.1637473062 Jul 12 05:37:06 PM PDT 24 Jul 12 05:37:12 PM PDT 24 28270232 ps
T825 /workspace/coverage/default/12.lc_ctrl_state_failure.2979270051 Jul 12 05:36:14 PM PDT 24 Jul 12 05:36:43 PM PDT 24 308785730 ps
T826 /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3627036972 Jul 12 05:35:11 PM PDT 24 Jul 12 05:35:29 PM PDT 24 436738632 ps
T827 /workspace/coverage/default/8.lc_ctrl_stress_all.221421491 Jul 12 05:35:47 PM PDT 24 Jul 12 05:37:23 PM PDT 24 4590236200 ps
T828 /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2432497520 Jul 12 05:35:37 PM PDT 24 Jul 12 05:35:47 PM PDT 24 771150447 ps
T829 /workspace/coverage/default/14.lc_ctrl_sec_mubi.3203298491 Jul 12 05:35:57 PM PDT 24 Jul 12 05:36:13 PM PDT 24 7283651129 ps
T830 /workspace/coverage/default/16.lc_ctrl_state_post_trans.996942792 Jul 12 05:36:28 PM PDT 24 Jul 12 05:36:39 PM PDT 24 70868453 ps
T831 /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3091206011 Jul 12 05:35:25 PM PDT 24 Jul 12 05:35:45 PM PDT 24 1281642820 ps
T832 /workspace/coverage/default/26.lc_ctrl_prog_failure.810836345 Jul 12 06:28:34 PM PDT 24 Jul 12 06:28:39 PM PDT 24 1358118910 ps
T833 /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1972045568 Jul 12 05:35:51 PM PDT 24 Jul 12 05:36:12 PM PDT 24 1473077014 ps
T834 /workspace/coverage/default/41.lc_ctrl_alert_test.3077370399 Jul 12 05:37:14 PM PDT 24 Jul 12 05:37:20 PM PDT 24 57353636 ps
T835 /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.4042123469 Jul 12 05:36:26 PM PDT 24 Jul 12 05:41:33 PM PDT 24 17735948310 ps
T836 /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1137567498 Jul 12 05:35:24 PM PDT 24 Jul 12 05:35:35 PM PDT 24 324376110 ps
T837 /workspace/coverage/default/9.lc_ctrl_errors.1715300513 Jul 12 05:35:52 PM PDT 24 Jul 12 05:36:06 PM PDT 24 280003910 ps
T838 /workspace/coverage/default/18.lc_ctrl_errors.743903100 Jul 12 05:36:14 PM PDT 24 Jul 12 05:36:28 PM PDT 24 4074243798 ps
T839 /workspace/coverage/default/41.lc_ctrl_stress_all.2675637550 Jul 12 05:37:05 PM PDT 24 Jul 12 05:40:52 PM PDT 24 14813685200 ps
T840 /workspace/coverage/default/10.lc_ctrl_stress_all.893169082 Jul 12 05:35:56 PM PDT 24 Jul 12 05:37:17 PM PDT 24 2259784931 ps
T841 /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2725307691 Jul 12 05:36:32 PM PDT 24 Jul 12 05:36:50 PM PDT 24 380320891 ps
T174 /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.870294489 Jul 12 05:36:59 PM PDT 24 Jul 12 05:54:10 PM PDT 24 761731009940 ps
T842 /workspace/coverage/default/2.lc_ctrl_prog_failure.3935500975 Jul 12 05:35:21 PM PDT 24 Jul 12 05:35:25 PM PDT 24 383768536 ps
T843 /workspace/coverage/default/22.lc_ctrl_sec_token_mux.4114424557 Jul 12 05:36:34 PM PDT 24 Jul 12 05:36:47 PM PDT 24 227895017 ps
T844 /workspace/coverage/default/41.lc_ctrl_sec_token_digest.3820711470 Jul 12 05:36:51 PM PDT 24 Jul 12 05:37:10 PM PDT 24 604480036 ps
T845 /workspace/coverage/default/2.lc_ctrl_security_escalation.3207046993 Jul 12 05:35:23 PM PDT 24 Jul 12 05:35:36 PM PDT 24 525303165 ps
T846 /workspace/coverage/default/27.lc_ctrl_state_post_trans.1095349880 Jul 12 05:36:37 PM PDT 24 Jul 12 05:36:46 PM PDT 24 82401877 ps
T847 /workspace/coverage/default/14.lc_ctrl_jtag_errors.3536421401 Jul 12 05:37:06 PM PDT 24 Jul 12 05:38:37 PM PDT 24 13191588095 ps
T848 /workspace/coverage/default/2.lc_ctrl_smoke.4127874551 Jul 12 05:35:22 PM PDT 24 Jul 12 05:35:25 PM PDT 24 22952955 ps
T849 /workspace/coverage/default/17.lc_ctrl_state_post_trans.729750432 Jul 12 05:36:07 PM PDT 24 Jul 12 05:36:15 PM PDT 24 70477800 ps
T850 /workspace/coverage/default/45.lc_ctrl_alert_test.748301171 Jul 12 05:37:04 PM PDT 24 Jul 12 05:37:10 PM PDT 24 79523833 ps
T851 /workspace/coverage/default/21.lc_ctrl_smoke.2637565416 Jul 12 05:36:20 PM PDT 24 Jul 12 05:36:22 PM PDT 24 36823521 ps
T852 /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1368587963 Jul 12 05:36:24 PM PDT 24 Jul 12 05:36:39 PM PDT 24 966711856 ps
T853 /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1079462866 Jul 12 05:35:58 PM PDT 24 Jul 12 05:36:03 PM PDT 24 796573734 ps
T854 /workspace/coverage/default/29.lc_ctrl_state_failure.2147717962 Jul 12 05:36:33 PM PDT 24 Jul 12 05:37:01 PM PDT 24 728052396 ps
T855 /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3305808015 Jul 12 05:35:41 PM PDT 24 Jul 12 05:35:44 PM PDT 24 33460014 ps
T856 /workspace/coverage/default/32.lc_ctrl_errors.3918519718 Jul 12 05:37:06 PM PDT 24 Jul 12 05:37:27 PM PDT 24 1253539913 ps
T857 /workspace/coverage/default/9.lc_ctrl_sec_mubi.1655025844 Jul 12 05:35:43 PM PDT 24 Jul 12 05:35:58 PM PDT 24 299979132 ps
T858 /workspace/coverage/default/2.lc_ctrl_alert_test.2088576413 Jul 12 05:35:30 PM PDT 24 Jul 12 05:35:32 PM PDT 24 44908055 ps
T859 /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3095829220 Jul 12 05:35:55 PM PDT 24 Jul 12 05:36:10 PM PDT 24 1776726224 ps
T860 /workspace/coverage/default/22.lc_ctrl_jtag_access.2747138009 Jul 12 05:36:32 PM PDT 24 Jul 12 05:36:39 PM PDT 24 632124314 ps
T861 /workspace/coverage/default/26.lc_ctrl_sec_mubi.416035481 Jul 12 06:28:42 PM PDT 24 Jul 12 06:28:56 PM PDT 24 583990762 ps
T70 /workspace/coverage/default/1.lc_ctrl_smoke.1648782585 Jul 12 05:35:23 PM PDT 24 Jul 12 05:35:26 PM PDT 24 39549604 ps
T862 /workspace/coverage/default/31.lc_ctrl_stress_all.2214204583 Jul 12 05:37:01 PM PDT 24 Jul 12 05:40:06 PM PDT 24 53546975551 ps
T863 /workspace/coverage/default/19.lc_ctrl_state_failure.3542547700 Jul 12 05:36:32 PM PDT 24 Jul 12 05:37:09 PM PDT 24 1142784118 ps
T864 /workspace/coverage/default/8.lc_ctrl_alert_test.1356192191 Jul 12 05:35:54 PM PDT 24 Jul 12 05:35:57 PM PDT 24 14629077 ps
T865 /workspace/coverage/default/40.lc_ctrl_state_post_trans.886162164 Jul 12 05:37:06 PM PDT 24 Jul 12 05:37:20 PM PDT 24 365662937 ps
T866 /workspace/coverage/default/11.lc_ctrl_sec_mubi.1256312670 Jul 12 05:35:53 PM PDT 24 Jul 12 05:36:04 PM PDT 24 1046034651 ps
T867 /workspace/coverage/default/36.lc_ctrl_state_post_trans.1622353919 Jul 12 05:36:49 PM PDT 24 Jul 12 05:36:56 PM PDT 24 120301940 ps
T122 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1334877856 Jul 12 06:07:38 PM PDT 24 Jul 12 06:08:32 PM PDT 24 15851662 ps
T123 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.762667527 Jul 12 06:07:13 PM PDT 24 Jul 12 06:07:53 PM PDT 24 843234321 ps
T112 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1969918699 Jul 12 06:07:10 PM PDT 24 Jul 12 06:07:39 PM PDT 24 31932800 ps
T139 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3317427148 Jul 12 06:06:52 PM PDT 24 Jul 12 06:07:09 PM PDT 24 58250593 ps
T145 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.4133808861 Jul 12 06:07:10 PM PDT 24 Jul 12 06:08:28 PM PDT 24 4558786572 ps
T868 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2955107392 Jul 12 06:06:45 PM PDT 24 Jul 12 06:06:54 PM PDT 24 16618563 ps
T144 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2151525367 Jul 12 06:06:43 PM PDT 24 Jul 12 06:06:52 PM PDT 24 130049745 ps
T108 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.4078407025 Jul 12 06:07:36 PM PDT 24 Jul 12 06:08:30 PM PDT 24 111035108 ps
T109 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3890412725 Jul 12 06:07:16 PM PDT 24 Jul 12 06:07:53 PM PDT 24 88955573 ps
T110 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1520697623 Jul 12 06:07:16 PM PDT 24 Jul 12 06:07:51 PM PDT 24 115009837 ps
T115 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.629985922 Jul 12 06:07:31 PM PDT 24 Jul 12 06:08:22 PM PDT 24 79031016 ps
T196 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3144534624 Jul 12 06:07:05 PM PDT 24 Jul 12 06:07:26 PM PDT 24 14099126 ps
T204 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.150241428 Jul 12 06:06:44 PM PDT 24 Jul 12 06:06:53 PM PDT 24 24245886 ps
T215 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1910693017 Jul 12 06:06:52 PM PDT 24 Jul 12 06:07:13 PM PDT 24 707315068 ps
T140 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2024169213 Jul 12 06:07:10 PM PDT 24 Jul 12 06:07:41 PM PDT 24 108804906 ps
T869 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1253304889 Jul 12 06:07:46 PM PDT 24 Jul 12 06:08:43 PM PDT 24 50752173 ps
T197 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2264372383 Jul 12 06:07:37 PM PDT 24 Jul 12 06:08:27 PM PDT 24 13977817 ps
T172 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.324932498 Jul 12 06:07:43 PM PDT 24 Jul 12 06:08:42 PM PDT 24 50508759 ps
T126 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1485195124 Jul 12 06:07:14 PM PDT 24 Jul 12 06:07:50 PM PDT 24 430522611 ps
T113 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.680146811 Jul 12 06:07:31 PM PDT 24 Jul 12 06:08:23 PM PDT 24 31027501 ps
T205 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.380270998 Jul 12 06:06:50 PM PDT 24 Jul 12 06:07:05 PM PDT 24 19410721 ps
T120 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1613289540 Jul 12 06:07:34 PM PDT 24 Jul 12 06:08:30 PM PDT 24 397370116 ps
T206 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3883136733 Jul 12 06:07:11 PM PDT 24 Jul 12 06:07:41 PM PDT 24 100907538 ps
T173 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2121606256 Jul 12 06:07:23 PM PDT 24 Jul 12 06:08:04 PM PDT 24 33756337 ps
T159 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.29704821 Jul 12 06:07:23 PM PDT 24 Jul 12 06:08:04 PM PDT 24 32681359 ps
T870 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2369047761 Jul 12 06:06:55 PM PDT 24 Jul 12 06:07:12 PM PDT 24 12552848 ps
T141 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2300964534 Jul 12 06:06:58 PM PDT 24 Jul 12 06:07:17 PM PDT 24 87081399 ps
T871 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.4221538159 Jul 12 06:07:17 PM PDT 24 Jul 12 06:07:57 PM PDT 24 549737021 ps
T207 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3672426155 Jul 12 06:07:39 PM PDT 24 Jul 12 06:08:32 PM PDT 24 20859281 ps
T208 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2073643621 Jul 12 06:07:18 PM PDT 24 Jul 12 06:07:52 PM PDT 24 23959191 ps
T114 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.268978228 Jul 12 06:07:23 PM PDT 24 Jul 12 06:08:05 PM PDT 24 244678478 ps
T872 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1374585265 Jul 12 06:06:50 PM PDT 24 Jul 12 06:07:05 PM PDT 24 306557458 ps
T160 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.16052878 Jul 12 06:07:11 PM PDT 24 Jul 12 06:07:41 PM PDT 24 70007792 ps
T161 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1610541487 Jul 12 06:07:31 PM PDT 24 Jul 12 06:08:22 PM PDT 24 37180807 ps
T873 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.363806994 Jul 12 06:07:37 PM PDT 24 Jul 12 06:08:27 PM PDT 24 135169681 ps
T209 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2723726581 Jul 12 06:06:44 PM PDT 24 Jul 12 06:06:55 PM PDT 24 137266402 ps
T136 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.448857183 Jul 12 06:06:45 PM PDT 24 Jul 12 06:06:55 PM PDT 24 348451419 ps
T162 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2867928917 Jul 12 06:06:56 PM PDT 24 Jul 12 06:07:13 PM PDT 24 29442179 ps
T874 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.592255450 Jul 12 06:06:58 PM PDT 24 Jul 12 06:07:23 PM PDT 24 697633855 ps
T875 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3620967767 Jul 12 06:07:04 PM PDT 24 Jul 12 06:07:24 PM PDT 24 93717920 ps
T163 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3191924807 Jul 12 06:06:51 PM PDT 24 Jul 12 06:07:06 PM PDT 24 15656659 ps
T142 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.359259045 Jul 12 06:06:59 PM PDT 24 Jul 12 06:07:18 PM PDT 24 201056527 ps
T131 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3463191588 Jul 12 06:07:07 PM PDT 24 Jul 12 06:07:30 PM PDT 24 112491355 ps
T121 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3811204295 Jul 12 06:07:16 PM PDT 24 Jul 12 06:07:49 PM PDT 24 44514407 ps
T876 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3171643277 Jul 12 06:07:29 PM PDT 24 Jul 12 06:08:16 PM PDT 24 173407087 ps
T877 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.4051241263 Jul 12 06:06:59 PM PDT 24 Jul 12 06:07:24 PM PDT 24 2970608490 ps
T878 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.4282300935 Jul 12 06:07:18 PM PDT 24 Jul 12 06:07:52 PM PDT 24 28224302 ps
T879 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.507414683 Jul 12 06:07:05 PM PDT 24 Jul 12 06:07:26 PM PDT 24 62121596 ps
T880 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.753675500 Jul 12 06:06:57 PM PDT 24 Jul 12 06:07:16 PM PDT 24 166767377 ps
T881 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.896015143 Jul 12 06:07:32 PM PDT 24 Jul 12 06:08:25 PM PDT 24 48124947 ps
T210 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1494586284 Jul 12 06:07:03 PM PDT 24 Jul 12 06:07:23 PM PDT 24 164019276 ps
T882 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.487234559 Jul 12 06:06:50 PM PDT 24 Jul 12 06:07:07 PM PDT 24 368404308 ps
T883 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2156141880 Jul 12 06:07:18 PM PDT 24 Jul 12 06:07:52 PM PDT 24 168534573 ps
T884 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2755444866 Jul 12 06:07:27 PM PDT 24 Jul 12 06:08:12 PM PDT 24 42116589 ps
T211 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.73488638 Jul 12 06:07:16 PM PDT 24 Jul 12 06:07:48 PM PDT 24 264417135 ps
T198 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.133874306 Jul 12 06:06:57 PM PDT 24 Jul 12 06:07:15 PM PDT 24 149087107 ps
T116 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3757443262 Jul 12 06:07:37 PM PDT 24 Jul 12 06:08:28 PM PDT 24 156629076 ps
T138 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1581578503 Jul 12 06:07:44 PM PDT 24 Jul 12 06:08:46 PM PDT 24 622624351 ps
T118 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1817390438 Jul 12 06:07:14 PM PDT 24 Jul 12 06:07:49 PM PDT 24 97181097 ps
T117 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3923854098 Jul 12 06:06:57 PM PDT 24 Jul 12 06:07:16 PM PDT 24 41410272 ps
T885 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3143648124 Jul 12 06:07:37 PM PDT 24 Jul 12 06:08:27 PM PDT 24 74142619 ps
T212 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2464068101 Jul 12 06:07:31 PM PDT 24 Jul 12 06:08:23 PM PDT 24 88154113 ps
T886 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.4011400040 Jul 12 06:07:16 PM PDT 24 Jul 12 06:08:08 PM PDT 24 4130520263 ps
T887 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4280070761 Jul 12 06:07:25 PM PDT 24 Jul 12 06:08:09 PM PDT 24 60946462 ps
T888 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.392295372 Jul 12 06:07:07 PM PDT 24 Jul 12 06:07:31 PM PDT 24 85600672 ps
T889 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2386439783 Jul 12 06:06:45 PM PDT 24 Jul 12 06:06:57 PM PDT 24 74771796 ps
T890 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1932623989 Jul 12 06:06:59 PM PDT 24 Jul 12 06:07:18 PM PDT 24 394974983 ps
T891 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2746125595 Jul 12 06:07:17 PM PDT 24 Jul 12 06:07:57 PM PDT 24 873341124 ps
T892 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.270295959 Jul 12 06:07:25 PM PDT 24 Jul 12 06:08:09 PM PDT 24 47288996 ps
T199 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2599994968 Jul 12 06:07:06 PM PDT 24 Jul 12 06:07:30 PM PDT 24 20328454 ps
T893 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3211483260 Jul 12 06:07:07 PM PDT 24 Jul 12 06:07:30 PM PDT 24 20681024 ps
T894 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.386107145 Jul 12 06:07:05 PM PDT 24 Jul 12 06:07:29 PM PDT 24 837609585 ps
T119 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3638099793 Jul 12 06:06:57 PM PDT 24 Jul 12 06:07:15 PM PDT 24 130709425 ps
T895 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.837951422 Jul 12 06:06:43 PM PDT 24 Jul 12 06:06:52 PM PDT 24 107194128 ps
T896 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.743633534 Jul 12 06:07:31 PM PDT 24 Jul 12 06:08:22 PM PDT 24 172549911 ps
T897 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2854858130 Jul 12 06:06:47 PM PDT 24 Jul 12 06:06:59 PM PDT 24 28795082 ps
T898 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3099824228 Jul 12 06:06:52 PM PDT 24 Jul 12 06:07:15 PM PDT 24 3117003918 ps
T899 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1321053108 Jul 12 06:06:34 PM PDT 24 Jul 12 06:06:37 PM PDT 24 124508324 ps
T900 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.659249461 Jul 12 06:07:07 PM PDT 24 Jul 12 06:07:30 PM PDT 24 113916889 ps
T901 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.429613128 Jul 12 06:07:16 PM PDT 24 Jul 12 06:07:49 PM PDT 24 65830185 ps
T902 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.962303110 Jul 12 06:06:57 PM PDT 24 Jul 12 06:07:15 PM PDT 24 206145514 ps
T903 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1118925217 Jul 12 06:07:25 PM PDT 24 Jul 12 06:08:10 PM PDT 24 537017993 ps
T904 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2822523032 Jul 12 06:07:15 PM PDT 24 Jul 12 06:07:49 PM PDT 24 464512067 ps
T905 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3411755773 Jul 12 06:07:37 PM PDT 24 Jul 12 06:08:31 PM PDT 24 78130722 ps
T906 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.4198908487 Jul 12 06:06:58 PM PDT 24 Jul 12 06:07:16 PM PDT 24 371778939 ps
T907 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.810962109 Jul 12 06:07:33 PM PDT 24 Jul 12 06:08:23 PM PDT 24 20425085 ps
T908 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.266430210 Jul 12 06:07:25 PM PDT 24 Jul 12 06:08:09 PM PDT 24 162074792 ps
T909 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2970937054 Jul 12 06:07:19 PM PDT 24 Jul 12 06:08:03 PM PDT 24 4328105683 ps
T910 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2323877723 Jul 12 06:07:17 PM PDT 24 Jul 12 06:07:51 PM PDT 24 15427682 ps
T911 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2184500684 Jul 12 06:07:06 PM PDT 24 Jul 12 06:08:25 PM PDT 24 2599701124 ps
T912 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1464547280 Jul 12 06:06:59 PM PDT 24 Jul 12 06:07:19 PM PDT 24 118947298 ps
T913 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2265159654 Jul 12 06:07:16 PM PDT 24 Jul 12 06:07:52 PM PDT 24 185625107 ps
T914 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3045791796 Jul 12 06:07:12 PM PDT 24 Jul 12 06:07:41 PM PDT 24 37515218 ps
T915 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2559674630 Jul 12 06:07:11 PM PDT 24 Jul 12 06:07:39 PM PDT 24 16619304 ps
T127 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1174493544 Jul 12 06:07:43 PM PDT 24 Jul 12 06:08:39 PM PDT 24 153227934 ps
T916 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2043387010 Jul 12 06:07:24 PM PDT 24 Jul 12 06:08:09 PM PDT 24 259902192 ps
T917 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1947658276 Jul 12 06:06:51 PM PDT 24 Jul 12 06:07:08 PM PDT 24 50823976 ps
T918 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2366944665 Jul 12 06:07:39 PM PDT 24 Jul 12 06:08:35 PM PDT 24 458890786 ps
T919 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3977775530 Jul 12 06:07:24 PM PDT 24 Jul 12 06:08:04 PM PDT 24 20796707 ps
T920 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.44181422 Jul 12 06:06:55 PM PDT 24 Jul 12 06:07:13 PM PDT 24 54975784 ps
T921 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1891244833 Jul 12 06:07:05 PM PDT 24 Jul 12 06:07:27 PM PDT 24 256465362 ps
T922 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3236380271 Jul 12 06:07:03 PM PDT 24 Jul 12 06:07:37 PM PDT 24 1654676637 ps
T923 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3902328388 Jul 12 06:06:46 PM PDT 24 Jul 12 06:06:59 PM PDT 24 727658331 ps
T924 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3352272188 Jul 12 06:07:16 PM PDT 24 Jul 12 06:07:51 PM PDT 24 34173873 ps
T925 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2129021319 Jul 12 06:06:51 PM PDT 24 Jul 12 06:07:08 PM PDT 24 215551278 ps
T926 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.227730384 Jul 12 06:06:42 PM PDT 24 Jul 12 06:07:13 PM PDT 24 11102489608 ps
T927 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1723706623 Jul 12 06:07:48 PM PDT 24 Jul 12 06:08:47 PM PDT 24 91282836 ps
T200 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.770297473 Jul 12 06:07:06 PM PDT 24 Jul 12 06:07:30 PM PDT 24 39296942 ps
T928 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3177715386 Jul 12 06:07:19 PM PDT 24 Jul 12 06:07:57 PM PDT 24 53604441 ps
T929 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1755252215 Jul 12 06:07:09 PM PDT 24 Jul 12 06:07:37 PM PDT 24 194376776 ps
T930 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3560159097 Jul 12 06:06:45 PM PDT 24 Jul 12 06:07:21 PM PDT 24 6312498718 ps
T931 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2127840416 Jul 12 06:06:52 PM PDT 24 Jul 12 06:07:08 PM PDT 24 67948388 ps
T124 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3671859093 Jul 12 06:07:30 PM PDT 24 Jul 12 06:08:19 PM PDT 24 309842027 ps
T932 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2898870751 Jul 12 06:07:11 PM PDT 24 Jul 12 06:07:40 PM PDT 24 790359647 ps
T128 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2848318369 Jul 12 06:07:03 PM PDT 24 Jul 12 06:07:24 PM PDT 24 67002428 ps
T201 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3170257374 Jul 12 06:06:46 PM PDT 24 Jul 12 06:06:57 PM PDT 24 115363294 ps
T933 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1441730547 Jul 12 06:06:44 PM PDT 24 Jul 12 06:06:55 PM PDT 24 34631375 ps
T934 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2583882615 Jul 12 06:07:11 PM PDT 24 Jul 12 06:07:40 PM PDT 24 153394432 ps
T935 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2873576682 Jul 12 06:06:52 PM PDT 24 Jul 12 06:07:09 PM PDT 24 22071881 ps
T936 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.258750866 Jul 12 06:06:42 PM PDT 24 Jul 12 06:07:10 PM PDT 24 2972130248 ps
T135 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2635382977 Jul 12 06:06:54 PM PDT 24 Jul 12 06:07:12 PM PDT 24 479469000 ps
T937 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1107046403 Jul 12 06:07:37 PM PDT 24 Jul 12 06:08:32 PM PDT 24 44545645 ps
T938 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1485689829 Jul 12 06:07:04 PM PDT 24 Jul 12 06:07:24 PM PDT 24 32849049 ps
T939 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.301227667 Jul 12 06:07:15 PM PDT 24 Jul 12 06:07:48 PM PDT 24 203720802 ps
T940 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1089524788 Jul 12 06:07:25 PM PDT 24 Jul 12 06:08:08 PM PDT 24 173434763 ps
T125 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1109311234 Jul 12 06:07:38 PM PDT 24 Jul 12 06:08:34 PM PDT 24 173445762 ps
T132 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2085378101 Jul 12 06:07:26 PM PDT 24 Jul 12 06:08:10 PM PDT 24 149885725 ps
T137 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.228378992 Jul 12 06:07:39 PM PDT 24 Jul 12 06:08:33 PM PDT 24 241813738 ps
T941 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1416584164 Jul 12 06:07:25 PM PDT 24 Jul 12 06:08:12 PM PDT 24 266614512 ps
T942 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1368867565 Jul 12 06:06:57 PM PDT 24 Jul 12 06:07:16 PM PDT 24 71377714 ps
T943 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3735986305 Jul 12 06:06:57 PM PDT 24 Jul 12 06:07:16 PM PDT 24 286240880 ps
T944 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1483194771 Jul 12 06:07:03 PM PDT 24 Jul 12 06:07:31 PM PDT 24 1526577952 ps
T945 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1255038344 Jul 12 06:07:01 PM PDT 24 Jul 12 06:07:20 PM PDT 24 67134018 ps
T946 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.218289275 Jul 12 06:07:16 PM PDT 24 Jul 12 06:07:52 PM PDT 24 142038549 ps
T947 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1019292473 Jul 12 06:07:01 PM PDT 24 Jul 12 06:07:20 PM PDT 24 74920174 ps
T948 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1973131512 Jul 12 06:07:31 PM PDT 24 Jul 12 06:08:22 PM PDT 24 125630452 ps
T202 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.740753632 Jul 12 06:07:33 PM PDT 24 Jul 12 06:08:23 PM PDT 24 47811208 ps
T949 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2505580540 Jul 12 06:06:37 PM PDT 24 Jul 12 06:06:45 PM PDT 24 328830043 ps
T950 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3385229850 Jul 12 06:06:59 PM PDT 24 Jul 12 06:07:18 PM PDT 24 28372167 ps
T951 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.100891834 Jul 12 06:07:22 PM PDT 24 Jul 12 06:08:04 PM PDT 24 26153137 ps
T129 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.4112597234 Jul 12 06:07:25 PM PDT 24 Jul 12 06:08:10 PM PDT 24 284586919 ps
T952 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.269505253 Jul 12 06:06:58 PM PDT 24 Jul 12 06:07:16 PM PDT 24 12878329 ps
T953 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2280849153 Jul 12 06:07:19 PM PDT 24 Jul 12 06:07:54 PM PDT 24 54851868 ps
T954 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3500452122 Jul 12 06:07:37 PM PDT 24 Jul 12 06:08:32 PM PDT 24 74435167 ps
T955 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3694321844 Jul 12 06:07:08 PM PDT 24 Jul 12 06:07:33 PM PDT 24 47875365 ps
T956 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2937078983 Jul 12 06:07:44 PM PDT 24 Jul 12 06:08:42 PM PDT 24 16163532 ps
T957 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.896022125 Jul 12 06:06:50 PM PDT 24 Jul 12 06:07:07 PM PDT 24 138224843 ps
T958 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1091560908 Jul 12 06:06:51 PM PDT 24 Jul 12 06:07:07 PM PDT 24 158921473 ps
T133 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.4032675622 Jul 12 06:06:58 PM PDT 24 Jul 12 06:07:17 PM PDT 24 357532180 ps
T959 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.381993426 Jul 12 06:07:46 PM PDT 24 Jul 12 06:08:47 PM PDT 24 39356709 ps
T223 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3502709764 Jul 12 06:07:31 PM PDT 24 Jul 12 06:08:23 PM PDT 24 63091886 ps
T960 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1253351433 Jul 12 06:07:18 PM PDT 24 Jul 12 06:07:54 PM PDT 24 351435910 ps
T961 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3588379541 Jul 12 06:07:04 PM PDT 24 Jul 12 06:07:27 PM PDT 24 150192675 ps
T962 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2188660808 Jul 12 06:07:11 PM PDT 24 Jul 12 06:07:41 PM PDT 24 29928325 ps
T963 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.408940698 Jul 12 06:06:52 PM PDT 24 Jul 12 06:07:11 PM PDT 24 115522453 ps
T964 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.914231081 Jul 12 06:07:30 PM PDT 24 Jul 12 06:08:17 PM PDT 24 13759883 ps
T965 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.827293651 Jul 12 06:07:15 PM PDT 24 Jul 12 06:07:52 PM PDT 24 190839253 ps
T966 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.456002240 Jul 12 06:07:37 PM PDT 24 Jul 12 06:08:28 PM PDT 24 19973568 ps
T967 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3502321387 Jul 12 06:07:35 PM PDT 24 Jul 12 06:08:27 PM PDT 24 33415895 ps
T968 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1264044751 Jul 12 06:07:45 PM PDT 24 Jul 12 06:08:43 PM PDT 24 85770627 ps
T969 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3936890423 Jul 12 06:06:44 PM PDT 24 Jul 12 06:06:53 PM PDT 24 324576169 ps
T970 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1599654216 Jul 12 06:06:59 PM PDT 24 Jul 12 06:07:18 PM PDT 24 65253224 ps
T971 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1943444280 Jul 12 06:07:19 PM PDT 24 Jul 12 06:07:56 PM PDT 24 124323314 ps
T972 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.4243901887 Jul 12 06:06:47 PM PDT 24 Jul 12 06:07:21 PM PDT 24 1548717437 ps
T973 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.4265820252 Jul 12 06:07:10 PM PDT 24 Jul 12 06:07:41 PM PDT 24 1298091182 ps
T974 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.969188118 Jul 12 06:07:46 PM PDT 24 Jul 12 06:08:43 PM PDT 24 40443983 ps
T975 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2488526333 Jul 12 06:06:52 PM PDT 24 Jul 12 06:07:08 PM PDT 24 203240319 ps
T976 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.102100832 Jul 12 06:06:54 PM PDT 24 Jul 12 06:07:12 PM PDT 24 32251993 ps
T977 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1485025770 Jul 12 06:07:24 PM PDT 24 Jul 12 06:08:07 PM PDT 24 20252134 ps
T978 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1357157740 Jul 12 06:06:43 PM PDT 24 Jul 12 06:06:52 PM PDT 24 68203718 ps
T979 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1232623846 Jul 12 06:07:08 PM PDT 24 Jul 12 06:07:33 PM PDT 24 49666531 ps
T980 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2753704225 Jul 12 06:07:03 PM PDT 24 Jul 12 06:07:29 PM PDT 24 295215202 ps
T981 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1905488379 Jul 12 06:07:04 PM PDT 24 Jul 12 06:07:26 PM PDT 24 59414046 ps
T982 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1050474475 Jul 12 06:07:24 PM PDT 24 Jul 12 06:08:04 PM PDT 24 73443326 ps
T983 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.109097703 Jul 12 06:07:15 PM PDT 24 Jul 12 06:07:49 PM PDT 24 92790991 ps
T984 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.304898139 Jul 12 06:06:53 PM PDT 24 Jul 12 06:07:10 PM PDT 24 46443706 ps
T985 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3820446324 Jul 12 06:07:10 PM PDT 24 Jul 12 06:07:39 PM PDT 24 103395606 ps
T986 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.196691476 Jul 12 06:07:19 PM PDT 24 Jul 12 06:07:56 PM PDT 24 392658554 ps
T987 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.35767397 Jul 12 06:07:03 PM PDT 24 Jul 12 06:07:23 PM PDT 24 45690291 ps
T988 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1697131319 Jul 12 06:07:11 PM PDT 24 Jul 12 06:07:41 PM PDT 24 28099132 ps
T989 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3854747405 Jul 12 06:06:44 PM PDT 24 Jul 12 06:06:54 PM PDT 24 133162192 ps
T130 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.111200580 Jul 12 06:07:24 PM PDT 24 Jul 12 06:08:08 PM PDT 24 42622239 ps
T990 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.625003996 Jul 12 06:07:23 PM PDT 24 Jul 12 06:08:06 PM PDT 24 71049466 ps
T203 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1385652094 Jul 12 06:07:30 PM PDT 24 Jul 12 06:08:17 PM PDT 24 18069727 ps
T134 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3129701814 Jul 12 06:07:18 PM PDT 24 Jul 12 06:07:53 PM PDT 24 44305547 ps

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.1442899120
Short name T12
Test name
Test status
Simulation time 273840841 ps
CPU time 13.64 seconds
Started Jul 12 05:35:12 PM PDT 24
Finished Jul 12 05:35:29 PM PDT 24
Peak memory 225968 kb
Host smart-c4f45d9a-f808-45f7-bace-00050936c963
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442899120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.1442899120
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.4188589810
Short name T26
Test name
Test status
Simulation time 8426958269 ps
CPU time 74.86 seconds
Started Jul 12 05:36:17 PM PDT 24
Finished Jul 12 05:37:33 PM PDT 24
Peak memory 250960 kb
Host smart-3dc8dfa2-d330-4916-b3ba-498626eb88de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188589810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.4188589810
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.53774223
Short name T37
Test name
Test status
Simulation time 383504341 ps
CPU time 12.22 seconds
Started Jul 12 05:37:48 PM PDT 24
Finished Jul 12 05:38:14 PM PDT 24
Peak memory 225512 kb
Host smart-225e544e-cf8a-4c8e-8d92-d77f716c5e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53774223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.53774223
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.1224204575
Short name T46
Test name
Test status
Simulation time 15933882438 ps
CPU time 405.71 seconds
Started Jul 12 05:37:06 PM PDT 24
Finished Jul 12 05:43:57 PM PDT 24
Peak memory 251032 kb
Host smart-f746686b-363f-435d-8a2e-bf05ab558dc7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1224204575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.1224204575
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.629985922
Short name T115
Test name
Test status
Simulation time 79031016 ps
CPU time 1.52 seconds
Started Jul 12 06:07:31 PM PDT 24
Finished Jul 12 06:08:22 PM PDT 24
Peak memory 219604 kb
Host smart-8ff2b56a-5eeb-465a-b4f1-360a03b012cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629985922 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.629985922
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.317130648
Short name T13
Test name
Test status
Simulation time 1432967567 ps
CPU time 10.04 seconds
Started Jul 12 05:37:23 PM PDT 24
Finished Jul 12 05:37:40 PM PDT 24
Peak memory 225564 kb
Host smart-290f0d40-646d-4a37-8a99-9ca1fdc1d95d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317130648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.317130648
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.1518223015
Short name T90
Test name
Test status
Simulation time 73487787286 ps
CPU time 1411.61 seconds
Started Jul 12 05:36:15 PM PDT 24
Finished Jul 12 05:59:48 PM PDT 24
Peak memory 529524 kb
Host smart-f0b42b92-d475-4ae9-8b06-e06eeca3ee76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1518223015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.1518223015
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.50107668
Short name T51
Test name
Test status
Simulation time 873399227 ps
CPU time 34.66 seconds
Started Jul 12 05:35:13 PM PDT 24
Finished Jul 12 05:35:51 PM PDT 24
Peak memory 283188 kb
Host smart-cf0cba1b-98f4-4c2a-ad88-64d9bf323cdb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50107668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.50107668
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.303134991
Short name T21
Test name
Test status
Simulation time 277421346 ps
CPU time 11.84 seconds
Started Jul 12 05:35:59 PM PDT 24
Finished Jul 12 05:36:13 PM PDT 24
Peak memory 225984 kb
Host smart-d8c0ea8a-3849-49d0-9300-0730db828a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303134991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.303134991
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.3321082710
Short name T9
Test name
Test status
Simulation time 759911793 ps
CPU time 7.46 seconds
Started Jul 12 05:36:30 PM PDT 24
Finished Jul 12 05:36:41 PM PDT 24
Peak memory 217212 kb
Host smart-1a0ae46c-9a57-4949-a742-b1b706e34408
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321082710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.3321082710
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.1121897493
Short name T107
Test name
Test status
Simulation time 31026592247 ps
CPU time 1401.92 seconds
Started Jul 12 05:35:13 PM PDT 24
Finished Jul 12 05:58:37 PM PDT 24
Peak memory 644312 kb
Host smart-88f2ec30-2139-44e0-a798-327bf6a98c73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1121897493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.1121897493
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1520697623
Short name T110
Test name
Test status
Simulation time 115009837 ps
CPU time 4.09 seconds
Started Jul 12 06:07:16 PM PDT 24
Finished Jul 12 06:07:51 PM PDT 24
Peak memory 217496 kb
Host smart-56f70d64-6d49-447e-bab4-d555a54fc17e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520697623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.1520697623
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.56458338
Short name T35
Test name
Test status
Simulation time 20465554 ps
CPU time 0.95 seconds
Started Jul 12 05:37:06 PM PDT 24
Finished Jul 12 05:37:13 PM PDT 24
Peak memory 208836 kb
Host smart-b1f80258-be24-4501-bbbb-0b4e9746f1b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56458338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.56458338
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3191924807
Short name T163
Test name
Test status
Simulation time 15656659 ps
CPU time 0.95 seconds
Started Jul 12 06:06:51 PM PDT 24
Finished Jul 12 06:07:06 PM PDT 24
Peak memory 209012 kb
Host smart-b845ba93-8b1d-42d9-99be-57c29de872e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191924807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.3191924807
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2300964534
Short name T141
Test name
Test status
Simulation time 87081399 ps
CPU time 2.03 seconds
Started Jul 12 06:06:58 PM PDT 24
Finished Jul 12 06:07:17 PM PDT 24
Peak memory 217644 kb
Host smart-5cdca82d-680a-4762-8d58-5134154cfc66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230096
4534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2300964534
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2010635211
Short name T7
Test name
Test status
Simulation time 2822803960 ps
CPU time 89.09 seconds
Started Jul 12 05:35:38 PM PDT 24
Finished Jul 12 05:37:10 PM PDT 24
Peak memory 283676 kb
Host smart-7630e905-4ec8-441d-acd3-e3a062b94b27
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010635211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2010635211
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.4078407025
Short name T108
Test name
Test status
Simulation time 111035108 ps
CPU time 4.13 seconds
Started Jul 12 06:07:36 PM PDT 24
Finished Jul 12 06:08:30 PM PDT 24
Peak memory 217432 kb
Host smart-f75bc2ed-af44-4c89-b58b-82de120b4008
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078407025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.4078407025
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2755444866
Short name T884
Test name
Test status
Simulation time 42116589 ps
CPU time 1.47 seconds
Started Jul 12 06:07:27 PM PDT 24
Finished Jul 12 06:08:12 PM PDT 24
Peak memory 217768 kb
Host smart-66201a10-4cad-4da8-bf6b-825590982215
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755444866 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.2755444866
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3129701814
Short name T134
Test name
Test status
Simulation time 44305547 ps
CPU time 1.88 seconds
Started Jul 12 06:07:18 PM PDT 24
Finished Jul 12 06:07:53 PM PDT 24
Peak memory 221992 kb
Host smart-ff3cad07-a6d4-4a28-a7f8-dacd56eaa563
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129701814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3129701814
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.268978228
Short name T114
Test name
Test status
Simulation time 244678478 ps
CPU time 3.13 seconds
Started Jul 12 06:07:23 PM PDT 24
Finished Jul 12 06:08:05 PM PDT 24
Peak memory 222416 kb
Host smart-a396f780-3b83-4750-a450-66c9fdb51b9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268978228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_
err.268978228
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2085378101
Short name T132
Test name
Test status
Simulation time 149885725 ps
CPU time 2.78 seconds
Started Jul 12 06:07:26 PM PDT 24
Finished Jul 12 06:08:10 PM PDT 24
Peak memory 222288 kb
Host smart-4f817032-aa7a-40fc-903e-5db8c5bd8b81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085378101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.2085378101
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.3880782243
Short name T1
Test name
Test status
Simulation time 214939854 ps
CPU time 18.33 seconds
Started Jul 12 05:36:59 PM PDT 24
Finished Jul 12 05:37:21 PM PDT 24
Peak memory 250808 kb
Host smart-cba45650-fafd-4c7e-8df9-51ee2051a3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880782243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3880782243
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.150241428
Short name T204
Test name
Test status
Simulation time 24245886 ps
CPU time 1.53 seconds
Started Jul 12 06:06:44 PM PDT 24
Finished Jul 12 06:06:53 PM PDT 24
Peak memory 211236 kb
Host smart-74eee798-5287-417f-b32f-7d83e6372dfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150241428 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.150241428
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3280856697
Short name T337
Test name
Test status
Simulation time 93412596 ps
CPU time 5.68 seconds
Started Jul 12 05:36:20 PM PDT 24
Finished Jul 12 05:36:27 PM PDT 24
Peak memory 214632 kb
Host smart-a5a22207-c1e2-4cc5-aa23-6cb86c22ff56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280856697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3280856697
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.2753044204
Short name T39
Test name
Test status
Simulation time 1322279593 ps
CPU time 11.75 seconds
Started Jul 12 05:36:49 PM PDT 24
Finished Jul 12 05:37:02 PM PDT 24
Peak memory 218340 kb
Host smart-e62e6771-ad5f-4f12-ae4d-3180e7f5b6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753044204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.2753044204
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.26176694
Short name T84
Test name
Test status
Simulation time 24872462 ps
CPU time 0.92 seconds
Started Jul 12 05:37:02 PM PDT 24
Finished Jul 12 05:37:07 PM PDT 24
Peak memory 213276 kb
Host smart-9a2f0241-e311-4c58-b6ca-77558cdae0b3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26176694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctr
l_volatile_unlock_smoke.26176694
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1109311234
Short name T125
Test name
Test status
Simulation time 173445762 ps
CPU time 3.54 seconds
Started Jul 12 06:07:38 PM PDT 24
Finished Jul 12 06:08:34 PM PDT 24
Peak memory 217444 kb
Host smart-9b4a4c64-ef5a-4675-86c6-b82305b9b7e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109311234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1109311234
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1581578503
Short name T138
Test name
Test status
Simulation time 622624351 ps
CPU time 5 seconds
Started Jul 12 06:07:44 PM PDT 24
Finished Jul 12 06:08:46 PM PDT 24
Peak memory 217472 kb
Host smart-c093e959-cdbf-4858-9ecb-f512e6151ca7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581578503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1581578503
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3463191588
Short name T131
Test name
Test status
Simulation time 112491355 ps
CPU time 1.86 seconds
Started Jul 12 06:07:07 PM PDT 24
Finished Jul 12 06:07:30 PM PDT 24
Peak memory 222008 kb
Host smart-8f39cd47-8161-40c0-8a70-3a012a4cb305
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463191588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.3463191588
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.835587208
Short name T221
Test name
Test status
Simulation time 13306324 ps
CPU time 1 seconds
Started Jul 12 05:35:13 PM PDT 24
Finished Jul 12 05:35:17 PM PDT 24
Peak memory 208948 kb
Host smart-7fbf818b-35ec-498d-8c70-08410fc9ac61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835587208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.835587208
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.731924388
Short name T219
Test name
Test status
Simulation time 10616852 ps
CPU time 0.84 seconds
Started Jul 12 05:35:24 PM PDT 24
Finished Jul 12 05:35:27 PM PDT 24
Peak memory 208652 kb
Host smart-28a88a46-f0da-49ef-a0bc-7f300338483f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731924388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.731924388
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2635382977
Short name T135
Test name
Test status
Simulation time 479469000 ps
CPU time 2.45 seconds
Started Jul 12 06:06:54 PM PDT 24
Finished Jul 12 06:07:12 PM PDT 24
Peak memory 217468 kb
Host smart-2b88b114-07a5-4287-a8f5-84e61383281f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635382977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2635382977
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1174493544
Short name T127
Test name
Test status
Simulation time 153227934 ps
CPU time 1.78 seconds
Started Jul 12 06:07:43 PM PDT 24
Finished Jul 12 06:08:39 PM PDT 24
Peak memory 221644 kb
Host smart-847956a4-2032-4578-a3a5-b972bc4d2787
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174493544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1174493544
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.4032675622
Short name T133
Test name
Test status
Simulation time 357532180 ps
CPU time 2.69 seconds
Started Jul 12 06:06:58 PM PDT 24
Finished Jul 12 06:07:17 PM PDT 24
Peak memory 217456 kb
Host smart-ee6bffd4-4e81-4635-943d-d99ffc19b369
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032675622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.4032675622
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.1564609299
Short name T49
Test name
Test status
Simulation time 14274364174 ps
CPU time 318.72 seconds
Started Jul 12 05:36:56 PM PDT 24
Finished Jul 12 05:42:19 PM PDT 24
Peak memory 251012 kb
Host smart-d8107173-b2b7-44fb-a5b9-073670dea37c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564609299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.1564609299
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.941779232
Short name T48
Test name
Test status
Simulation time 361028470 ps
CPU time 10.17 seconds
Started Jul 12 05:37:07 PM PDT 24
Finished Jul 12 05:37:23 PM PDT 24
Peak memory 225896 kb
Host smart-df33ec0c-24ed-4463-b3d0-5ae309746992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941779232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.941779232
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2270584282
Short name T5
Test name
Test status
Simulation time 1853716805 ps
CPU time 15.08 seconds
Started Jul 12 05:35:45 PM PDT 24
Finished Jul 12 05:36:04 PM PDT 24
Peak memory 250876 kb
Host smart-aa6d42eb-1b0e-45c2-8de7-66ed2a6e6ee1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270584282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.2270584282
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3130224927
Short name T6
Test name
Test status
Simulation time 3254208202 ps
CPU time 29.19 seconds
Started Jul 12 05:36:28 PM PDT 24
Finished Jul 12 05:36:59 PM PDT 24
Peak memory 244464 kb
Host smart-46cf9487-af63-40ad-883e-a8f516d29999
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130224927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3130224927
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3170257374
Short name T201
Test name
Test status
Simulation time 115363294 ps
CPU time 1.31 seconds
Started Jul 12 06:06:46 PM PDT 24
Finished Jul 12 06:06:57 PM PDT 24
Peak memory 217448 kb
Host smart-78713b8f-1bb4-425a-bc18-858f34742fe9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170257374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.3170257374
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3936890423
Short name T969
Test name
Test status
Simulation time 324576169 ps
CPU time 1.39 seconds
Started Jul 12 06:06:44 PM PDT 24
Finished Jul 12 06:06:53 PM PDT 24
Peak memory 217240 kb
Host smart-413eae8e-31e7-4904-a2ee-7275fb6888e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936890423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3936890423
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1357157740
Short name T978
Test name
Test status
Simulation time 68203718 ps
CPU time 1.02 seconds
Started Jul 12 06:06:43 PM PDT 24
Finished Jul 12 06:06:52 PM PDT 24
Peak memory 209840 kb
Host smart-35ff74ae-ba5b-436f-a62c-90fa338c4e22
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357157740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.1357157740
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1441730547
Short name T933
Test name
Test status
Simulation time 34631375 ps
CPU time 1.49 seconds
Started Jul 12 06:06:44 PM PDT 24
Finished Jul 12 06:06:55 PM PDT 24
Peak memory 218952 kb
Host smart-756c91a9-2a94-43fd-a7c2-775b6925c35d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441730547 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1441730547
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2955107392
Short name T868
Test name
Test status
Simulation time 16618563 ps
CPU time 0.85 seconds
Started Jul 12 06:06:45 PM PDT 24
Finished Jul 12 06:06:54 PM PDT 24
Peak memory 209176 kb
Host smart-224468ed-c365-4af0-bb98-d8dd356114af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955107392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2955107392
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3854747405
Short name T989
Test name
Test status
Simulation time 133162192 ps
CPU time 1.07 seconds
Started Jul 12 06:06:44 PM PDT 24
Finished Jul 12 06:06:54 PM PDT 24
Peak memory 209048 kb
Host smart-16fc73a7-4798-4831-862d-c7681288f595
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854747405 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3854747405
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.4243901887
Short name T972
Test name
Test status
Simulation time 1548717437 ps
CPU time 22.97 seconds
Started Jul 12 06:06:47 PM PDT 24
Finished Jul 12 06:07:21 PM PDT 24
Peak memory 217092 kb
Host smart-f8c11a50-008d-46d9-97ba-fa081f13f37d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243901887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.4243901887
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.227730384
Short name T926
Test name
Test status
Simulation time 11102489608 ps
CPU time 23.64 seconds
Started Jul 12 06:06:42 PM PDT 24
Finished Jul 12 06:07:13 PM PDT 24
Peak memory 209280 kb
Host smart-268e493f-6861-4434-8510-a6b44cd4474a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227730384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.227730384
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1321053108
Short name T899
Test name
Test status
Simulation time 124508324 ps
CPU time 1.82 seconds
Started Jul 12 06:06:34 PM PDT 24
Finished Jul 12 06:06:37 PM PDT 24
Peak memory 210860 kb
Host smart-96de2006-0cc2-4af5-a9f5-b300eab903f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321053108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1321053108
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3902328388
Short name T923
Test name
Test status
Simulation time 727658331 ps
CPU time 4.05 seconds
Started Jul 12 06:06:46 PM PDT 24
Finished Jul 12 06:06:59 PM PDT 24
Peak memory 218604 kb
Host smart-2c875156-6e18-47f3-a26e-1d933f450243
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390232
8388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3902328388
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2505580540
Short name T949
Test name
Test status
Simulation time 328830043 ps
CPU time 2.59 seconds
Started Jul 12 06:06:37 PM PDT 24
Finished Jul 12 06:06:45 PM PDT 24
Peak memory 217348 kb
Host smart-9bf6a688-1840-461b-8887-05675327e3ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505580540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2505580540
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2723726581
Short name T209
Test name
Test status
Simulation time 137266402 ps
CPU time 1.78 seconds
Started Jul 12 06:06:44 PM PDT 24
Finished Jul 12 06:06:55 PM PDT 24
Peak memory 211428 kb
Host smart-dde9ca8a-8d7e-4b6c-b83f-9fb291431ae2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723726581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.2723726581
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2386439783
Short name T889
Test name
Test status
Simulation time 74771796 ps
CPU time 3.03 seconds
Started Jul 12 06:06:45 PM PDT 24
Finished Jul 12 06:06:57 PM PDT 24
Peak memory 217768 kb
Host smart-09a84f7d-69cc-42db-856a-38b4d28f6525
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386439783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.2386439783
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.448857183
Short name T136
Test name
Test status
Simulation time 348451419 ps
CPU time 1.99 seconds
Started Jul 12 06:06:45 PM PDT 24
Finished Jul 12 06:06:55 PM PDT 24
Peak memory 222012 kb
Host smart-b35cce88-d8f0-4486-8684-bd9b2799429f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448857183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.448857183
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.753675500
Short name T880
Test name
Test status
Simulation time 166767377 ps
CPU time 1.26 seconds
Started Jul 12 06:06:57 PM PDT 24
Finished Jul 12 06:07:16 PM PDT 24
Peak memory 209300 kb
Host smart-38f4781e-ff41-43be-a9fe-97ee9def37f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753675500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.753675500
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1374585265
Short name T872
Test name
Test status
Simulation time 306557458 ps
CPU time 1.8 seconds
Started Jul 12 06:06:50 PM PDT 24
Finished Jul 12 06:07:05 PM PDT 24
Peak memory 217316 kb
Host smart-bdc4c78a-ae3f-4e75-b08b-14614f41aa3b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374585265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.1374585265
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3317427148
Short name T139
Test name
Test status
Simulation time 58250593 ps
CPU time 0.93 seconds
Started Jul 12 06:06:52 PM PDT 24
Finished Jul 12 06:07:09 PM PDT 24
Peak memory 209772 kb
Host smart-ccad1382-92df-4ad6-82b0-f31a63cc1377
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317427148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.3317427148
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2488526333
Short name T975
Test name
Test status
Simulation time 203240319 ps
CPU time 1.11 seconds
Started Jul 12 06:06:52 PM PDT 24
Finished Jul 12 06:07:08 PM PDT 24
Peak memory 218932 kb
Host smart-9e4dfa14-05b7-4a47-b0f8-672a54a4c8db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488526333 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2488526333
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.962303110
Short name T902
Test name
Test status
Simulation time 206145514 ps
CPU time 2.19 seconds
Started Jul 12 06:06:57 PM PDT 24
Finished Jul 12 06:07:15 PM PDT 24
Peak memory 209136 kb
Host smart-68d358cc-ae85-4dd7-bcb3-f927bfbb1fcb
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962303110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.962303110
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.258750866
Short name T936
Test name
Test status
Simulation time 2972130248 ps
CPU time 19.65 seconds
Started Jul 12 06:06:42 PM PDT 24
Finished Jul 12 06:07:10 PM PDT 24
Peak memory 209316 kb
Host smart-1551bac9-f886-4c93-a7dd-32923275d14d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258750866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.258750866
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3560159097
Short name T930
Test name
Test status
Simulation time 6312498718 ps
CPU time 26.79 seconds
Started Jul 12 06:06:45 PM PDT 24
Finished Jul 12 06:07:21 PM PDT 24
Peak memory 217488 kb
Host smart-53118813-9f31-4b32-a39c-d500bb733c8f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560159097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3560159097
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.837951422
Short name T895
Test name
Test status
Simulation time 107194128 ps
CPU time 1.83 seconds
Started Jul 12 06:06:43 PM PDT 24
Finished Jul 12 06:06:52 PM PDT 24
Peak memory 217412 kb
Host smart-7950c5f4-3d24-40c4-a6c9-d275d5d7d7ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837951422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.837951422
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1947658276
Short name T917
Test name
Test status
Simulation time 50823976 ps
CPU time 1.61 seconds
Started Jul 12 06:06:51 PM PDT 24
Finished Jul 12 06:07:08 PM PDT 24
Peak memory 218500 kb
Host smart-e8d309f1-8259-464f-a3f2-c10e5dc5ca73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194765
8276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1947658276
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2151525367
Short name T144
Test name
Test status
Simulation time 130049745 ps
CPU time 1.54 seconds
Started Jul 12 06:06:43 PM PDT 24
Finished Jul 12 06:06:52 PM PDT 24
Peak memory 209004 kb
Host smart-f011c13e-c1a3-440e-bfa5-b797cf59ffe2
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151525367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2151525367
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2854858130
Short name T897
Test name
Test status
Simulation time 28795082 ps
CPU time 1.17 seconds
Started Jul 12 06:06:47 PM PDT 24
Finished Jul 12 06:06:59 PM PDT 24
Peak memory 209308 kb
Host smart-e5df55c8-4e52-4ec3-b22b-c2dadc34b712
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854858130 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.2854858130
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.380270998
Short name T205
Test name
Test status
Simulation time 19410721 ps
CPU time 1.31 seconds
Started Jul 12 06:06:50 PM PDT 24
Finished Jul 12 06:07:05 PM PDT 24
Peak memory 209256 kb
Host smart-f8317f9b-ba9a-40c1-b077-12e0fd3970ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380270998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.380270998
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.102100832
Short name T976
Test name
Test status
Simulation time 32251993 ps
CPU time 1.96 seconds
Started Jul 12 06:06:54 PM PDT 24
Finished Jul 12 06:07:12 PM PDT 24
Peak memory 218432 kb
Host smart-28f7ca61-0963-499e-9726-be49e479e24d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102100832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.102100832
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.100891834
Short name T951
Test name
Test status
Simulation time 26153137 ps
CPU time 1.24 seconds
Started Jul 12 06:07:22 PM PDT 24
Finished Jul 12 06:08:04 PM PDT 24
Peak memory 218512 kb
Host smart-dd3a24d7-1e6e-412d-a60a-67ac1b35d254
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100891834 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.100891834
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1485025770
Short name T977
Test name
Test status
Simulation time 20252134 ps
CPU time 0.92 seconds
Started Jul 12 06:07:24 PM PDT 24
Finished Jul 12 06:08:07 PM PDT 24
Peak memory 209488 kb
Host smart-c8d95500-890a-4e5b-b746-603bfc345397
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485025770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1485025770
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1050474475
Short name T982
Test name
Test status
Simulation time 73443326 ps
CPU time 1.21 seconds
Started Jul 12 06:07:24 PM PDT 24
Finished Jul 12 06:08:04 PM PDT 24
Peak memory 209376 kb
Host smart-af40e09e-0576-4979-ba46-9c6d89bc89c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050474475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.1050474475
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.625003996
Short name T990
Test name
Test status
Simulation time 71049466 ps
CPU time 3.12 seconds
Started Jul 12 06:07:23 PM PDT 24
Finished Jul 12 06:08:06 PM PDT 24
Peak memory 217400 kb
Host smart-e57de512-20fa-4bdd-8316-aa3a50fce040
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625003996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.625003996
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.111200580
Short name T130
Test name
Test status
Simulation time 42622239 ps
CPU time 1.75 seconds
Started Jul 12 06:07:24 PM PDT 24
Finished Jul 12 06:08:08 PM PDT 24
Peak memory 221488 kb
Host smart-93997477-f6ae-4cd8-b82d-641fafe5fd9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111200580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_
err.111200580
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.29704821
Short name T159
Test name
Test status
Simulation time 32681359 ps
CPU time 0.94 seconds
Started Jul 12 06:07:23 PM PDT 24
Finished Jul 12 06:08:04 PM PDT 24
Peak memory 209292 kb
Host smart-b63a0324-0321-48ac-b5dd-ce9cd550e8ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29704821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.29704821
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1089524788
Short name T940
Test name
Test status
Simulation time 173434763 ps
CPU time 1.51 seconds
Started Jul 12 06:07:25 PM PDT 24
Finished Jul 12 06:08:08 PM PDT 24
Peak memory 217476 kb
Host smart-afa2bc85-0b02-4dc8-8e13-2d0feeabdb6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089524788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1089524788
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1416584164
Short name T941
Test name
Test status
Simulation time 266614512 ps
CPU time 4.92 seconds
Started Jul 12 06:07:25 PM PDT 24
Finished Jul 12 06:08:12 PM PDT 24
Peak memory 217384 kb
Host smart-1a8f00a0-1363-4d54-9d29-eebadc7c7cba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416584164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1416584164
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1973131512
Short name T948
Test name
Test status
Simulation time 125630452 ps
CPU time 1.09 seconds
Started Jul 12 06:07:31 PM PDT 24
Finished Jul 12 06:08:22 PM PDT 24
Peak memory 217660 kb
Host smart-2a77f674-1d3e-4a55-bcab-c391015b1253
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973131512 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.1973131512
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1610541487
Short name T161
Test name
Test status
Simulation time 37180807 ps
CPU time 0.85 seconds
Started Jul 12 06:07:31 PM PDT 24
Finished Jul 12 06:08:22 PM PDT 24
Peak memory 209160 kb
Host smart-4cfecf83-0f6b-4ff1-8b1a-3a345ff94a8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610541487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1610541487
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.914231081
Short name T964
Test name
Test status
Simulation time 13759883 ps
CPU time 1.24 seconds
Started Jul 12 06:07:30 PM PDT 24
Finished Jul 12 06:08:17 PM PDT 24
Peak memory 209232 kb
Host smart-0782566c-fe96-4ea3-ad51-31246fe3d421
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914231081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_same_csr_outstanding.914231081
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4280070761
Short name T887
Test name
Test status
Simulation time 60946462 ps
CPU time 2.19 seconds
Started Jul 12 06:07:25 PM PDT 24
Finished Jul 12 06:08:09 PM PDT 24
Peak memory 218580 kb
Host smart-d8aeffb9-3faa-4b5d-a1fc-c879e56340e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280070761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.4280070761
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1385652094
Short name T203
Test name
Test status
Simulation time 18069727 ps
CPU time 0.84 seconds
Started Jul 12 06:07:30 PM PDT 24
Finished Jul 12 06:08:17 PM PDT 24
Peak memory 209176 kb
Host smart-d64d4580-b2fd-4b7d-8be5-8330b46ee354
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385652094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.1385652094
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2464068101
Short name T212
Test name
Test status
Simulation time 88154113 ps
CPU time 1.5 seconds
Started Jul 12 06:07:31 PM PDT 24
Finished Jul 12 06:08:23 PM PDT 24
Peak memory 211400 kb
Host smart-7be77982-7b34-408e-95be-dc8d905158b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464068101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2464068101
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1613289540
Short name T120
Test name
Test status
Simulation time 397370116 ps
CPU time 5.3 seconds
Started Jul 12 06:07:34 PM PDT 24
Finished Jul 12 06:08:30 PM PDT 24
Peak memory 217540 kb
Host smart-c9a25ab8-c32e-4604-add1-394692ae9678
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613289540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.1613289540
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3671859093
Short name T124
Test name
Test status
Simulation time 309842027 ps
CPU time 2.87 seconds
Started Jul 12 06:07:30 PM PDT 24
Finished Jul 12 06:08:19 PM PDT 24
Peak memory 222180 kb
Host smart-bcf20c7d-d33c-4050-9098-a028bd331486
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671859093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.3671859093
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3171643277
Short name T876
Test name
Test status
Simulation time 173407087 ps
CPU time 0.99 seconds
Started Jul 12 06:07:29 PM PDT 24
Finished Jul 12 06:08:16 PM PDT 24
Peak memory 217604 kb
Host smart-90d48ddc-b640-432c-aefb-9465d01cb2bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171643277 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.3171643277
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.740753632
Short name T202
Test name
Test status
Simulation time 47811208 ps
CPU time 0.95 seconds
Started Jul 12 06:07:33 PM PDT 24
Finished Jul 12 06:08:23 PM PDT 24
Peak memory 209032 kb
Host smart-35b01846-e867-494d-9202-70cddf42ca91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740753632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.740753632
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.743633534
Short name T896
Test name
Test status
Simulation time 172549911 ps
CPU time 1.59 seconds
Started Jul 12 06:07:31 PM PDT 24
Finished Jul 12 06:08:22 PM PDT 24
Peak memory 209276 kb
Host smart-04cbfd3b-73dc-4232-86bf-dbf3e70ac7cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743633534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.743633534
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.680146811
Short name T113
Test name
Test status
Simulation time 31027501 ps
CPU time 2.21 seconds
Started Jul 12 06:07:31 PM PDT 24
Finished Jul 12 06:08:23 PM PDT 24
Peak memory 217428 kb
Host smart-589649cb-e6fe-44a8-b2c9-3883f270b766
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680146811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.680146811
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3502709764
Short name T223
Test name
Test status
Simulation time 63091886 ps
CPU time 1.96 seconds
Started Jul 12 06:07:31 PM PDT 24
Finished Jul 12 06:08:23 PM PDT 24
Peak memory 212984 kb
Host smart-a134fe12-34b9-4484-95ca-b7e25d488dd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502709764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.3502709764
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.456002240
Short name T966
Test name
Test status
Simulation time 19973568 ps
CPU time 1.25 seconds
Started Jul 12 06:07:37 PM PDT 24
Finished Jul 12 06:08:28 PM PDT 24
Peak memory 217752 kb
Host smart-93dd5a49-18b3-441b-9c68-704bdd5b9cfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456002240 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.456002240
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2264372383
Short name T197
Test name
Test status
Simulation time 13977817 ps
CPU time 1.01 seconds
Started Jul 12 06:07:37 PM PDT 24
Finished Jul 12 06:08:27 PM PDT 24
Peak memory 209172 kb
Host smart-4fd281ab-a1bc-4672-a396-7dfe363bbc35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264372383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2264372383
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3502321387
Short name T967
Test name
Test status
Simulation time 33415895 ps
CPU time 1.41 seconds
Started Jul 12 06:07:35 PM PDT 24
Finished Jul 12 06:08:27 PM PDT 24
Peak memory 209396 kb
Host smart-a6023a1e-e10c-4f7d-bc05-5dda1c195e21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502321387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.3502321387
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.896015143
Short name T881
Test name
Test status
Simulation time 48124947 ps
CPU time 3.39 seconds
Started Jul 12 06:07:32 PM PDT 24
Finished Jul 12 06:08:25 PM PDT 24
Peak memory 217704 kb
Host smart-73ef3a0a-0335-4ce4-808f-c979fbfa9d18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896015143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.896015143
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.228378992
Short name T137
Test name
Test status
Simulation time 241813738 ps
CPU time 1.99 seconds
Started Jul 12 06:07:39 PM PDT 24
Finished Jul 12 06:08:33 PM PDT 24
Peak memory 222012 kb
Host smart-36df0f15-e1c3-438a-8783-17e67b57e406
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228378992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg_
err.228378992
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.363806994
Short name T873
Test name
Test status
Simulation time 135169681 ps
CPU time 1.32 seconds
Started Jul 12 06:07:37 PM PDT 24
Finished Jul 12 06:08:27 PM PDT 24
Peak memory 217608 kb
Host smart-6df199cf-e06e-4398-bc77-eb8a16b0292f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363806994 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.363806994
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1334877856
Short name T122
Test name
Test status
Simulation time 15851662 ps
CPU time 0.88 seconds
Started Jul 12 06:07:38 PM PDT 24
Finished Jul 12 06:08:32 PM PDT 24
Peak memory 208900 kb
Host smart-8048177f-5ba6-4a84-9dfd-43bb1525cc66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334877856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1334877856
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.1107046403
Short name T937
Test name
Test status
Simulation time 44545645 ps
CPU time 1.97 seconds
Started Jul 12 06:07:37 PM PDT 24
Finished Jul 12 06:08:32 PM PDT 24
Peak memory 211052 kb
Host smart-be962de8-ae60-4245-9d3f-50dce056269b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107046403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.1107046403
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2366944665
Short name T918
Test name
Test status
Simulation time 458890786 ps
CPU time 3.35 seconds
Started Jul 12 06:07:39 PM PDT 24
Finished Jul 12 06:08:35 PM PDT 24
Peak memory 217392 kb
Host smart-3c57f271-716c-4128-a026-bb6cb9cc8fea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366944665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.2366944665
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3411755773
Short name T905
Test name
Test status
Simulation time 78130722 ps
CPU time 1.49 seconds
Started Jul 12 06:07:37 PM PDT 24
Finished Jul 12 06:08:31 PM PDT 24
Peak memory 219580 kb
Host smart-051ae125-6647-475b-a115-8cdf4f3888a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411755773 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3411755773
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3143648124
Short name T885
Test name
Test status
Simulation time 74142619 ps
CPU time 0.95 seconds
Started Jul 12 06:07:37 PM PDT 24
Finished Jul 12 06:08:27 PM PDT 24
Peak memory 209284 kb
Host smart-30a96db2-d474-4b1c-89c7-5591695d1599
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143648124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.3143648124
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3672426155
Short name T207
Test name
Test status
Simulation time 20859281 ps
CPU time 1.18 seconds
Started Jul 12 06:07:39 PM PDT 24
Finished Jul 12 06:08:32 PM PDT 24
Peak memory 209196 kb
Host smart-bf9818bc-6583-4c1f-9932-9f62aae1f757
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672426155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.3672426155
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3757443262
Short name T116
Test name
Test status
Simulation time 156629076 ps
CPU time 1.6 seconds
Started Jul 12 06:07:37 PM PDT 24
Finished Jul 12 06:08:28 PM PDT 24
Peak memory 217504 kb
Host smart-e4a6b30a-88f4-4a4a-ab3a-6fff4822377b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757443262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.3757443262
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1264044751
Short name T968
Test name
Test status
Simulation time 85770627 ps
CPU time 1.56 seconds
Started Jul 12 06:07:45 PM PDT 24
Finished Jul 12 06:08:43 PM PDT 24
Peak memory 218732 kb
Host smart-3a8e3dee-e6a1-4e60-9373-650725c49b56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264044751 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1264044751
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1253304889
Short name T869
Test name
Test status
Simulation time 50752173 ps
CPU time 0.91 seconds
Started Jul 12 06:07:46 PM PDT 24
Finished Jul 12 06:08:43 PM PDT 24
Peak memory 209044 kb
Host smart-03f65d18-8f2f-4787-89f2-57caf2528662
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253304889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.1253304889
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.969188118
Short name T974
Test name
Test status
Simulation time 40443983 ps
CPU time 1.32 seconds
Started Jul 12 06:07:46 PM PDT 24
Finished Jul 12 06:08:43 PM PDT 24
Peak memory 209256 kb
Host smart-7c8c6342-9cfb-4ca3-ac24-5ea2573e5a10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969188118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.969188118
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3500452122
Short name T954
Test name
Test status
Simulation time 74435167 ps
CPU time 2.75 seconds
Started Jul 12 06:07:37 PM PDT 24
Finished Jul 12 06:08:32 PM PDT 24
Peak memory 217388 kb
Host smart-043c55ae-dd9d-410a-a73f-7f5207b2febf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500452122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3500452122
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.324932498
Short name T172
Test name
Test status
Simulation time 50508759 ps
CPU time 1.62 seconds
Started Jul 12 06:07:43 PM PDT 24
Finished Jul 12 06:08:42 PM PDT 24
Peak memory 221312 kb
Host smart-ea4553e6-8cbf-42bc-9bb2-78d93e25730a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324932498 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.324932498
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2937078983
Short name T956
Test name
Test status
Simulation time 16163532 ps
CPU time 0.86 seconds
Started Jul 12 06:07:44 PM PDT 24
Finished Jul 12 06:08:42 PM PDT 24
Peak memory 209292 kb
Host smart-803ecdd0-af90-4f9d-9078-0a6c750bfb44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937078983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2937078983
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1723706623
Short name T927
Test name
Test status
Simulation time 91282836 ps
CPU time 1.27 seconds
Started Jul 12 06:07:48 PM PDT 24
Finished Jul 12 06:08:47 PM PDT 24
Peak memory 209280 kb
Host smart-d32c76b0-f06a-4a12-bcc9-7a9ebf499040
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723706623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.1723706623
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.381993426
Short name T959
Test name
Test status
Simulation time 39356709 ps
CPU time 2.54 seconds
Started Jul 12 06:07:46 PM PDT 24
Finished Jul 12 06:08:47 PM PDT 24
Peak memory 217540 kb
Host smart-97eceba3-5e42-4d0e-93e7-d2d64f819b24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381993426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.381993426
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.133874306
Short name T198
Test name
Test status
Simulation time 149087107 ps
CPU time 1.8 seconds
Started Jul 12 06:06:57 PM PDT 24
Finished Jul 12 06:07:15 PM PDT 24
Peak memory 209276 kb
Host smart-e63d2713-590f-4c64-a54b-1a8c5690ee7e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133874306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing
.133874306
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.4198908487
Short name T906
Test name
Test status
Simulation time 371778939 ps
CPU time 2.09 seconds
Started Jul 12 06:06:58 PM PDT 24
Finished Jul 12 06:07:16 PM PDT 24
Peak memory 209144 kb
Host smart-de50bac3-2310-45d0-a407-eac4727f0799
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198908487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.4198908487
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2873576682
Short name T935
Test name
Test status
Simulation time 22071881 ps
CPU time 1.28 seconds
Started Jul 12 06:06:52 PM PDT 24
Finished Jul 12 06:07:09 PM PDT 24
Peak memory 211520 kb
Host smart-6590ced2-6254-40a7-a12c-f9e0e40568ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873576682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.2873576682
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1932623989
Short name T890
Test name
Test status
Simulation time 394974983 ps
CPU time 1.48 seconds
Started Jul 12 06:06:59 PM PDT 24
Finished Jul 12 06:07:18 PM PDT 24
Peak memory 217620 kb
Host smart-c4d16c24-7806-4413-a004-6ecc0cbb7ed9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932623989 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1932623989
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2127840416
Short name T931
Test name
Test status
Simulation time 67948388 ps
CPU time 0.9 seconds
Started Jul 12 06:06:52 PM PDT 24
Finished Jul 12 06:07:08 PM PDT 24
Peak memory 209276 kb
Host smart-1decdd42-4167-492f-993d-c41a673c1bb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127840416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2127840416
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.896022125
Short name T957
Test name
Test status
Simulation time 138224843 ps
CPU time 1.93 seconds
Started Jul 12 06:06:50 PM PDT 24
Finished Jul 12 06:07:07 PM PDT 24
Peak memory 208708 kb
Host smart-7667e58c-8c99-473f-a1a3-f0b4728c77c9
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896022125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_jtag_alert_test.896022125
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3099824228
Short name T898
Test name
Test status
Simulation time 3117003918 ps
CPU time 7.66 seconds
Started Jul 12 06:06:52 PM PDT 24
Finished Jul 12 06:07:15 PM PDT 24
Peak memory 209300 kb
Host smart-02c4ec8b-edf3-48b0-8a13-51d85412b5ab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099824228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.3099824228
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1910693017
Short name T215
Test name
Test status
Simulation time 707315068 ps
CPU time 5.09 seconds
Started Jul 12 06:06:52 PM PDT 24
Finished Jul 12 06:07:13 PM PDT 24
Peak memory 217016 kb
Host smart-a384d19d-2b11-4085-b7f1-cb59ffca7c8b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910693017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1910693017
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1091560908
Short name T958
Test name
Test status
Simulation time 158921473 ps
CPU time 1.72 seconds
Started Jul 12 06:06:51 PM PDT 24
Finished Jul 12 06:07:07 PM PDT 24
Peak memory 210848 kb
Host smart-49fd8dfc-42e3-4648-a506-ce292242f789
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091560908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.1091560908
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.487234559
Short name T882
Test name
Test status
Simulation time 368404308 ps
CPU time 3.01 seconds
Started Jul 12 06:06:50 PM PDT 24
Finished Jul 12 06:07:07 PM PDT 24
Peak memory 218696 kb
Host smart-f7a8932f-42e0-41b2-8da2-d8b31ea85e90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487234
559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.487234559
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.408940698
Short name T963
Test name
Test status
Simulation time 115522453 ps
CPU time 3.28 seconds
Started Jul 12 06:06:52 PM PDT 24
Finished Jul 12 06:07:11 PM PDT 24
Peak memory 209284 kb
Host smart-8cb355b2-bb9b-4ccf-bfaf-c83b48eca68f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408940698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.408940698
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.304898139
Short name T984
Test name
Test status
Simulation time 46443706 ps
CPU time 1.22 seconds
Started Jul 12 06:06:53 PM PDT 24
Finished Jul 12 06:07:10 PM PDT 24
Peak memory 209200 kb
Host smart-ea5d52bd-6f99-4dc9-aa34-f76e96b29f44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304898139 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.304898139
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3385229850
Short name T950
Test name
Test status
Simulation time 28372167 ps
CPU time 0.99 seconds
Started Jul 12 06:06:59 PM PDT 24
Finished Jul 12 06:07:18 PM PDT 24
Peak memory 209352 kb
Host smart-331994be-b296-4a3c-9203-2db4fb616190
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385229850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3385229850
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2129021319
Short name T925
Test name
Test status
Simulation time 215551278 ps
CPU time 2.34 seconds
Started Jul 12 06:06:51 PM PDT 24
Finished Jul 12 06:07:08 PM PDT 24
Peak memory 217384 kb
Host smart-3798e91b-9706-482b-b265-3976880a76f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129021319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2129021319
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3638099793
Short name T119
Test name
Test status
Simulation time 130709425 ps
CPU time 2.73 seconds
Started Jul 12 06:06:57 PM PDT 24
Finished Jul 12 06:07:15 PM PDT 24
Peak memory 217504 kb
Host smart-98e571a3-8858-4351-8147-f648d21371f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638099793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.3638099793
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1464547280
Short name T912
Test name
Test status
Simulation time 118947298 ps
CPU time 1.61 seconds
Started Jul 12 06:06:59 PM PDT 24
Finished Jul 12 06:07:19 PM PDT 24
Peak memory 209408 kb
Host smart-9df7879e-1a68-4cd0-a6c8-fecc8e66490a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464547280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.1464547280
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1368867565
Short name T942
Test name
Test status
Simulation time 71377714 ps
CPU time 1.39 seconds
Started Jul 12 06:06:57 PM PDT 24
Finished Jul 12 06:07:16 PM PDT 24
Peak memory 209220 kb
Host smart-a5d9fd2e-1616-423d-ab3a-f135599d96ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368867565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.1368867565
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2369047761
Short name T870
Test name
Test status
Simulation time 12552848 ps
CPU time 0.98 seconds
Started Jul 12 06:06:55 PM PDT 24
Finished Jul 12 06:07:12 PM PDT 24
Peak memory 209824 kb
Host smart-1c446052-b2de-4e4b-8a32-50f1eb8d0b82
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369047761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.2369047761
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3735986305
Short name T943
Test name
Test status
Simulation time 286240880 ps
CPU time 1.65 seconds
Started Jul 12 06:06:57 PM PDT 24
Finished Jul 12 06:07:16 PM PDT 24
Peak memory 217848 kb
Host smart-2f1ac029-f8e3-4095-86b5-6065dc46744e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735986305 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3735986305
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.269505253
Short name T952
Test name
Test status
Simulation time 12878329 ps
CPU time 1 seconds
Started Jul 12 06:06:58 PM PDT 24
Finished Jul 12 06:07:16 PM PDT 24
Peak memory 208832 kb
Host smart-860f46a9-ab3e-4fd1-bdee-51760481d7ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269505253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.269505253
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1255038344
Short name T945
Test name
Test status
Simulation time 67134018 ps
CPU time 1.44 seconds
Started Jul 12 06:07:01 PM PDT 24
Finished Jul 12 06:07:20 PM PDT 24
Peak memory 209080 kb
Host smart-bf8ba9cc-6de5-4328-a934-a0e0be0e715b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255038344 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.1255038344
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.4051241263
Short name T877
Test name
Test status
Simulation time 2970608490 ps
CPU time 6.39 seconds
Started Jul 12 06:06:59 PM PDT 24
Finished Jul 12 06:07:24 PM PDT 24
Peak memory 217460 kb
Host smart-3dc5de9a-16cc-40d4-936a-82a44e211c26
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051241263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.4051241263
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.592255450
Short name T874
Test name
Test status
Simulation time 697633855 ps
CPU time 8.89 seconds
Started Jul 12 06:06:58 PM PDT 24
Finished Jul 12 06:07:23 PM PDT 24
Peak memory 209212 kb
Host smart-fd81349a-7284-4dd4-bd21-8a154b7af355
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592255450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.592255450
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.359259045
Short name T142
Test name
Test status
Simulation time 201056527 ps
CPU time 1.67 seconds
Started Jul 12 06:06:59 PM PDT 24
Finished Jul 12 06:07:18 PM PDT 24
Peak memory 210600 kb
Host smart-77a3171f-5619-4a69-80df-b6c7d282b481
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359259045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.359259045
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.44181422
Short name T920
Test name
Test status
Simulation time 54975784 ps
CPU time 1.3 seconds
Started Jul 12 06:06:55 PM PDT 24
Finished Jul 12 06:07:13 PM PDT 24
Peak memory 209172 kb
Host smart-75f9db81-c8d9-470e-b9d4-c2b6ee068639
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44181422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test
+UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 3.lc_ctrl_jtag_csr_rw.44181422
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2867928917
Short name T162
Test name
Test status
Simulation time 29442179 ps
CPU time 1.44 seconds
Started Jul 12 06:06:56 PM PDT 24
Finished Jul 12 06:07:13 PM PDT 24
Peak memory 217552 kb
Host smart-bff916c5-4cdc-403d-9158-25087378398c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867928917 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2867928917
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1599654216
Short name T970
Test name
Test status
Simulation time 65253224 ps
CPU time 1.28 seconds
Started Jul 12 06:06:59 PM PDT 24
Finished Jul 12 06:07:18 PM PDT 24
Peak memory 209336 kb
Host smart-e340a0bb-0e77-4df3-a808-0bbd6c5773a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599654216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.1599654216
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3923854098
Short name T117
Test name
Test status
Simulation time 41410272 ps
CPU time 3.07 seconds
Started Jul 12 06:06:57 PM PDT 24
Finished Jul 12 06:07:16 PM PDT 24
Peak memory 217412 kb
Host smart-93eb6643-0cb1-4c70-bc58-7df582c3b57c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923854098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.3923854098
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.770297473
Short name T200
Test name
Test status
Simulation time 39296942 ps
CPU time 1.32 seconds
Started Jul 12 06:07:06 PM PDT 24
Finished Jul 12 06:07:30 PM PDT 24
Peak memory 209348 kb
Host smart-2e3df51a-cda1-4041-bc1b-9c1c4a778504
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770297473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasing
.770297473
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3211483260
Short name T893
Test name
Test status
Simulation time 20681024 ps
CPU time 1.4 seconds
Started Jul 12 06:07:07 PM PDT 24
Finished Jul 12 06:07:30 PM PDT 24
Peak memory 209316 kb
Host smart-3465d275-cf01-466a-88c8-e44346acf998
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211483260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.3211483260
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2599994968
Short name T199
Test name
Test status
Simulation time 20328454 ps
CPU time 1.03 seconds
Started Jul 12 06:07:06 PM PDT 24
Finished Jul 12 06:07:30 PM PDT 24
Peak memory 209796 kb
Host smart-2bb2dae6-a8ef-4595-bff0-7c431e5090a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599994968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.2599994968
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1905488379
Short name T981
Test name
Test status
Simulation time 59414046 ps
CPU time 1.09 seconds
Started Jul 12 06:07:04 PM PDT 24
Finished Jul 12 06:07:26 PM PDT 24
Peak memory 217760 kb
Host smart-35550116-8826-4101-9673-189ef0e7c864
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905488379 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1905488379
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3144534624
Short name T196
Test name
Test status
Simulation time 14099126 ps
CPU time 1.05 seconds
Started Jul 12 06:07:05 PM PDT 24
Finished Jul 12 06:07:26 PM PDT 24
Peak memory 208984 kb
Host smart-06d1d38f-026c-4cc7-b549-ae98615f3f03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144534624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3144534624
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.507414683
Short name T879
Test name
Test status
Simulation time 62121596 ps
CPU time 1.29 seconds
Started Jul 12 06:07:05 PM PDT 24
Finished Jul 12 06:07:26 PM PDT 24
Peak memory 209112 kb
Host smart-d9013a8c-7a0b-4977-a491-a66694e95ced
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507414683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_alert_test.507414683
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1483194771
Short name T944
Test name
Test status
Simulation time 1526577952 ps
CPU time 8.89 seconds
Started Jul 12 06:07:03 PM PDT 24
Finished Jul 12 06:07:31 PM PDT 24
Peak memory 209004 kb
Host smart-caef2199-0bea-49d8-b222-663d69da5d6d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483194771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.1483194771
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2184500684
Short name T911
Test name
Test status
Simulation time 2599701124 ps
CPU time 56.95 seconds
Started Jul 12 06:07:06 PM PDT 24
Finished Jul 12 06:08:25 PM PDT 24
Peak memory 209144 kb
Host smart-7951dbc6-188c-4851-9b84-db5054df6aee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184500684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.2184500684
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1019292473
Short name T947
Test name
Test status
Simulation time 74920174 ps
CPU time 1.47 seconds
Started Jul 12 06:07:01 PM PDT 24
Finished Jul 12 06:07:20 PM PDT 24
Peak memory 210584 kb
Host smart-b72a3b41-5564-4fd7-95d4-9243f25d30ad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019292473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.1019292473
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3694321844
Short name T955
Test name
Test status
Simulation time 47875365 ps
CPU time 1.69 seconds
Started Jul 12 06:07:08 PM PDT 24
Finished Jul 12 06:07:33 PM PDT 24
Peak memory 219036 kb
Host smart-4b6efcdc-b74c-4ea4-a441-f62f674b1273
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369432
1844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3694321844
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.35767397
Short name T987
Test name
Test status
Simulation time 45690291 ps
CPU time 1.15 seconds
Started Jul 12 06:07:03 PM PDT 24
Finished Jul 12 06:07:23 PM PDT 24
Peak memory 209112 kb
Host smart-ca3d2882-b589-46fe-aa9f-7d45cb405ac4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35767397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test
+UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 4.lc_ctrl_jtag_csr_rw.35767397
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1494586284
Short name T210
Test name
Test status
Simulation time 164019276 ps
CPU time 1.89 seconds
Started Jul 12 06:07:03 PM PDT 24
Finished Jul 12 06:07:23 PM PDT 24
Peak memory 209260 kb
Host smart-30a9d48f-62de-4eb1-a738-78e9aa95fe6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494586284 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1494586284
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.659249461
Short name T900
Test name
Test status
Simulation time 113916889 ps
CPU time 1.46 seconds
Started Jul 12 06:07:07 PM PDT 24
Finished Jul 12 06:07:30 PM PDT 24
Peak memory 209284 kb
Host smart-81989d13-8c52-4c29-84f4-e0017802dc99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659249461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
same_csr_outstanding.659249461
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1232623846
Short name T979
Test name
Test status
Simulation time 49666531 ps
CPU time 2.27 seconds
Started Jul 12 06:07:08 PM PDT 24
Finished Jul 12 06:07:33 PM PDT 24
Peak memory 217404 kb
Host smart-4c817c2b-86b9-4b3d-93c1-b10513c4b85a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232623846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1232623846
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2848318369
Short name T128
Test name
Test status
Simulation time 67002428 ps
CPU time 2.11 seconds
Started Jul 12 06:07:03 PM PDT 24
Finished Jul 12 06:07:24 PM PDT 24
Peak memory 221956 kb
Host smart-292f227e-60b5-40f1-abcc-d232556e2da5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848318369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.2848318369
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.16052878
Short name T160
Test name
Test status
Simulation time 70007792 ps
CPU time 1.06 seconds
Started Jul 12 06:07:11 PM PDT 24
Finished Jul 12 06:07:41 PM PDT 24
Peak memory 218640 kb
Host smart-fc022c44-085d-45c5-b4ef-e80584accf59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16052878 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.16052878
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2188660808
Short name T962
Test name
Test status
Simulation time 29928325 ps
CPU time 0.89 seconds
Started Jul 12 06:07:11 PM PDT 24
Finished Jul 12 06:07:41 PM PDT 24
Peak memory 209264 kb
Host smart-0055d3b6-b63e-436b-9dc1-d1ea98643919
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188660808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2188660808
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3620967767
Short name T875
Test name
Test status
Simulation time 93717920 ps
CPU time 1.25 seconds
Started Jul 12 06:07:04 PM PDT 24
Finished Jul 12 06:07:24 PM PDT 24
Peak memory 208608 kb
Host smart-5081e8df-1b79-4f33-8da0-e3ad5e5fa890
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620967767 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.3620967767
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2753704225
Short name T980
Test name
Test status
Simulation time 295215202 ps
CPU time 7.46 seconds
Started Jul 12 06:07:03 PM PDT 24
Finished Jul 12 06:07:29 PM PDT 24
Peak memory 209020 kb
Host smart-4c6d1877-2d31-4eb4-a746-83060cd0cf5a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753704225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2753704225
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3236380271
Short name T922
Test name
Test status
Simulation time 1654676637 ps
CPU time 14.62 seconds
Started Jul 12 06:07:03 PM PDT 24
Finished Jul 12 06:07:37 PM PDT 24
Peak memory 217048 kb
Host smart-3913c8e9-41a0-43c9-8356-8abc35917ac3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236380271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3236380271
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3588379541
Short name T961
Test name
Test status
Simulation time 150192675 ps
CPU time 2.13 seconds
Started Jul 12 06:07:04 PM PDT 24
Finished Jul 12 06:07:27 PM PDT 24
Peak memory 210860 kb
Host smart-b6d265df-af8e-40e0-bc1e-cbbd9340c300
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588379541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3588379541
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1891244833
Short name T921
Test name
Test status
Simulation time 256465362 ps
CPU time 2.44 seconds
Started Jul 12 06:07:05 PM PDT 24
Finished Jul 12 06:07:27 PM PDT 24
Peak memory 217636 kb
Host smart-5aad901c-f03d-457f-9c5d-31f8a7d1ac62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189124
4833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1891244833
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.386107145
Short name T894
Test name
Test status
Simulation time 837609585 ps
CPU time 2.58 seconds
Started Jul 12 06:07:05 PM PDT 24
Finished Jul 12 06:07:29 PM PDT 24
Peak memory 209232 kb
Host smart-57e8ec06-c39e-4dd7-a625-66393235c3e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386107145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.386107145
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1485689829
Short name T938
Test name
Test status
Simulation time 32849049 ps
CPU time 1.14 seconds
Started Jul 12 06:07:04 PM PDT 24
Finished Jul 12 06:07:24 PM PDT 24
Peak memory 209400 kb
Host smart-fb5959f5-0cec-4adf-8b1e-a7174bda636c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485689829 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.1485689829
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2559674630
Short name T915
Test name
Test status
Simulation time 16619304 ps
CPU time 1.05 seconds
Started Jul 12 06:07:11 PM PDT 24
Finished Jul 12 06:07:39 PM PDT 24
Peak memory 217404 kb
Host smart-cf126988-ed09-4a36-b035-0bc0c5fd9c7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559674630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2559674630
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.392295372
Short name T888
Test name
Test status
Simulation time 85600672 ps
CPU time 1.92 seconds
Started Jul 12 06:07:07 PM PDT 24
Finished Jul 12 06:07:31 PM PDT 24
Peak memory 217728 kb
Host smart-483866bd-5743-4655-9a2c-1094c7d28761
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392295372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.392295372
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1969918699
Short name T112
Test name
Test status
Simulation time 31932800 ps
CPU time 1.43 seconds
Started Jul 12 06:07:10 PM PDT 24
Finished Jul 12 06:07:39 PM PDT 24
Peak memory 222756 kb
Host smart-dabcae4a-b5a1-40c1-bd07-9b5be766d757
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969918699 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.1969918699
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1697131319
Short name T988
Test name
Test status
Simulation time 28099132 ps
CPU time 0.98 seconds
Started Jul 12 06:07:11 PM PDT 24
Finished Jul 12 06:07:41 PM PDT 24
Peak memory 209228 kb
Host smart-cf8a9d83-9aad-4e16-bfcd-86faba67b82d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697131319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1697131319
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3352272188
Short name T924
Test name
Test status
Simulation time 34173873 ps
CPU time 1.47 seconds
Started Jul 12 06:07:16 PM PDT 24
Finished Jul 12 06:07:51 PM PDT 24
Peak memory 209156 kb
Host smart-a3960cb4-ffc9-4100-96b9-c0e6286cca56
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352272188 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.3352272188
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.4265820252
Short name T973
Test name
Test status
Simulation time 1298091182 ps
CPU time 4.06 seconds
Started Jul 12 06:07:10 PM PDT 24
Finished Jul 12 06:07:41 PM PDT 24
Peak memory 208996 kb
Host smart-bbcb54e8-353f-4098-9a64-b3659fddf7e2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265820252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.4265820252
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.4133808861
Short name T145
Test name
Test status
Simulation time 4558786572 ps
CPU time 51.19 seconds
Started Jul 12 06:07:10 PM PDT 24
Finished Jul 12 06:08:28 PM PDT 24
Peak memory 209288 kb
Host smart-4ac3e229-0955-4bcd-bf58-9f58d12ae4cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133808861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.4133808861
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2024169213
Short name T140
Test name
Test status
Simulation time 108804906 ps
CPU time 3.08 seconds
Started Jul 12 06:07:10 PM PDT 24
Finished Jul 12 06:07:41 PM PDT 24
Peak memory 217412 kb
Host smart-9ac42f22-400e-48f3-9e3a-1bda89d30079
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024169213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2024169213
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1485195124
Short name T126
Test name
Test status
Simulation time 430522611 ps
CPU time 3.06 seconds
Started Jul 12 06:07:14 PM PDT 24
Finished Jul 12 06:07:50 PM PDT 24
Peak memory 218836 kb
Host smart-8bc34d5d-6705-441a-8bf6-713164699161
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148519
5124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1485195124
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2583882615
Short name T934
Test name
Test status
Simulation time 153394432 ps
CPU time 2.45 seconds
Started Jul 12 06:07:11 PM PDT 24
Finished Jul 12 06:07:40 PM PDT 24
Peak memory 217360 kb
Host smart-b7060df0-d9db-41bf-a422-66ebec926efa
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583882615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.2583882615
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3820446324
Short name T985
Test name
Test status
Simulation time 103395606 ps
CPU time 1.42 seconds
Started Jul 12 06:07:10 PM PDT 24
Finished Jul 12 06:07:39 PM PDT 24
Peak memory 211280 kb
Host smart-7f8b529c-1bbe-4259-939c-9a21f2ff5dd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820446324 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3820446324
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3045791796
Short name T914
Test name
Test status
Simulation time 37515218 ps
CPU time 1.26 seconds
Started Jul 12 06:07:12 PM PDT 24
Finished Jul 12 06:07:41 PM PDT 24
Peak memory 209296 kb
Host smart-704c2656-53f0-4899-bcd0-a0e0374f8628
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045791796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.3045791796
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3890412725
Short name T109
Test name
Test status
Simulation time 88955573 ps
CPU time 2.69 seconds
Started Jul 12 06:07:16 PM PDT 24
Finished Jul 12 06:07:53 PM PDT 24
Peak memory 217424 kb
Host smart-eb063250-0a03-43da-9e2d-ff06c6a60853
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890412725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.3890412725
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1817390438
Short name T118
Test name
Test status
Simulation time 97181097 ps
CPU time 2.39 seconds
Started Jul 12 06:07:14 PM PDT 24
Finished Jul 12 06:07:49 PM PDT 24
Peak memory 217512 kb
Host smart-3ea7cb84-e166-409a-bb38-b4f44e89ebe8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817390438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.1817390438
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.4282300935
Short name T878
Test name
Test status
Simulation time 28224302 ps
CPU time 1 seconds
Started Jul 12 06:07:18 PM PDT 24
Finished Jul 12 06:07:52 PM PDT 24
Peak memory 217604 kb
Host smart-6e669b97-56aa-448d-a464-a837787fe483
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282300935 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.4282300935
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2280849153
Short name T953
Test name
Test status
Simulation time 54851868 ps
CPU time 0.92 seconds
Started Jul 12 06:07:19 PM PDT 24
Finished Jul 12 06:07:54 PM PDT 24
Peak memory 209248 kb
Host smart-e6af2573-18f9-4261-b94a-53471f6cd901
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280849153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2280849153
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2156141880
Short name T883
Test name
Test status
Simulation time 168534573 ps
CPU time 1.72 seconds
Started Jul 12 06:07:18 PM PDT 24
Finished Jul 12 06:07:52 PM PDT 24
Peak memory 208708 kb
Host smart-6452b723-1501-444f-bd98-7fa33a636ea1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156141880 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2156141880
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1755252215
Short name T929
Test name
Test status
Simulation time 194376776 ps
CPU time 3.16 seconds
Started Jul 12 06:07:09 PM PDT 24
Finished Jul 12 06:07:37 PM PDT 24
Peak memory 208916 kb
Host smart-fb188423-aa09-4c94-ac97-d00d7e25c0e6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755252215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1755252215
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.762667527
Short name T123
Test name
Test status
Simulation time 843234321 ps
CPU time 10.58 seconds
Started Jul 12 06:07:13 PM PDT 24
Finished Jul 12 06:07:53 PM PDT 24
Peak memory 208912 kb
Host smart-3d781bb8-023e-493e-a66c-c2d97001b9cc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762667527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.762667527
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2898870751
Short name T932
Test name
Test status
Simulation time 790359647 ps
CPU time 2.05 seconds
Started Jul 12 06:07:11 PM PDT 24
Finished Jul 12 06:07:40 PM PDT 24
Peak memory 210972 kb
Host smart-fcb42257-bd60-4dcf-86c8-ebe82094dfd5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898870751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2898870751
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1943444280
Short name T971
Test name
Test status
Simulation time 124323314 ps
CPU time 2.88 seconds
Started Jul 12 06:07:19 PM PDT 24
Finished Jul 12 06:07:56 PM PDT 24
Peak memory 219068 kb
Host smart-2dd25d51-38f7-4dce-bb81-dec4e4d6befc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194344
4280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1943444280
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.301227667
Short name T939
Test name
Test status
Simulation time 203720802 ps
CPU time 1.16 seconds
Started Jul 12 06:07:15 PM PDT 24
Finished Jul 12 06:07:48 PM PDT 24
Peak memory 209208 kb
Host smart-68b70f5d-df1d-47e7-ad69-4b20eae307a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301227667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.301227667
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3883136733
Short name T206
Test name
Test status
Simulation time 100907538 ps
CPU time 1.31 seconds
Started Jul 12 06:07:11 PM PDT 24
Finished Jul 12 06:07:41 PM PDT 24
Peak memory 211176 kb
Host smart-9c3844c6-5688-4959-ac05-6fce0cf1cc26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883136733 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.3883136733
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2073643621
Short name T208
Test name
Test status
Simulation time 23959191 ps
CPU time 1.1 seconds
Started Jul 12 06:07:18 PM PDT 24
Finished Jul 12 06:07:52 PM PDT 24
Peak memory 209356 kb
Host smart-b6a0f7d3-4a61-473d-acbd-06b6d6093a08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073643621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.2073643621
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.196691476
Short name T986
Test name
Test status
Simulation time 392658554 ps
CPU time 3.16 seconds
Started Jul 12 06:07:19 PM PDT 24
Finished Jul 12 06:07:56 PM PDT 24
Peak memory 217412 kb
Host smart-7e6b65b7-29b6-4882-a159-e8505ec66a85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196691476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.196691476
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3811204295
Short name T121
Test name
Test status
Simulation time 44514407 ps
CPU time 1.7 seconds
Started Jul 12 06:07:16 PM PDT 24
Finished Jul 12 06:07:49 PM PDT 24
Peak memory 218752 kb
Host smart-d6116141-897d-4e0e-8ecd-44572e26e5f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811204295 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3811204295
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2323877723
Short name T910
Test name
Test status
Simulation time 15427682 ps
CPU time 0.91 seconds
Started Jul 12 06:07:17 PM PDT 24
Finished Jul 12 06:07:51 PM PDT 24
Peak memory 209236 kb
Host smart-9fa0c7a6-59cd-453a-9096-172c15af179f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323877723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2323877723
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1253351433
Short name T960
Test name
Test status
Simulation time 351435910 ps
CPU time 2.86 seconds
Started Jul 12 06:07:18 PM PDT 24
Finished Jul 12 06:07:54 PM PDT 24
Peak memory 208700 kb
Host smart-d3fb89e3-d465-4b40-984b-d81cecda888d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253351433 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.1253351433
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2970937054
Short name T909
Test name
Test status
Simulation time 4328105683 ps
CPU time 10.6 seconds
Started Jul 12 06:07:19 PM PDT 24
Finished Jul 12 06:08:03 PM PDT 24
Peak memory 209188 kb
Host smart-ec145207-0a47-4f09-848e-6c62fc1e807a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970937054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2970937054
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.4011400040
Short name T886
Test name
Test status
Simulation time 4130520263 ps
CPU time 20.35 seconds
Started Jul 12 06:07:16 PM PDT 24
Finished Jul 12 06:08:08 PM PDT 24
Peak memory 209128 kb
Host smart-0ec3253b-5be3-4adb-9b28-69b100d163d1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011400040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.4011400040
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2822523032
Short name T904
Test name
Test status
Simulation time 464512067 ps
CPU time 1.87 seconds
Started Jul 12 06:07:15 PM PDT 24
Finished Jul 12 06:07:49 PM PDT 24
Peak memory 210880 kb
Host smart-3d5ce750-99ad-4a15-b90c-314ddc8dd582
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822523032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2822523032
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2746125595
Short name T891
Test name
Test status
Simulation time 873341124 ps
CPU time 5.89 seconds
Started Jul 12 06:07:17 PM PDT 24
Finished Jul 12 06:07:57 PM PDT 24
Peak memory 217560 kb
Host smart-af9f02ee-2bcb-4b6e-9c9b-72e11891a7c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274612
5595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2746125595
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.429613128
Short name T901
Test name
Test status
Simulation time 65830185 ps
CPU time 1.36 seconds
Started Jul 12 06:07:16 PM PDT 24
Finished Jul 12 06:07:49 PM PDT 24
Peak memory 209156 kb
Host smart-0474b3b9-c98d-4d04-bd63-ed86525142b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429613128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.429613128
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.218289275
Short name T946
Test name
Test status
Simulation time 142038549 ps
CPU time 1.76 seconds
Started Jul 12 06:07:16 PM PDT 24
Finished Jul 12 06:07:52 PM PDT 24
Peak memory 211188 kb
Host smart-1b12d375-68eb-42d3-a702-efe5acca7332
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218289275 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.218289275
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.73488638
Short name T211
Test name
Test status
Simulation time 264417135 ps
CPU time 1.14 seconds
Started Jul 12 06:07:16 PM PDT 24
Finished Jul 12 06:07:48 PM PDT 24
Peak memory 209232 kb
Host smart-30e94b05-4c57-4933-8953-5ddc126da014
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73488638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_s
ame_csr_outstanding.73488638
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3177715386
Short name T928
Test name
Test status
Simulation time 53604441 ps
CPU time 3.13 seconds
Started Jul 12 06:07:19 PM PDT 24
Finished Jul 12 06:07:57 PM PDT 24
Peak memory 217608 kb
Host smart-099d0a8e-0381-47ec-8e30-96a4eb0512b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177715386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3177715386
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2121606256
Short name T173
Test name
Test status
Simulation time 33756337 ps
CPU time 1.34 seconds
Started Jul 12 06:07:23 PM PDT 24
Finished Jul 12 06:08:04 PM PDT 24
Peak memory 219688 kb
Host smart-af9f08f9-e92f-459a-beb2-0ce82e3420d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121606256 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2121606256
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3977775530
Short name T919
Test name
Test status
Simulation time 20796707 ps
CPU time 1.24 seconds
Started Jul 12 06:07:24 PM PDT 24
Finished Jul 12 06:08:04 PM PDT 24
Peak memory 209228 kb
Host smart-c09235f0-8777-47ff-835e-3c47e495062c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977775530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3977775530
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2043387010
Short name T916
Test name
Test status
Simulation time 259902192 ps
CPU time 2.74 seconds
Started Jul 12 06:07:24 PM PDT 24
Finished Jul 12 06:08:09 PM PDT 24
Peak memory 209112 kb
Host smart-9d37077e-1ad1-4b47-83e0-b6262cd132ab
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043387010 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2043387010
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.827293651
Short name T965
Test name
Test status
Simulation time 190839253 ps
CPU time 5.24 seconds
Started Jul 12 06:07:15 PM PDT 24
Finished Jul 12 06:07:52 PM PDT 24
Peak memory 217044 kb
Host smart-038db0b7-3355-45d8-bbfc-127b8508cd57
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827293651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.827293651
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.4221538159
Short name T871
Test name
Test status
Simulation time 549737021 ps
CPU time 6.1 seconds
Started Jul 12 06:07:17 PM PDT 24
Finished Jul 12 06:07:57 PM PDT 24
Peak memory 208868 kb
Host smart-0b565866-268d-4e8c-9e7b-995ec999311c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221538159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.4221538159
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2265159654
Short name T913
Test name
Test status
Simulation time 185625107 ps
CPU time 1.94 seconds
Started Jul 12 06:07:16 PM PDT 24
Finished Jul 12 06:07:52 PM PDT 24
Peak memory 217356 kb
Host smart-be653e15-4e88-488b-a870-171313ba308b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265159654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2265159654
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1118925217
Short name T903
Test name
Test status
Simulation time 537017993 ps
CPU time 3.53 seconds
Started Jul 12 06:07:25 PM PDT 24
Finished Jul 12 06:08:10 PM PDT 24
Peak memory 218508 kb
Host smart-a5fed4de-ab82-4ef3-b4e5-ca9002ad9fa7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111892
5217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1118925217
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.109097703
Short name T983
Test name
Test status
Simulation time 92790991 ps
CPU time 1.58 seconds
Started Jul 12 06:07:15 PM PDT 24
Finished Jul 12 06:07:49 PM PDT 24
Peak memory 209220 kb
Host smart-dcbc8228-0083-4cd5-836c-e002542b0cf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109097703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.109097703
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.266430210
Short name T908
Test name
Test status
Simulation time 162074792 ps
CPU time 1.99 seconds
Started Jul 12 06:07:25 PM PDT 24
Finished Jul 12 06:08:09 PM PDT 24
Peak memory 209492 kb
Host smart-c7cfc972-5ff7-4e96-a6bf-89c3f500b7d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266430210 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.266430210
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.810962109
Short name T907
Test name
Test status
Simulation time 20425085 ps
CPU time 1.22 seconds
Started Jul 12 06:07:33 PM PDT 24
Finished Jul 12 06:08:23 PM PDT 24
Peak memory 209384 kb
Host smart-0a2d0c27-6079-4f8a-ad14-07aae2c5cd33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810962109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
same_csr_outstanding.810962109
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.270295959
Short name T892
Test name
Test status
Simulation time 47288996 ps
CPU time 1.88 seconds
Started Jul 12 06:07:25 PM PDT 24
Finished Jul 12 06:08:09 PM PDT 24
Peak memory 217420 kb
Host smart-594a0afb-7b3a-447e-8546-bd864dbee787
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270295959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.270295959
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.4112597234
Short name T129
Test name
Test status
Simulation time 284586919 ps
CPU time 3.36 seconds
Started Jul 12 06:07:25 PM PDT 24
Finished Jul 12 06:08:10 PM PDT 24
Peak memory 222004 kb
Host smart-671d92f3-7858-4bec-8df8-5f723b0e9bce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112597234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.4112597234
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3384588556
Short name T560
Test name
Test status
Simulation time 17829035 ps
CPU time 0.91 seconds
Started Jul 12 05:35:13 PM PDT 24
Finished Jul 12 05:35:17 PM PDT 24
Peak memory 208900 kb
Host smart-a5cac0fa-9e5b-41c1-ac76-219902b345fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384588556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3384588556
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1420630984
Short name T403
Test name
Test status
Simulation time 5210386576 ps
CPU time 17.23 seconds
Started Jul 12 05:35:12 PM PDT 24
Finished Jul 12 05:35:32 PM PDT 24
Peak memory 218204 kb
Host smart-e664cf9d-8cc0-4e11-aeb9-4026fc6a5fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420630984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1420630984
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.1991272374
Short name T34
Test name
Test status
Simulation time 1763732473 ps
CPU time 3.83 seconds
Started Jul 12 05:35:14 PM PDT 24
Finished Jul 12 05:35:21 PM PDT 24
Peak memory 217016 kb
Host smart-3d12a4d8-34cb-4b8c-9703-ac7c4759696f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991272374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.1991272374
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.1330196529
Short name T660
Test name
Test status
Simulation time 28112749672 ps
CPU time 50.24 seconds
Started Jul 12 05:35:13 PM PDT 24
Finished Jul 12 05:36:05 PM PDT 24
Peak memory 218680 kb
Host smart-82bda97e-bc8e-477e-adb3-e3cffcd9fa32
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330196529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.1330196529
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.3826067138
Short name T735
Test name
Test status
Simulation time 3513402460 ps
CPU time 3.69 seconds
Started Jul 12 05:35:13 PM PDT 24
Finished Jul 12 05:35:19 PM PDT 24
Peak memory 217756 kb
Host smart-6d9dcf65-700c-4332-a44f-e2c4670265aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826067138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.3
826067138
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.629376234
Short name T253
Test name
Test status
Simulation time 2143047516 ps
CPU time 7.59 seconds
Started Jul 12 05:35:14 PM PDT 24
Finished Jul 12 05:35:24 PM PDT 24
Peak memory 223860 kb
Host smart-af57b8bc-5f92-4cde-81a0-6b6012336d41
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629376234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
prog_failure.629376234
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.521573705
Short name T71
Test name
Test status
Simulation time 1513937662 ps
CPU time 23.91 seconds
Started Jul 12 05:35:11 PM PDT 24
Finished Jul 12 05:35:36 PM PDT 24
Peak memory 217656 kb
Host smart-d0143281-bf76-460c-bef3-8579cd86583d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521573705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_regwen_during_op.521573705
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3801099037
Short name T653
Test name
Test status
Simulation time 352969452 ps
CPU time 1.55 seconds
Started Jul 12 05:35:16 PM PDT 24
Finished Jul 12 05:35:19 PM PDT 24
Peak memory 217644 kb
Host smart-b28b330a-5299-4d3d-97cc-19084b1e7ccd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801099037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3801099037
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1485597380
Short name T155
Test name
Test status
Simulation time 815064314 ps
CPU time 38.57 seconds
Started Jul 12 05:35:55 PM PDT 24
Finished Jul 12 05:36:35 PM PDT 24
Peak memory 250888 kb
Host smart-8082a317-35a5-4987-9f5e-7538b1bf1754
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485597380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1485597380
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.3477007602
Short name T646
Test name
Test status
Simulation time 447563346 ps
CPU time 19.17 seconds
Started Jul 12 05:35:12 PM PDT 24
Finished Jul 12 05:35:34 PM PDT 24
Peak memory 250844 kb
Host smart-819942cc-4ee8-4cbd-8368-24affb98d33a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477007602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.3477007602
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.3074383769
Short name T611
Test name
Test status
Simulation time 176371104 ps
CPU time 2.82 seconds
Started Jul 12 05:35:15 PM PDT 24
Finished Jul 12 05:35:20 PM PDT 24
Peak memory 222312 kb
Host smart-67b41cfb-efdb-48f1-871d-64bbe7a600bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074383769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3074383769
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.2018386770
Short name T690
Test name
Test status
Simulation time 230393033 ps
CPU time 6.56 seconds
Started Jul 12 05:35:13 PM PDT 24
Finished Jul 12 05:35:22 PM PDT 24
Peak memory 214548 kb
Host smart-78745c73-d058-4b8f-9a3a-7fa31444846e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018386770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2018386770
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3627036972
Short name T826
Test name
Test status
Simulation time 436738632 ps
CPU time 15.72 seconds
Started Jul 12 05:35:11 PM PDT 24
Finished Jul 12 05:35:29 PM PDT 24
Peak memory 225984 kb
Host smart-ebdde31f-93bc-40d9-afe1-5c3e1a136333
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627036972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.3627036972
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2710991924
Short name T738
Test name
Test status
Simulation time 2132233665 ps
CPU time 11.12 seconds
Started Jul 12 05:35:16 PM PDT 24
Finished Jul 12 05:35:29 PM PDT 24
Peak memory 225980 kb
Host smart-8fd63488-7587-46d5-8581-000a3afe04ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710991924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
710991924
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.1912015791
Short name T323
Test name
Test status
Simulation time 1468746609 ps
CPU time 11.85 seconds
Started Jul 12 05:35:13 PM PDT 24
Finished Jul 12 05:35:28 PM PDT 24
Peak memory 225984 kb
Host smart-e20683c6-6cf4-487d-a739-c80c57720b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912015791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.1912015791
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.1183825190
Short name T247
Test name
Test status
Simulation time 599719661 ps
CPU time 5.08 seconds
Started Jul 12 05:35:14 PM PDT 24
Finished Jul 12 05:35:22 PM PDT 24
Peak memory 217612 kb
Host smart-2ff7a4de-58ce-46b3-91db-4f4e8d8f3a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183825190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.1183825190
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.3709278379
Short name T752
Test name
Test status
Simulation time 2588191278 ps
CPU time 23 seconds
Started Jul 12 05:35:12 PM PDT 24
Finished Jul 12 05:35:38 PM PDT 24
Peak memory 250992 kb
Host smart-6e7765ea-09f6-408d-a1e7-92ce6e1f9c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709278379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3709278379
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.589535695
Short name T631
Test name
Test status
Simulation time 94114566 ps
CPU time 7.8 seconds
Started Jul 12 05:35:16 PM PDT 24
Finished Jul 12 05:35:25 PM PDT 24
Peak memory 250776 kb
Host smart-311d9707-4353-4937-a7f3-07f7a2415e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589535695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.589535695
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.536129828
Short name T549
Test name
Test status
Simulation time 3870749034 ps
CPU time 118.48 seconds
Started Jul 12 05:35:09 PM PDT 24
Finished Jul 12 05:37:08 PM PDT 24
Peak memory 225996 kb
Host smart-aeb64528-4af4-426d-9f2a-9f6f3223f54e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536129828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.536129828
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.921492101
Short name T609
Test name
Test status
Simulation time 29538290 ps
CPU time 0.88 seconds
Started Jul 12 05:35:13 PM PDT 24
Finished Jul 12 05:35:17 PM PDT 24
Peak memory 211756 kb
Host smart-b075a4d2-481a-4766-b92b-b6e8ec636abc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921492101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr
l_volatile_unlock_smoke.921492101
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.1839139122
Short name T234
Test name
Test status
Simulation time 33424100 ps
CPU time 0.89 seconds
Started Jul 12 05:35:21 PM PDT 24
Finished Jul 12 05:35:23 PM PDT 24
Peak memory 208592 kb
Host smart-0a164703-d80b-4a1d-90b7-5853d4cdb2cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839139122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.1839139122
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.814103395
Short name T569
Test name
Test status
Simulation time 13262965 ps
CPU time 1.07 seconds
Started Jul 12 05:35:23 PM PDT 24
Finished Jul 12 05:35:25 PM PDT 24
Peak memory 208932 kb
Host smart-72e29d56-f2ba-49ea-aa03-c4ff16b39145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814103395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.814103395
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1369813616
Short name T334
Test name
Test status
Simulation time 716456256 ps
CPU time 13.05 seconds
Started Jul 12 05:35:24 PM PDT 24
Finished Jul 12 05:35:38 PM PDT 24
Peak memory 218156 kb
Host smart-6496ed99-31b8-4129-93bf-73e4cc33fc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369813616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1369813616
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1513500611
Short name T330
Test name
Test status
Simulation time 200706441 ps
CPU time 1.85 seconds
Started Jul 12 05:35:23 PM PDT 24
Finished Jul 12 05:35:26 PM PDT 24
Peak memory 216972 kb
Host smart-9cff2837-0b83-4287-905f-a11c2a40dd99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513500611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1513500611
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2116334366
Short name T267
Test name
Test status
Simulation time 21917111867 ps
CPU time 68.36 seconds
Started Jul 12 05:35:19 PM PDT 24
Finished Jul 12 05:36:28 PM PDT 24
Peak memory 218208 kb
Host smart-8ebd6f4d-5045-4bd2-ae66-d9ace1a84202
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116334366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2116334366
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.936385132
Short name T461
Test name
Test status
Simulation time 297166059 ps
CPU time 2.64 seconds
Started Jul 12 05:35:25 PM PDT 24
Finished Jul 12 05:35:29 PM PDT 24
Peak memory 217360 kb
Host smart-eace0c4f-1149-4728-a135-ed713ecfddbd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936385132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.936385132
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.736585316
Short name T443
Test name
Test status
Simulation time 180855620 ps
CPU time 3.66 seconds
Started Jul 12 05:35:21 PM PDT 24
Finished Jul 12 05:35:25 PM PDT 24
Peak memory 218100 kb
Host smart-bf23f558-1e40-46ed-9a4d-3e7b679bedff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736585316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
prog_failure.736585316
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3091206011
Short name T831
Test name
Test status
Simulation time 1281642820 ps
CPU time 18.04 seconds
Started Jul 12 05:35:25 PM PDT 24
Finished Jul 12 05:35:45 PM PDT 24
Peak memory 217632 kb
Host smart-be07eae1-7fdb-4c74-a261-7486227d82e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091206011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3091206011
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.2806792998
Short name T402
Test name
Test status
Simulation time 459300975 ps
CPU time 5.54 seconds
Started Jul 12 05:35:24 PM PDT 24
Finished Jul 12 05:35:31 PM PDT 24
Peak memory 217628 kb
Host smart-b5227b67-59bc-4014-80b9-99b653df4363
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806792998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
2806792998
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.302515689
Short name T796
Test name
Test status
Simulation time 5920495749 ps
CPU time 66.45 seconds
Started Jul 12 05:35:24 PM PDT 24
Finished Jul 12 05:36:32 PM PDT 24
Peak memory 283736 kb
Host smart-8d2e4543-d218-4fab-afca-e5189d7984bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302515689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.302515689
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3095733827
Short name T343
Test name
Test status
Simulation time 330970462 ps
CPU time 9.96 seconds
Started Jul 12 05:35:24 PM PDT 24
Finished Jul 12 05:35:36 PM PDT 24
Peak memory 246164 kb
Host smart-d9a17325-7010-4623-9a95-da93e4b37cf6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095733827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.3095733827
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.724321503
Short name T156
Test name
Test status
Simulation time 82532509 ps
CPU time 3.7 seconds
Started Jul 12 05:35:23 PM PDT 24
Finished Jul 12 05:35:28 PM PDT 24
Peak memory 218104 kb
Host smart-2adbfcdb-7a5d-4c1c-aece-97b62393d498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724321503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.724321503
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2332756884
Short name T321
Test name
Test status
Simulation time 299025197 ps
CPU time 11.25 seconds
Started Jul 12 05:35:19 PM PDT 24
Finished Jul 12 05:35:31 PM PDT 24
Peak memory 217660 kb
Host smart-c321a4e7-0265-43c9-a106-456a5e6ff937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332756884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2332756884
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.448384134
Short name T102
Test name
Test status
Simulation time 218474833 ps
CPU time 26.71 seconds
Started Jul 12 05:35:23 PM PDT 24
Finished Jul 12 05:35:51 PM PDT 24
Peak memory 269272 kb
Host smart-0f41c553-b702-45d6-8413-56976cc99682
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448384134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.448384134
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.3050003979
Short name T352
Test name
Test status
Simulation time 468399908 ps
CPU time 13.23 seconds
Started Jul 12 05:35:24 PM PDT 24
Finished Jul 12 05:35:39 PM PDT 24
Peak memory 225892 kb
Host smart-2e847b65-142b-4816-bd5e-93012fec622b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050003979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.3050003979
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.2278431923
Short name T256
Test name
Test status
Simulation time 563556330 ps
CPU time 19.33 seconds
Started Jul 12 05:35:22 PM PDT 24
Finished Jul 12 05:35:42 PM PDT 24
Peak memory 226064 kb
Host smart-d6f79b92-6fb9-41a4-b362-1a1f682f691b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278431923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.2278431923
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.1975681039
Short name T589
Test name
Test status
Simulation time 1013295578 ps
CPU time 9.13 seconds
Started Jul 12 05:35:23 PM PDT 24
Finished Jul 12 05:35:33 PM PDT 24
Peak memory 218080 kb
Host smart-ce5a192e-6e44-4557-879d-48b90b77a50a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975681039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.1
975681039
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3590214221
Short name T475
Test name
Test status
Simulation time 428083058 ps
CPU time 9.83 seconds
Started Jul 12 05:35:25 PM PDT 24
Finished Jul 12 05:35:36 PM PDT 24
Peak memory 225916 kb
Host smart-cc3063f8-6a97-42e1-9cdb-eed318a082be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590214221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3590214221
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.1648782585
Short name T70
Test name
Test status
Simulation time 39549604 ps
CPU time 1.88 seconds
Started Jul 12 05:35:23 PM PDT 24
Finished Jul 12 05:35:26 PM PDT 24
Peak memory 213892 kb
Host smart-9ce3babf-eb86-4b06-9dd3-57ac98cc9b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648782585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1648782585
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.2126179425
Short name T686
Test name
Test status
Simulation time 388757028 ps
CPU time 30.15 seconds
Started Jul 12 05:35:22 PM PDT 24
Finished Jul 12 05:35:53 PM PDT 24
Peak memory 250884 kb
Host smart-80623e5a-4750-4ccd-aea0-033dc53a334b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126179425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2126179425
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.735541269
Short name T606
Test name
Test status
Simulation time 157605214 ps
CPU time 8.99 seconds
Started Jul 12 05:35:22 PM PDT 24
Finished Jul 12 05:35:32 PM PDT 24
Peak memory 250804 kb
Host smart-45b99b03-5e69-426c-a966-2570816f6519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735541269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.735541269
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.885596870
Short name T587
Test name
Test status
Simulation time 71494509424 ps
CPU time 281.9 seconds
Started Jul 12 05:35:25 PM PDT 24
Finished Jul 12 05:40:09 PM PDT 24
Peak memory 225984 kb
Host smart-e5cbae7d-919b-40b2-a26e-49122208c0a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885596870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.885596870
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.3771029860
Short name T147
Test name
Test status
Simulation time 96501486658 ps
CPU time 483.61 seconds
Started Jul 12 05:35:21 PM PDT 24
Finished Jul 12 05:43:25 PM PDT 24
Peak memory 333048 kb
Host smart-3ce8b1da-0c1f-4673-8ed2-bb8e2e3fad09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3771029860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.3771029860
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2009131490
Short name T602
Test name
Test status
Simulation time 28558225 ps
CPU time 0.96 seconds
Started Jul 12 05:35:23 PM PDT 24
Finished Jul 12 05:35:25 PM PDT 24
Peak memory 217676 kb
Host smart-6ffa3567-5517-4483-a2e2-36e9e9551e10
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009131490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2009131490
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.689108724
Short name T363
Test name
Test status
Simulation time 19259932 ps
CPU time 1.22 seconds
Started Jul 12 05:35:54 PM PDT 24
Finished Jul 12 05:35:57 PM PDT 24
Peak memory 208944 kb
Host smart-2c7b7e53-7cf8-4d45-a4ff-359c5e9ccc9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689108724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.689108724
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.2165474665
Short name T387
Test name
Test status
Simulation time 332429735 ps
CPU time 11.57 seconds
Started Jul 12 05:35:47 PM PDT 24
Finished Jul 12 05:36:03 PM PDT 24
Peak memory 218156 kb
Host smart-c81c776b-761e-4ce7-bfd0-9d7bb17a8d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165474665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.2165474665
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.3977330044
Short name T739
Test name
Test status
Simulation time 530121400 ps
CPU time 14.01 seconds
Started Jul 12 05:35:52 PM PDT 24
Finished Jul 12 05:36:08 PM PDT 24
Peak memory 217408 kb
Host smart-0efa3bfb-654d-4fe0-8d1a-63881e688fda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977330044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.3977330044
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.4089282577
Short name T624
Test name
Test status
Simulation time 22287531897 ps
CPU time 35.77 seconds
Started Jul 12 05:35:55 PM PDT 24
Finished Jul 12 05:36:33 PM PDT 24
Peak memory 226072 kb
Host smart-5756650c-834e-4dae-9bb4-f76f0246edbe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089282577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.4089282577
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.4107156305
Short name T703
Test name
Test status
Simulation time 1542437339 ps
CPU time 5.37 seconds
Started Jul 12 05:36:16 PM PDT 24
Finished Jul 12 05:36:22 PM PDT 24
Peak memory 218044 kb
Host smart-ba4f7c1e-646d-4fb0-bbb6-52bc2213a6df
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107156305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.4107156305
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3884871198
Short name T732
Test name
Test status
Simulation time 401517216 ps
CPU time 3.5 seconds
Started Jul 12 05:35:50 PM PDT 24
Finished Jul 12 05:35:56 PM PDT 24
Peak memory 217652 kb
Host smart-73299a15-afef-4d3d-b623-8fda2c47722e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884871198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.3884871198
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1810485
Short name T401
Test name
Test status
Simulation time 9401361853 ps
CPU time 45.69 seconds
Started Jul 12 05:35:53 PM PDT 24
Finished Jul 12 05:36:41 PM PDT 24
Peak memory 250960 kb
Host smart-c917c435-b1f4-4763-9003-be80ff81ecec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_st
ate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_
state_failure.1810485
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2944381648
Short name T476
Test name
Test status
Simulation time 27987024 ps
CPU time 2.15 seconds
Started Jul 12 05:35:47 PM PDT 24
Finished Jul 12 05:35:53 PM PDT 24
Peak memory 218164 kb
Host smart-fcf0ca43-cdc1-427c-8a9a-3f46d7c573b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944381648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2944381648
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.1417116063
Short name T55
Test name
Test status
Simulation time 1160423482 ps
CPU time 9.61 seconds
Started Jul 12 05:35:56 PM PDT 24
Finished Jul 12 05:36:07 PM PDT 24
Peak memory 218804 kb
Host smart-69cf5339-9a66-4bbe-8418-a67cdcb3bd0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417116063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.1417116063
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3095829220
Short name T859
Test name
Test status
Simulation time 1776726224 ps
CPU time 8.35 seconds
Started Jul 12 05:35:55 PM PDT 24
Finished Jul 12 05:36:10 PM PDT 24
Peak memory 225912 kb
Host smart-18128ac8-3a9c-457a-a80d-b4c14117b489
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095829220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3095829220
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.4260820614
Short name T623
Test name
Test status
Simulation time 691994251 ps
CPU time 12.39 seconds
Started Jul 12 05:35:59 PM PDT 24
Finished Jul 12 05:36:13 PM PDT 24
Peak memory 218056 kb
Host smart-578fc65e-dfec-4182-b1f2-98a4001015f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260820614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
4260820614
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.943763551
Short name T397
Test name
Test status
Simulation time 322842168 ps
CPU time 12.56 seconds
Started Jul 12 05:35:49 PM PDT 24
Finished Jul 12 05:36:04 PM PDT 24
Peak memory 225592 kb
Host smart-5c873a11-5b84-4dd7-a3a1-1bca4849e719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943763551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.943763551
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.1073431342
Short name T64
Test name
Test status
Simulation time 54326428 ps
CPU time 1.09 seconds
Started Jul 12 05:35:44 PM PDT 24
Finished Jul 12 05:35:49 PM PDT 24
Peak memory 213712 kb
Host smart-cb48787e-f5a9-4ce9-8dba-36b9a15d7c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073431342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1073431342
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.3474245592
Short name T675
Test name
Test status
Simulation time 632797191 ps
CPU time 26.97 seconds
Started Jul 12 05:35:48 PM PDT 24
Finished Jul 12 05:36:23 PM PDT 24
Peak memory 250836 kb
Host smart-c0673b33-2996-4d01-8bb9-969025a565cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474245592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.3474245592
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.3088907596
Short name T96
Test name
Test status
Simulation time 46285521 ps
CPU time 3.17 seconds
Started Jul 12 05:35:49 PM PDT 24
Finished Jul 12 05:35:56 PM PDT 24
Peak memory 226208 kb
Host smart-8e5bccf4-f275-44d0-9998-932319e397e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088907596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3088907596
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.893169082
Short name T840
Test name
Test status
Simulation time 2259784931 ps
CPU time 79.15 seconds
Started Jul 12 05:35:56 PM PDT 24
Finished Jul 12 05:37:17 PM PDT 24
Peak memory 273456 kb
Host smart-7c2f6e86-9134-4208-8cfe-6106e55dda0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893169082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.893169082
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1314432363
Short name T538
Test name
Test status
Simulation time 16190314 ps
CPU time 1.14 seconds
Started Jul 12 05:35:45 PM PDT 24
Finished Jul 12 05:35:51 PM PDT 24
Peak memory 212912 kb
Host smart-b12adfcb-319e-4b54-a6ee-0e4583e428cb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314432363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.1314432363
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.4065153879
Short name T398
Test name
Test status
Simulation time 14458726 ps
CPU time 0.83 seconds
Started Jul 12 05:35:53 PM PDT 24
Finished Jul 12 05:35:56 PM PDT 24
Peak memory 208668 kb
Host smart-503916d0-a018-4955-b60a-25757056caef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065153879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.4065153879
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.51746331
Short name T523
Test name
Test status
Simulation time 258833011 ps
CPU time 9.45 seconds
Started Jul 12 05:35:52 PM PDT 24
Finished Jul 12 05:36:04 PM PDT 24
Peak memory 218092 kb
Host smart-d07d0f66-5c1a-4897-bcf0-76a633d39749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51746331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.51746331
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.252138046
Short name T358
Test name
Test status
Simulation time 1225825219 ps
CPU time 7.8 seconds
Started Jul 12 05:35:55 PM PDT 24
Finished Jul 12 05:36:05 PM PDT 24
Peak memory 217344 kb
Host smart-51185983-a853-4245-9c91-f7c0529decd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252138046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.252138046
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.3103923175
Short name T248
Test name
Test status
Simulation time 3375926858 ps
CPU time 47.58 seconds
Started Jul 12 05:36:12 PM PDT 24
Finished Jul 12 05:37:01 PM PDT 24
Peak memory 219940 kb
Host smart-88633da9-8a1d-49d2-8c17-d843d81475e5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103923175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.3103923175
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.992272260
Short name T434
Test name
Test status
Simulation time 185047148 ps
CPU time 2.44 seconds
Started Jul 12 05:35:55 PM PDT 24
Finished Jul 12 05:36:00 PM PDT 24
Peak memory 218108 kb
Host smart-c575a975-ac83-406a-9548-66fecda5215b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992272260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_prog_failure.992272260
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.1331151934
Short name T687
Test name
Test status
Simulation time 309949614 ps
CPU time 9.28 seconds
Started Jul 12 05:36:01 PM PDT 24
Finished Jul 12 05:36:11 PM PDT 24
Peak memory 217664 kb
Host smart-804d477c-cfd2-4de8-8796-c4492debf507
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331151934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.1331151934
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3533192274
Short name T431
Test name
Test status
Simulation time 3775757942 ps
CPU time 29.11 seconds
Started Jul 12 05:35:53 PM PDT 24
Finished Jul 12 05:36:24 PM PDT 24
Peak memory 250860 kb
Host smart-9d5d6fd4-720e-4484-aa96-0efd10c58d86
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533192274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3533192274
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2506111879
Short name T748
Test name
Test status
Simulation time 60705918 ps
CPU time 3.4 seconds
Started Jul 12 05:36:15 PM PDT 24
Finished Jul 12 05:36:19 PM PDT 24
Peak memory 218016 kb
Host smart-98ce8baf-6413-426f-a000-83ac1ace77d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506111879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2506111879
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.1256312670
Short name T866
Test name
Test status
Simulation time 1046034651 ps
CPU time 9.27 seconds
Started Jul 12 05:35:53 PM PDT 24
Finished Jul 12 05:36:04 PM PDT 24
Peak memory 225932 kb
Host smart-b5997736-af80-469c-b1ab-6e868ad8d7df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256312670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.1256312670
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2691021371
Short name T437
Test name
Test status
Simulation time 745870606 ps
CPU time 15.8 seconds
Started Jul 12 05:35:58 PM PDT 24
Finished Jul 12 05:36:16 PM PDT 24
Peak memory 225984 kb
Host smart-93e0ea26-7b89-4771-b669-16b948049cc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691021371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2691021371
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.794518435
Short name T15
Test name
Test status
Simulation time 478079300 ps
CPU time 6.99 seconds
Started Jul 12 05:35:50 PM PDT 24
Finished Jul 12 05:36:00 PM PDT 24
Peak memory 225980 kb
Host smart-9c9456a6-de1c-4258-bdc2-722737221a1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794518435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.794518435
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2375102490
Short name T568
Test name
Test status
Simulation time 2635785987 ps
CPU time 14.21 seconds
Started Jul 12 05:35:51 PM PDT 24
Finished Jul 12 05:36:08 PM PDT 24
Peak memory 225564 kb
Host smart-375b48a8-231d-4b64-870d-dcc8ead0af40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375102490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2375102490
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2806479651
Short name T74
Test name
Test status
Simulation time 191613982 ps
CPU time 2.25 seconds
Started Jul 12 05:35:59 PM PDT 24
Finished Jul 12 05:36:03 PM PDT 24
Peak memory 214420 kb
Host smart-4524f853-17d1-4d22-a88c-d69da2939bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806479651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2806479651
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.115957507
Short name T467
Test name
Test status
Simulation time 430021250 ps
CPU time 21 seconds
Started Jul 12 05:35:50 PM PDT 24
Finished Jul 12 05:36:13 PM PDT 24
Peak memory 250912 kb
Host smart-eb6bac1e-e303-41f2-8dd9-eb13abc85ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115957507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.115957507
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.1568212321
Short name T545
Test name
Test status
Simulation time 284611375 ps
CPU time 3.53 seconds
Started Jul 12 05:35:52 PM PDT 24
Finished Jul 12 05:35:58 PM PDT 24
Peak memory 222212 kb
Host smart-c9858cba-4fda-4242-a8e7-2121e657e9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568212321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1568212321
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.2896649637
Short name T41
Test name
Test status
Simulation time 7283665743 ps
CPU time 55.71 seconds
Started Jul 12 05:35:57 PM PDT 24
Finished Jul 12 05:36:55 PM PDT 24
Peak memory 226040 kb
Host smart-4d9cfd4b-79c7-4799-a4c2-95025df69799
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896649637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.2896649637
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.4251882901
Short name T812
Test name
Test status
Simulation time 21083886 ps
CPU time 0.86 seconds
Started Jul 12 05:35:52 PM PDT 24
Finished Jul 12 05:35:55 PM PDT 24
Peak memory 211816 kb
Host smart-5b8acc30-bdb4-4913-b347-eeea119502c8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251882901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.4251882901
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3484851773
Short name T823
Test name
Test status
Simulation time 52198142 ps
CPU time 1.01 seconds
Started Jul 12 05:44:11 PM PDT 24
Finished Jul 12 05:44:13 PM PDT 24
Peak memory 208896 kb
Host smart-039c3f54-f3c2-4fc4-9dbe-dd481c3a35dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484851773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3484851773
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.3750352082
Short name T327
Test name
Test status
Simulation time 369710313 ps
CPU time 15.36 seconds
Started Jul 12 05:36:11 PM PDT 24
Finished Jul 12 05:36:27 PM PDT 24
Peak memory 218152 kb
Host smart-3fd4f33f-c782-431d-8f4a-be83e9e3cd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750352082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3750352082
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.629563021
Short name T819
Test name
Test status
Simulation time 104765150 ps
CPU time 3.19 seconds
Started Jul 12 05:35:49 PM PDT 24
Finished Jul 12 05:35:56 PM PDT 24
Peak memory 216968 kb
Host smart-fb74993b-05a6-4c25-a855-5a70c8b311f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629563021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.629563021
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.1010109804
Short name T721
Test name
Test status
Simulation time 12843134502 ps
CPU time 50.88 seconds
Started Jul 12 05:35:52 PM PDT 24
Finished Jul 12 05:36:46 PM PDT 24
Peak memory 226008 kb
Host smart-cf9c509b-2885-452c-8770-8af551868200
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010109804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.1010109804
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2155519195
Short name T736
Test name
Test status
Simulation time 791599166 ps
CPU time 2.27 seconds
Started Jul 12 05:35:57 PM PDT 24
Finished Jul 12 05:36:01 PM PDT 24
Peak memory 218192 kb
Host smart-79fae4a1-ac68-4bb1-bfdc-f80ed350c41e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155519195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.2155519195
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1972045568
Short name T833
Test name
Test status
Simulation time 1473077014 ps
CPU time 18.56 seconds
Started Jul 12 05:35:51 PM PDT 24
Finished Jul 12 05:36:12 PM PDT 24
Peak memory 217640 kb
Host smart-c3b8adb7-3e6a-44fd-a48e-9b4dbecefa21
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972045568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1972045568
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1388882758
Short name T706
Test name
Test status
Simulation time 13528910979 ps
CPU time 81.14 seconds
Started Jul 12 05:35:54 PM PDT 24
Finished Jul 12 05:37:22 PM PDT 24
Peak memory 283592 kb
Host smart-d9b16cc8-55ab-4418-89db-8167df236ea4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388882758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1388882758
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2724999436
Short name T805
Test name
Test status
Simulation time 1554124483 ps
CPU time 12.21 seconds
Started Jul 12 05:35:54 PM PDT 24
Finished Jul 12 05:36:08 PM PDT 24
Peak memory 250764 kb
Host smart-3aabe815-42dc-4ea4-92a9-43e48fdebbad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724999436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.2724999436
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1727608930
Short name T423
Test name
Test status
Simulation time 131455562 ps
CPU time 1.91 seconds
Started Jul 12 05:35:51 PM PDT 24
Finished Jul 12 05:35:55 PM PDT 24
Peak memory 222004 kb
Host smart-fdcf5615-7eac-4b5e-9532-575b5e871935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727608930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1727608930
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.1288033174
Short name T755
Test name
Test status
Simulation time 1391916540 ps
CPU time 15.79 seconds
Started Jul 12 05:35:52 PM PDT 24
Finished Jul 12 05:36:10 PM PDT 24
Peak memory 225932 kb
Host smart-f62209af-8736-4f2d-97a2-b816d3575714
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288033174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.1288033174
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2391237611
Short name T578
Test name
Test status
Simulation time 1358571467 ps
CPU time 9.48 seconds
Started Jul 12 05:35:54 PM PDT 24
Finished Jul 12 05:36:06 PM PDT 24
Peak memory 225860 kb
Host smart-aecc0dcb-e1cf-47c4-b67f-a8d439aac240
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391237611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.2391237611
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.2397743627
Short name T465
Test name
Test status
Simulation time 703942930 ps
CPU time 8.73 seconds
Started Jul 12 05:35:57 PM PDT 24
Finished Jul 12 05:36:07 PM PDT 24
Peak memory 218184 kb
Host smart-d9b97786-1722-4351-9f78-cf02c21dd22e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397743627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
2397743627
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.3304858466
Short name T551
Test name
Test status
Simulation time 967655193 ps
CPU time 10.43 seconds
Started Jul 12 05:35:56 PM PDT 24
Finished Jul 12 05:36:08 PM PDT 24
Peak memory 225968 kb
Host smart-6ace9f29-d625-40bd-8cc0-61b2e16b67ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304858466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.3304858466
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.1572015286
Short name T803
Test name
Test status
Simulation time 101158415 ps
CPU time 2.62 seconds
Started Jul 12 05:35:53 PM PDT 24
Finished Jul 12 05:35:58 PM PDT 24
Peak memory 214600 kb
Host smart-67981c57-ee6b-4206-bb8d-101d360387bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572015286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.1572015286
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2979270051
Short name T825
Test name
Test status
Simulation time 308785730 ps
CPU time 28.24 seconds
Started Jul 12 05:36:14 PM PDT 24
Finished Jul 12 05:36:43 PM PDT 24
Peak memory 250836 kb
Host smart-20e4541f-2e36-43a0-bff9-4ac9d2961929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979270051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2979270051
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2550504657
Short name T268
Test name
Test status
Simulation time 100668628 ps
CPU time 6.87 seconds
Started Jul 12 05:35:53 PM PDT 24
Finished Jul 12 05:36:02 PM PDT 24
Peak memory 250376 kb
Host smart-15d0ec55-167e-4b2a-98ca-578935074710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550504657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2550504657
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2643388819
Short name T691
Test name
Test status
Simulation time 21698987905 ps
CPU time 229.29 seconds
Started Jul 12 05:35:49 PM PDT 24
Finished Jul 12 05:39:42 PM PDT 24
Peak memory 283716 kb
Host smart-d0285290-4816-4626-9741-c63ade004c24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643388819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2643388819
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3958180920
Short name T775
Test name
Test status
Simulation time 13365335 ps
CPU time 1.04 seconds
Started Jul 12 05:35:53 PM PDT 24
Finished Jul 12 05:35:56 PM PDT 24
Peak memory 211848 kb
Host smart-900d3887-e6e8-4cc4-baf3-7674dea8edb1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958180920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3958180920
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.115792571
Short name T652
Test name
Test status
Simulation time 14509350 ps
CPU time 1.02 seconds
Started Jul 12 05:36:00 PM PDT 24
Finished Jul 12 05:36:02 PM PDT 24
Peak memory 208828 kb
Host smart-a054f891-d684-4ab1-b7cb-795d1cdc838b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115792571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.115792571
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.1962353322
Short name T40
Test name
Test status
Simulation time 300439653 ps
CPU time 11.09 seconds
Started Jul 12 05:35:57 PM PDT 24
Finished Jul 12 05:36:10 PM PDT 24
Peak memory 225952 kb
Host smart-7ff0661a-557f-4ce3-9909-88595e1f3016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962353322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1962353322
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.3754323258
Short name T11
Test name
Test status
Simulation time 309530407 ps
CPU time 7.68 seconds
Started Jul 12 05:36:16 PM PDT 24
Finished Jul 12 05:36:25 PM PDT 24
Peak memory 217132 kb
Host smart-5730199e-a3f6-4d21-923a-9c2ef0cff2c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754323258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.3754323258
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.3730693546
Short name T411
Test name
Test status
Simulation time 3638169343 ps
CPU time 48.49 seconds
Started Jul 12 05:35:58 PM PDT 24
Finished Jul 12 05:36:49 PM PDT 24
Peak memory 219336 kb
Host smart-95b7fe9b-fe78-49bc-a0ba-35dc478ca8ed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730693546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.3730693546
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2704778041
Short name T380
Test name
Test status
Simulation time 186035520 ps
CPU time 6.94 seconds
Started Jul 12 05:36:00 PM PDT 24
Finished Jul 12 05:36:08 PM PDT 24
Peak memory 218156 kb
Host smart-f6c6088b-5dca-41c7-a622-4c05697eb734
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704778041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2704778041
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.1187926751
Short name T284
Test name
Test status
Simulation time 176592885 ps
CPU time 1.94 seconds
Started Jul 12 05:36:12 PM PDT 24
Finished Jul 12 05:36:15 PM PDT 24
Peak memory 217608 kb
Host smart-711f5d99-53c7-4a66-9f2f-1711728faa63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187926751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.1187926751
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2201357169
Short name T516
Test name
Test status
Simulation time 4392782164 ps
CPU time 55.96 seconds
Started Jul 12 05:45:37 PM PDT 24
Finished Jul 12 05:46:34 PM PDT 24
Peak memory 275528 kb
Host smart-7758a9a6-16a9-41a0-a1d6-c2e095c9cdcd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201357169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2201357169
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3177532842
Short name T377
Test name
Test status
Simulation time 3172619381 ps
CPU time 17.98 seconds
Started Jul 12 05:35:59 PM PDT 24
Finished Jul 12 05:36:19 PM PDT 24
Peak memory 246744 kb
Host smart-09edd775-0a68-481f-9ed7-b45e5c0d24ed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177532842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.3177532842
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.996824039
Short name T801
Test name
Test status
Simulation time 139781025 ps
CPU time 3.64 seconds
Started Jul 12 05:36:18 PM PDT 24
Finished Jul 12 05:36:23 PM PDT 24
Peak memory 218032 kb
Host smart-70469666-2437-432f-8863-915a5522dfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996824039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.996824039
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.719102292
Short name T712
Test name
Test status
Simulation time 1869324302 ps
CPU time 11.12 seconds
Started Jul 12 05:36:12 PM PDT 24
Finished Jul 12 05:36:25 PM PDT 24
Peak memory 225968 kb
Host smart-8949f219-21d8-4327-a991-123338b69651
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719102292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di
gest.719102292
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.785912992
Short name T182
Test name
Test status
Simulation time 1425836024 ps
CPU time 12.77 seconds
Started Jul 12 05:36:14 PM PDT 24
Finished Jul 12 05:36:28 PM PDT 24
Peak memory 218172 kb
Host smart-9bedbbaf-1220-4548-963f-2f2152da1e95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785912992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.785912992
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.4198275760
Short name T535
Test name
Test status
Simulation time 66978476 ps
CPU time 2.86 seconds
Started Jul 12 05:36:16 PM PDT 24
Finished Jul 12 05:36:20 PM PDT 24
Peak memory 214564 kb
Host smart-33450658-7451-420a-8fd9-98c14d2fd6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198275760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.4198275760
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.1508717573
Short name T724
Test name
Test status
Simulation time 1052742906 ps
CPU time 27.16 seconds
Started Jul 12 05:35:56 PM PDT 24
Finished Jul 12 05:36:25 PM PDT 24
Peak memory 246260 kb
Host smart-31475af1-ca7a-4758-aa03-f3c11ebdfed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508717573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.1508717573
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1470972280
Short name T621
Test name
Test status
Simulation time 440921581 ps
CPU time 8.68 seconds
Started Jul 12 05:35:59 PM PDT 24
Finished Jul 12 05:36:09 PM PDT 24
Peak memory 242688 kb
Host smart-f3db7278-043b-4698-8ee9-2cd660a9a4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470972280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1470972280
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.1070015734
Short name T481
Test name
Test status
Simulation time 3921396547 ps
CPU time 69.26 seconds
Started Jul 12 05:36:01 PM PDT 24
Finished Jul 12 05:37:11 PM PDT 24
Peak memory 250864 kb
Host smart-86d4fb59-864a-4631-baff-0240c898bc0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070015734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.1070015734
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2025346019
Short name T457
Test name
Test status
Simulation time 22365457 ps
CPU time 0.85 seconds
Started Jul 12 05:35:52 PM PDT 24
Finished Jul 12 05:35:56 PM PDT 24
Peak memory 211864 kb
Host smart-887689ab-d88e-4fe9-a69a-7017d761084e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025346019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2025346019
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.1122300332
Short name T301
Test name
Test status
Simulation time 54901629 ps
CPU time 0.9 seconds
Started Jul 12 05:36:10 PM PDT 24
Finished Jul 12 05:36:11 PM PDT 24
Peak memory 208916 kb
Host smart-4ae34f27-bb09-4f5e-9855-18b1843dd902
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122300332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.1122300332
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.2157872621
Short name T315
Test name
Test status
Simulation time 216815989 ps
CPU time 11.93 seconds
Started Jul 12 05:36:15 PM PDT 24
Finished Jul 12 05:36:29 PM PDT 24
Peak memory 225988 kb
Host smart-5ca0f117-f55b-4916-b650-9c1490b50826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157872621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.2157872621
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.1317953956
Short name T444
Test name
Test status
Simulation time 44494556 ps
CPU time 1.88 seconds
Started Jul 12 05:36:05 PM PDT 24
Finished Jul 12 05:36:07 PM PDT 24
Peak memory 216972 kb
Host smart-855b3b10-3954-422e-b1f2-c3c24a40e333
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317953956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.1317953956
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.3536421401
Short name T847
Test name
Test status
Simulation time 13191588095 ps
CPU time 84.36 seconds
Started Jul 12 05:37:06 PM PDT 24
Finished Jul 12 05:38:37 PM PDT 24
Peak memory 218888 kb
Host smart-76e4f7a8-52ee-40e9-9707-ff16df87d82c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536421401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.3536421401
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.563620928
Short name T480
Test name
Test status
Simulation time 5050231755 ps
CPU time 10.53 seconds
Started Jul 12 05:36:03 PM PDT 24
Finished Jul 12 05:36:14 PM PDT 24
Peak memory 218220 kb
Host smart-a978df30-f748-445b-94e4-21f87bcfeb6d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563620928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag
_prog_failure.563620928
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1079462866
Short name T853
Test name
Test status
Simulation time 796573734 ps
CPU time 3.67 seconds
Started Jul 12 05:35:58 PM PDT 24
Finished Jul 12 05:36:03 PM PDT 24
Peak memory 217652 kb
Host smart-d6ebf2eb-0178-4f04-9124-03c493f73b29
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079462866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1079462866
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.988833662
Short name T762
Test name
Test status
Simulation time 3511494780 ps
CPU time 60.79 seconds
Started Jul 12 05:35:55 PM PDT 24
Finished Jul 12 05:36:58 PM PDT 24
Peak memory 250952 kb
Host smart-846476fe-7b1e-4935-90e5-eefa0edd918d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988833662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_state_failure.988833662
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1676484333
Short name T286
Test name
Test status
Simulation time 320767714 ps
CPU time 15.35 seconds
Started Jul 12 05:36:06 PM PDT 24
Finished Jul 12 05:36:23 PM PDT 24
Peak memory 250908 kb
Host smart-cc0141c8-6900-4eb2-96e2-f3374b63d018
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676484333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.1676484333
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.4221600975
Short name T287
Test name
Test status
Simulation time 225546095 ps
CPU time 3.32 seconds
Started Jul 12 05:36:05 PM PDT 24
Finished Jul 12 05:36:09 PM PDT 24
Peak memory 218216 kb
Host smart-2241c09b-ffd2-4c64-b947-075c097796f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221600975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.4221600975
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.3203298491
Short name T829
Test name
Test status
Simulation time 7283651129 ps
CPU time 13.81 seconds
Started Jul 12 05:35:57 PM PDT 24
Finished Jul 12 05:36:13 PM PDT 24
Peak memory 226040 kb
Host smart-16bf4ede-3370-4063-a560-db3e0c916617
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203298491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.3203298491
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.2560329882
Short name T391
Test name
Test status
Simulation time 272509273 ps
CPU time 10.95 seconds
Started Jul 12 05:36:13 PM PDT 24
Finished Jul 12 05:36:25 PM PDT 24
Peak memory 225888 kb
Host smart-b80956aa-ae07-49c6-80e5-7d0f077c276e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560329882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.2560329882
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.3142022372
Short name T680
Test name
Test status
Simulation time 3251087508 ps
CPU time 10.75 seconds
Started Jul 12 05:36:21 PM PDT 24
Finished Jul 12 05:36:33 PM PDT 24
Peak memory 218260 kb
Host smart-84e3a30f-939d-4ac2-8816-ca05a3645f17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142022372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
3142022372
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2785927772
Short name T780
Test name
Test status
Simulation time 548396774 ps
CPU time 7.92 seconds
Started Jul 12 05:36:18 PM PDT 24
Finished Jul 12 05:36:27 PM PDT 24
Peak memory 218188 kb
Host smart-39f4d806-ef06-49cc-8fd9-a745b7a05eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785927772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2785927772
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1888059086
Short name T442
Test name
Test status
Simulation time 77264325 ps
CPU time 2.64 seconds
Started Jul 12 05:36:20 PM PDT 24
Finished Jul 12 05:36:24 PM PDT 24
Peak memory 214340 kb
Host smart-7bdf5c89-adc4-467d-ba5b-b674ba8200dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888059086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1888059086
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.474630037
Short name T610
Test name
Test status
Simulation time 211123583 ps
CPU time 25.89 seconds
Started Jul 12 05:35:56 PM PDT 24
Finished Jul 12 05:36:24 PM PDT 24
Peak memory 250944 kb
Host smart-054704e0-e254-44ea-b45b-7db019bfac38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474630037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.474630037
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.1170355162
Short name T289
Test name
Test status
Simulation time 105933694 ps
CPU time 8.31 seconds
Started Jul 12 05:35:59 PM PDT 24
Finished Jul 12 05:36:09 PM PDT 24
Peak memory 250856 kb
Host smart-677470c9-5791-473e-92e0-cb00a974432e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170355162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.1170355162
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.505892469
Short name T573
Test name
Test status
Simulation time 7380485442 ps
CPU time 32.92 seconds
Started Jul 12 05:36:08 PM PDT 24
Finished Jul 12 05:36:42 PM PDT 24
Peak memory 219756 kb
Host smart-2b601c31-253c-479a-88a2-f9e78dc6e72a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505892469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.505892469
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3362557907
Short name T164
Test name
Test status
Simulation time 42073975 ps
CPU time 0.96 seconds
Started Jul 12 05:35:59 PM PDT 24
Finished Jul 12 05:36:02 PM PDT 24
Peak memory 211776 kb
Host smart-fc819b95-119a-4019-b13a-27a15108a7a9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362557907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3362557907
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2261866246
Short name T699
Test name
Test status
Simulation time 58945997 ps
CPU time 1 seconds
Started Jul 12 05:36:22 PM PDT 24
Finished Jul 12 05:36:24 PM PDT 24
Peak memory 209064 kb
Host smart-4093d9cd-8937-4de9-8e74-2c608930847a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261866246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2261866246
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.1355470736
Short name T705
Test name
Test status
Simulation time 409725294 ps
CPU time 17.28 seconds
Started Jul 12 05:36:14 PM PDT 24
Finished Jul 12 05:36:32 PM PDT 24
Peak memory 218040 kb
Host smart-b0737ae4-2c6c-4d62-82da-7ebba584bdbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355470736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.1355470736
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.3700838840
Short name T192
Test name
Test status
Simulation time 194529208 ps
CPU time 1.99 seconds
Started Jul 12 05:36:03 PM PDT 24
Finished Jul 12 05:36:06 PM PDT 24
Peak memory 217040 kb
Host smart-65bdeb8a-18d7-49c8-a441-6a5827f0736d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700838840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.3700838840
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2184341489
Short name T386
Test name
Test status
Simulation time 5883899210 ps
CPU time 44.32 seconds
Started Jul 12 05:36:21 PM PDT 24
Finished Jul 12 05:37:06 PM PDT 24
Peak memory 220072 kb
Host smart-2b1691c5-2cf2-4f9d-a35d-ce2ea252a8ef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184341489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2184341489
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2085337797
Short name T370
Test name
Test status
Simulation time 294978835 ps
CPU time 6.04 seconds
Started Jul 12 05:36:06 PM PDT 24
Finished Jul 12 05:36:13 PM PDT 24
Peak memory 218156 kb
Host smart-87e63ff3-04e6-4c36-8488-a1e34801f328
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085337797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.2085337797
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1416662758
Short name T677
Test name
Test status
Simulation time 2991007112 ps
CPU time 8.61 seconds
Started Jul 12 05:36:26 PM PDT 24
Finished Jul 12 05:36:36 PM PDT 24
Peak memory 217564 kb
Host smart-79969b85-6f30-494b-b87d-4c2bb0448d7d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416662758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1416662758
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.277349822
Short name T288
Test name
Test status
Simulation time 4903522097 ps
CPU time 26.11 seconds
Started Jul 12 05:36:30 PM PDT 24
Finished Jul 12 05:37:00 PM PDT 24
Peak memory 250976 kb
Host smart-a43cd72b-2943-4feb-b0ec-6fe1ccdfcc2c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277349822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_state_failure.277349822
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.655573669
Short name T241
Test name
Test status
Simulation time 1152171031 ps
CPU time 13.61 seconds
Started Jul 12 05:36:22 PM PDT 24
Finished Jul 12 05:36:37 PM PDT 24
Peak memory 250888 kb
Host smart-8ebb79be-a67d-483e-941f-96bf5456d486
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655573669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_state_post_trans.655573669
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.4152897927
Short name T528
Test name
Test status
Simulation time 463261369 ps
CPU time 2.92 seconds
Started Jul 12 05:35:58 PM PDT 24
Finished Jul 12 05:36:03 PM PDT 24
Peak memory 218132 kb
Host smart-e70dd2bf-1945-4df4-a7cf-2bd990ae7583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152897927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.4152897927
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.371999774
Short name T255
Test name
Test status
Simulation time 325434968 ps
CPU time 10.38 seconds
Started Jul 12 05:36:07 PM PDT 24
Finished Jul 12 05:36:19 PM PDT 24
Peak memory 225984 kb
Host smart-e4f177d8-9cc1-48d0-995e-7ed6fd0df799
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371999774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.371999774
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.576638734
Short name T718
Test name
Test status
Simulation time 572839609 ps
CPU time 11.6 seconds
Started Jul 12 05:36:06 PM PDT 24
Finished Jul 12 05:36:19 PM PDT 24
Peak memory 225976 kb
Host smart-cc987e28-d8ed-465f-bded-97a91142ed2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576638734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di
gest.576638734
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1138617632
Short name T526
Test name
Test status
Simulation time 5070930761 ps
CPU time 10.36 seconds
Started Jul 12 05:36:04 PM PDT 24
Finished Jul 12 05:36:15 PM PDT 24
Peak memory 218248 kb
Host smart-f1bd0655-2678-46c3-950d-90687765dd85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138617632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1138617632
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.1882677323
Short name T659
Test name
Test status
Simulation time 386029073 ps
CPU time 8.87 seconds
Started Jul 12 05:36:20 PM PDT 24
Finished Jul 12 05:36:30 PM PDT 24
Peak memory 225964 kb
Host smart-0af4ff73-65c3-44f9-98cd-74dfa12134cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882677323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.1882677323
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1294916001
Short name T239
Test name
Test status
Simulation time 184010887 ps
CPU time 3.88 seconds
Started Jul 12 05:36:11 PM PDT 24
Finished Jul 12 05:36:16 PM PDT 24
Peak memory 217596 kb
Host smart-a2adde30-a925-4c42-9aaa-1f9b66dcb9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294916001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1294916001
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.1589878531
Short name T326
Test name
Test status
Simulation time 182777766 ps
CPU time 21.75 seconds
Started Jul 12 05:36:08 PM PDT 24
Finished Jul 12 05:36:31 PM PDT 24
Peak memory 250900 kb
Host smart-e4863d74-d160-4886-8ed5-1772711d9bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589878531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.1589878531
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.4292147450
Short name T394
Test name
Test status
Simulation time 1405135176 ps
CPU time 10.26 seconds
Started Jul 12 05:36:15 PM PDT 24
Finished Jul 12 05:36:26 PM PDT 24
Peak memory 242836 kb
Host smart-141da51d-895d-49f7-971c-2ad0e8a80e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292147450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.4292147450
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3038938972
Short name T636
Test name
Test status
Simulation time 8232541293 ps
CPU time 239.43 seconds
Started Jul 12 05:36:07 PM PDT 24
Finished Jul 12 05:40:07 PM PDT 24
Peak memory 250964 kb
Host smart-1f142262-ae59-4a0c-8051-776fc479b7fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038938972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3038938972
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.1469971943
Short name T157
Test name
Test status
Simulation time 371118237869 ps
CPU time 411.44 seconds
Started Jul 12 05:36:20 PM PDT 24
Finished Jul 12 05:43:13 PM PDT 24
Peak memory 438248 kb
Host smart-6a3b9a6c-5296-4b50-8c5e-2ecf617deccf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1469971943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.1469971943
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2584562978
Short name T577
Test name
Test status
Simulation time 12776427 ps
CPU time 0.85 seconds
Started Jul 12 05:36:09 PM PDT 24
Finished Jul 12 05:36:11 PM PDT 24
Peak memory 211848 kb
Host smart-3072c5a7-c25a-4ef7-8a5a-11d14f6d48e6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584562978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2584562978
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2098285180
Short name T725
Test name
Test status
Simulation time 39593229 ps
CPU time 0.97 seconds
Started Jul 12 05:36:14 PM PDT 24
Finished Jul 12 05:36:16 PM PDT 24
Peak memory 208964 kb
Host smart-05f5d195-6338-44be-acfd-22308b55d334
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098285180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2098285180
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.1935103980
Short name T682
Test name
Test status
Simulation time 1877939471 ps
CPU time 17.73 seconds
Started Jul 12 05:36:28 PM PDT 24
Finished Jul 12 05:36:48 PM PDT 24
Peak memory 218152 kb
Host smart-ea0ab1ff-2a45-4f0b-899a-e93d9d3d23a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935103980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1935103980
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.857084774
Short name T195
Test name
Test status
Simulation time 2935284335 ps
CPU time 7.26 seconds
Started Jul 12 05:36:26 PM PDT 24
Finished Jul 12 05:36:35 PM PDT 24
Peak memory 217280 kb
Host smart-52b970ed-6391-473b-a999-f8872e87dedf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857084774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.857084774
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3769168049
Short name T441
Test name
Test status
Simulation time 2172465209 ps
CPU time 24.68 seconds
Started Jul 12 05:36:06 PM PDT 24
Finished Jul 12 05:36:31 PM PDT 24
Peak memory 218124 kb
Host smart-3253e77d-66c3-4919-8c12-98e10068d7de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769168049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3769168049
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.2718960321
Short name T176
Test name
Test status
Simulation time 329037754 ps
CPU time 6.6 seconds
Started Jul 12 05:36:04 PM PDT 24
Finished Jul 12 05:36:11 PM PDT 24
Peak memory 218184 kb
Host smart-b98e876b-14e7-45f9-9757-050b3467a66f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718960321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.2718960321
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.457212144
Short name T69
Test name
Test status
Simulation time 1108557822 ps
CPU time 6.37 seconds
Started Jul 12 05:36:15 PM PDT 24
Finished Jul 12 05:36:23 PM PDT 24
Peak memory 217632 kb
Host smart-629d65b7-3f76-40bb-9a45-b42b739b14ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457212144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke.
457212144
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.3576842998
Short name T601
Test name
Test status
Simulation time 7852235991 ps
CPU time 75.32 seconds
Started Jul 12 05:36:06 PM PDT 24
Finished Jul 12 05:37:23 PM PDT 24
Peak memory 268824 kb
Host smart-ef06141f-1ff1-44f4-9b1d-d990f16fae15
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576842998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.3576842998
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3528593858
Short name T713
Test name
Test status
Simulation time 1618360315 ps
CPU time 17.86 seconds
Started Jul 12 05:36:07 PM PDT 24
Finished Jul 12 05:36:26 PM PDT 24
Peak memory 250900 kb
Host smart-4b47b2fe-78a2-42dc-a0d4-d1a5473cb16f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528593858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3528593858
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2492711918
Short name T674
Test name
Test status
Simulation time 211614221 ps
CPU time 4.78 seconds
Started Jul 12 05:36:08 PM PDT 24
Finished Jul 12 05:36:13 PM PDT 24
Peak memory 222536 kb
Host smart-c9c0ab42-eca1-431b-aafa-dec8f8e4e320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492711918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2492711918
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2576639719
Short name T597
Test name
Test status
Simulation time 11114712510 ps
CPU time 23.69 seconds
Started Jul 12 05:36:31 PM PDT 24
Finished Jul 12 05:36:58 PM PDT 24
Peak memory 226000 kb
Host smart-20050f2d-b9d3-4326-94ea-0d2c12c6f2f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576639719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2576639719
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2557386874
Short name T596
Test name
Test status
Simulation time 512210646 ps
CPU time 17.44 seconds
Started Jul 12 05:36:06 PM PDT 24
Finished Jul 12 05:36:25 PM PDT 24
Peak memory 218404 kb
Host smart-00e4927d-5189-4b8d-9c2d-0be30a5916a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557386874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2557386874
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.1242876593
Short name T81
Test name
Test status
Simulation time 1125661979 ps
CPU time 10.85 seconds
Started Jul 12 05:36:05 PM PDT 24
Finished Jul 12 05:36:16 PM PDT 24
Peak memory 225888 kb
Host smart-2a91e8a0-a947-4d3f-a14a-c160e1fe2fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242876593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1242876593
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1911373422
Short name T554
Test name
Test status
Simulation time 832458860 ps
CPU time 21.74 seconds
Started Jul 12 05:36:11 PM PDT 24
Finished Jul 12 05:36:33 PM PDT 24
Peak memory 250908 kb
Host smart-deb2bf3b-a086-4317-8a09-090d78f2a3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911373422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1911373422
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.996942792
Short name T830
Test name
Test status
Simulation time 70868453 ps
CPU time 8.99 seconds
Started Jul 12 05:36:28 PM PDT 24
Finished Jul 12 05:36:39 PM PDT 24
Peak memory 250904 kb
Host smart-be28168b-67bc-4ad1-8624-f585a254ce2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996942792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.996942792
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1962308631
Short name T700
Test name
Test status
Simulation time 12181237927 ps
CPU time 197.78 seconds
Started Jul 12 05:36:15 PM PDT 24
Finished Jul 12 05:39:33 PM PDT 24
Peak memory 277264 kb
Host smart-b9df2466-ab18-46a8-8210-646e3d3ae6d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962308631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1962308631
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.3232327672
Short name T148
Test name
Test status
Simulation time 34099096684 ps
CPU time 184.94 seconds
Started Jul 12 05:36:26 PM PDT 24
Finished Jul 12 05:39:32 PM PDT 24
Peak memory 270736 kb
Host smart-62514a11-2eae-484a-bbda-24607680d889
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3232327672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.3232327672
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1729982431
Short name T269
Test name
Test status
Simulation time 13390228 ps
CPU time 0.85 seconds
Started Jul 12 05:36:06 PM PDT 24
Finished Jul 12 05:36:08 PM PDT 24
Peak memory 211768 kb
Host smart-09d96749-94fb-48ac-90db-693920b58618
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729982431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.1729982431
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.3823814726
Short name T651
Test name
Test status
Simulation time 37810689 ps
CPU time 0.86 seconds
Started Jul 12 05:36:03 PM PDT 24
Finished Jul 12 05:36:04 PM PDT 24
Peak memory 208736 kb
Host smart-5bb63e24-172e-43c4-98e4-1d669069d8c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823814726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.3823814726
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.3438277937
Short name T257
Test name
Test status
Simulation time 1091559439 ps
CPU time 8.92 seconds
Started Jul 12 05:36:23 PM PDT 24
Finished Jul 12 05:36:33 PM PDT 24
Peak memory 225936 kb
Host smart-229a8095-8881-4148-a85f-9174491e64a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438277937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3438277937
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.2337004494
Short name T747
Test name
Test status
Simulation time 737532144 ps
CPU time 5.7 seconds
Started Jul 12 05:36:22 PM PDT 24
Finished Jul 12 05:36:28 PM PDT 24
Peak memory 217176 kb
Host smart-ca22ddc9-8511-4016-8928-3b619324aa00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337004494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.2337004494
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.4035597416
Short name T586
Test name
Test status
Simulation time 22819476881 ps
CPU time 27.5 seconds
Started Jul 12 05:36:06 PM PDT 24
Finished Jul 12 05:36:34 PM PDT 24
Peak memory 225984 kb
Host smart-966e700f-990d-4dee-a605-a46bf117dc1f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035597416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.4035597416
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.108414191
Short name T641
Test name
Test status
Simulation time 560779444 ps
CPU time 10.71 seconds
Started Jul 12 05:36:15 PM PDT 24
Finished Jul 12 05:36:27 PM PDT 24
Peak memory 218140 kb
Host smart-7709648d-6e66-431d-8b26-4813ae9671d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108414191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.108414191
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1943649541
Short name T419
Test name
Test status
Simulation time 137845854 ps
CPU time 4.81 seconds
Started Jul 12 05:36:05 PM PDT 24
Finished Jul 12 05:36:11 PM PDT 24
Peak memory 217536 kb
Host smart-f39de257-7999-46e2-8173-e6d864b904c2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943649541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1943649541
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3580264312
Short name T761
Test name
Test status
Simulation time 39910493670 ps
CPU time 54.54 seconds
Started Jul 12 05:36:16 PM PDT 24
Finished Jul 12 05:37:12 PM PDT 24
Peak memory 276960 kb
Host smart-62b7308f-34b1-407a-b2fd-cf633c83b1fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580264312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.3580264312
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.787616985
Short name T616
Test name
Test status
Simulation time 4027022406 ps
CPU time 18.63 seconds
Started Jul 12 05:36:12 PM PDT 24
Finished Jul 12 05:36:32 PM PDT 24
Peak memory 250604 kb
Host smart-5c448fc3-d877-4a74-8da2-9d730a247f65
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787616985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
jtag_state_post_trans.787616985
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1895902159
Short name T795
Test name
Test status
Simulation time 16801050 ps
CPU time 1.52 seconds
Started Jul 12 05:36:07 PM PDT 24
Finished Jul 12 05:36:10 PM PDT 24
Peak memory 218156 kb
Host smart-0a0fa8e8-01cd-498c-b9ef-6a9d4c12df7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895902159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1895902159
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1705879811
Short name T100
Test name
Test status
Simulation time 662096714 ps
CPU time 14.25 seconds
Started Jul 12 05:36:22 PM PDT 24
Finished Jul 12 05:36:37 PM PDT 24
Peak memory 225972 kb
Host smart-8103467d-136d-493a-8da2-292101c3dbc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705879811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1705879811
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.380034034
Short name T454
Test name
Test status
Simulation time 891476629 ps
CPU time 7.93 seconds
Started Jul 12 05:36:14 PM PDT 24
Finished Jul 12 05:36:22 PM PDT 24
Peak memory 225936 kb
Host smart-bf9807e9-7c62-4f0a-baa6-3d9496de4e7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380034034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.380034034
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.2802325197
Short name T635
Test name
Test status
Simulation time 424810804 ps
CPU time 15.43 seconds
Started Jul 12 05:36:24 PM PDT 24
Finished Jul 12 05:36:47 PM PDT 24
Peak memory 225964 kb
Host smart-e1ec3a6d-ae30-430c-a537-e28bd80095be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802325197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2802325197
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.909692231
Short name T634
Test name
Test status
Simulation time 192747461 ps
CPU time 2.77 seconds
Started Jul 12 05:36:25 PM PDT 24
Finished Jul 12 05:36:28 PM PDT 24
Peak memory 214816 kb
Host smart-93b767e9-d310-439b-b6f4-ea986c5c3605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909692231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.909692231
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.58860260
Short name T477
Test name
Test status
Simulation time 762918312 ps
CPU time 21.41 seconds
Started Jul 12 05:36:05 PM PDT 24
Finished Jul 12 05:36:28 PM PDT 24
Peak memory 250804 kb
Host smart-0938d883-87d4-4256-9e39-93d48f4272fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58860260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.58860260
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.729750432
Short name T849
Test name
Test status
Simulation time 70477800 ps
CPU time 6.84 seconds
Started Jul 12 05:36:07 PM PDT 24
Finished Jul 12 05:36:15 PM PDT 24
Peak memory 250524 kb
Host smart-f74ca569-9f3f-47e1-9a7e-81dbb8c5c4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729750432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.729750432
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.1921509096
Short name T820
Test name
Test status
Simulation time 7547218297 ps
CPU time 52.25 seconds
Started Jul 12 05:36:21 PM PDT 24
Finished Jul 12 05:37:15 PM PDT 24
Peak memory 250908 kb
Host smart-698aee22-c6ad-49af-a8a3-501cc3e3690f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921509096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.1921509096
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3435295086
Short name T790
Test name
Test status
Simulation time 21243117 ps
CPU time 0.9 seconds
Started Jul 12 05:36:05 PM PDT 24
Finished Jul 12 05:36:07 PM PDT 24
Peak memory 211656 kb
Host smart-36d998a9-434c-4fba-9e54-213e9f46f184
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435295086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.3435295086
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.2928223056
Short name T672
Test name
Test status
Simulation time 17863989 ps
CPU time 0.92 seconds
Started Jul 12 05:36:27 PM PDT 24
Finished Jul 12 05:36:29 PM PDT 24
Peak memory 208924 kb
Host smart-bbafb066-0ef0-4cf7-98fe-f5202b066013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928223056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2928223056
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.743903100
Short name T838
Test name
Test status
Simulation time 4074243798 ps
CPU time 13.47 seconds
Started Jul 12 05:36:14 PM PDT 24
Finished Jul 12 05:36:28 PM PDT 24
Peak memory 226028 kb
Host smart-8da5b418-a626-4128-9c5a-2be15822e78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743903100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.743903100
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.1617771527
Short name T355
Test name
Test status
Simulation time 189208099 ps
CPU time 3.31 seconds
Started Jul 12 05:36:32 PM PDT 24
Finished Jul 12 05:36:40 PM PDT 24
Peak memory 217176 kb
Host smart-43de604e-4204-455d-b64f-5edef6d664aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617771527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.1617771527
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2496300248
Short name T529
Test name
Test status
Simulation time 22112524380 ps
CPU time 27.02 seconds
Started Jul 12 05:36:30 PM PDT 24
Finished Jul 12 05:37:01 PM PDT 24
Peak memory 218872 kb
Host smart-f3e9da26-3e93-4dde-8a46-38a17e02b4e6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496300248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2496300248
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3978608570
Short name T571
Test name
Test status
Simulation time 3256023237 ps
CPU time 20.89 seconds
Started Jul 12 05:36:25 PM PDT 24
Finished Jul 12 05:36:47 PM PDT 24
Peak memory 222696 kb
Host smart-0173be14-0044-4474-9add-fb57949d7e0b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978608570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3978608570
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2725307691
Short name T841
Test name
Test status
Simulation time 380320891 ps
CPU time 10.57 seconds
Started Jul 12 05:36:32 PM PDT 24
Finished Jul 12 05:36:50 PM PDT 24
Peak memory 217616 kb
Host smart-229a1e77-72e6-42ac-af3e-67509ceb34a8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725307691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2725307691
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1345986596
Short name T512
Test name
Test status
Simulation time 1425819299 ps
CPU time 47.82 seconds
Started Jul 12 05:36:17 PM PDT 24
Finished Jul 12 05:37:06 PM PDT 24
Peak memory 267396 kb
Host smart-2a586480-3903-462c-a60e-089aafc0fd87
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345986596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1345986596
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3712697557
Short name T746
Test name
Test status
Simulation time 505367162 ps
CPU time 12.49 seconds
Started Jul 12 05:36:30 PM PDT 24
Finished Jul 12 05:36:46 PM PDT 24
Peak memory 248632 kb
Host smart-8d155cd5-068a-4cca-b729-030734481dcd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712697557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.3712697557
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.2833021005
Short name T658
Test name
Test status
Simulation time 84060766 ps
CPU time 2.13 seconds
Started Jul 12 05:36:24 PM PDT 24
Finished Jul 12 05:36:27 PM PDT 24
Peak memory 218136 kb
Host smart-0a02eaae-0da4-46ac-b7bd-8d4ee8044eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833021005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2833021005
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.1246028265
Short name T506
Test name
Test status
Simulation time 478133127 ps
CPU time 17.53 seconds
Started Jul 12 05:36:18 PM PDT 24
Finished Jul 12 05:36:37 PM PDT 24
Peak memory 218844 kb
Host smart-20d9da4f-ff18-42dc-b345-5cb710be189c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246028265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1246028265
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1368587963
Short name T852
Test name
Test status
Simulation time 966711856 ps
CPU time 13.69 seconds
Started Jul 12 05:36:24 PM PDT 24
Finished Jul 12 05:36:39 PM PDT 24
Peak memory 225848 kb
Host smart-105e07e8-48ee-4818-a429-c75977254926
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368587963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1368587963
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1880804681
Short name T508
Test name
Test status
Simulation time 1143071543 ps
CPU time 13.71 seconds
Started Jul 12 05:36:18 PM PDT 24
Finished Jul 12 05:36:32 PM PDT 24
Peak memory 225996 kb
Host smart-062ace4b-f451-4461-b116-5c9599388cb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880804681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1880804681
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.4004050037
Short name T648
Test name
Test status
Simulation time 795366378 ps
CPU time 9.94 seconds
Started Jul 12 05:36:30 PM PDT 24
Finished Jul 12 05:36:44 PM PDT 24
Peak memory 225856 kb
Host smart-84cc1a50-7b14-4738-a28b-b6c258924575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004050037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.4004050037
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.490013638
Short name T75
Test name
Test status
Simulation time 14086670 ps
CPU time 1.2 seconds
Started Jul 12 05:36:11 PM PDT 24
Finished Jul 12 05:36:13 PM PDT 24
Peak memory 221796 kb
Host smart-ae5391ec-33fc-4acd-aa2a-c3d0d43b53d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490013638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.490013638
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.1644564186
Short name T758
Test name
Test status
Simulation time 532228055 ps
CPU time 20.77 seconds
Started Jul 12 05:36:21 PM PDT 24
Finished Jul 12 05:36:42 PM PDT 24
Peak memory 245724 kb
Host smart-cbec3ba3-d5c6-45e7-996f-bc15c4099764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644564186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.1644564186
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3042175669
Short name T225
Test name
Test status
Simulation time 390591723 ps
CPU time 3.47 seconds
Started Jul 12 05:36:07 PM PDT 24
Finished Jul 12 05:36:12 PM PDT 24
Peak memory 226340 kb
Host smart-a318c121-f602-4fb9-a318-dcda186c3ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042175669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3042175669
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.31729226
Short name T328
Test name
Test status
Simulation time 2433118106 ps
CPU time 87.53 seconds
Started Jul 12 05:36:29 PM PDT 24
Finished Jul 12 05:37:58 PM PDT 24
Peak memory 246208 kb
Host smart-ba88452a-7c4c-4011-b168-b3aa994b51bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31729226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.lc_ctrl_stress_all.31729226
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2095354472
Short name T684
Test name
Test status
Simulation time 90221002 ps
CPU time 0.97 seconds
Started Jul 12 05:36:20 PM PDT 24
Finished Jul 12 05:36:22 PM PDT 24
Peak memory 211828 kb
Host smart-31071445-f99c-4946-9e68-6194c26cf406
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095354472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.2095354472
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.1936584695
Short name T773
Test name
Test status
Simulation time 85136173 ps
CPU time 1.24 seconds
Started Jul 12 05:36:24 PM PDT 24
Finished Jul 12 05:36:27 PM PDT 24
Peak memory 208984 kb
Host smart-151f1303-94fe-419a-a237-186cf8c0803d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936584695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1936584695
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.920353645
Short name T320
Test name
Test status
Simulation time 1199621419 ps
CPU time 10.53 seconds
Started Jul 12 05:36:24 PM PDT 24
Finished Jul 12 05:36:36 PM PDT 24
Peak memory 218168 kb
Host smart-3618e865-dd45-4f0a-94b1-2bbde48a7e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920353645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.920353645
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.1875138217
Short name T8
Test name
Test status
Simulation time 1091696504 ps
CPU time 10.74 seconds
Started Jul 12 05:36:25 PM PDT 24
Finished Jul 12 05:36:37 PM PDT 24
Peak memory 217116 kb
Host smart-5d180f0d-9784-4dc3-871c-ee93a618afce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875138217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.1875138217
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.1130072631
Short name T681
Test name
Test status
Simulation time 1575141575 ps
CPU time 27.14 seconds
Started Jul 12 05:36:27 PM PDT 24
Finished Jul 12 05:36:56 PM PDT 24
Peak memory 218928 kb
Host smart-63785d22-4b93-42cf-a471-32d775ebc040
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130072631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.1130072631
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.3051414515
Short name T373
Test name
Test status
Simulation time 642296782 ps
CPU time 6.99 seconds
Started Jul 12 05:36:10 PM PDT 24
Finished Jul 12 05:36:18 PM PDT 24
Peak memory 223072 kb
Host smart-2627b1ec-e769-4572-9a71-10b20a2bb52f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051414515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.3051414515
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2566063714
Short name T608
Test name
Test status
Simulation time 436671399 ps
CPU time 5.49 seconds
Started Jul 12 05:36:22 PM PDT 24
Finished Jul 12 05:36:29 PM PDT 24
Peak memory 217624 kb
Host smart-bd7c4c68-f496-41af-a3a3-76530d0a9720
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566063714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2566063714
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.1655878768
Short name T170
Test name
Test status
Simulation time 3960069150 ps
CPU time 36.47 seconds
Started Jul 12 05:36:29 PM PDT 24
Finished Jul 12 05:37:08 PM PDT 24
Peak memory 267364 kb
Host smart-1ab3b617-7577-4136-adbc-9274b7404ac3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655878768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.1655878768
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.3954427874
Short name T356
Test name
Test status
Simulation time 4873068815 ps
CPU time 13.64 seconds
Started Jul 12 05:36:25 PM PDT 24
Finished Jul 12 05:36:40 PM PDT 24
Peak memory 250856 kb
Host smart-63f1e1f4-dd4b-4cc7-9ad2-97215291bebf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954427874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.3954427874
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.267163865
Short name T469
Test name
Test status
Simulation time 22244884 ps
CPU time 1.56 seconds
Started Jul 12 05:36:28 PM PDT 24
Finished Jul 12 05:36:31 PM PDT 24
Peak memory 221752 kb
Host smart-f1d99471-5e45-4984-b438-18fe55e60399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267163865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.267163865
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.9993258
Short name T335
Test name
Test status
Simulation time 230319100 ps
CPU time 10.42 seconds
Started Jul 12 05:36:28 PM PDT 24
Finished Jul 12 05:36:44 PM PDT 24
Peak memory 225980 kb
Host smart-7315f278-e1bf-4f7a-855a-521d2804f809
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9993258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.9993258
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.996032699
Short name T642
Test name
Test status
Simulation time 1204192788 ps
CPU time 12.79 seconds
Started Jul 12 05:36:31 PM PDT 24
Finished Jul 12 05:36:48 PM PDT 24
Peak memory 225944 kb
Host smart-6aabaf10-b3b2-4554-adb5-3584c8e728d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996032699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_di
gest.996032699
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.1780568532
Short name T60
Test name
Test status
Simulation time 954103026 ps
CPU time 8.81 seconds
Started Jul 12 05:36:09 PM PDT 24
Finished Jul 12 05:36:18 PM PDT 24
Peak memory 218152 kb
Host smart-ddf2698e-4b8c-4e99-8e73-cc1c07b73187
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780568532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
1780568532
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.4233433923
Short name T720
Test name
Test status
Simulation time 350893198 ps
CPU time 8.68 seconds
Started Jul 12 05:36:12 PM PDT 24
Finished Jul 12 05:36:22 PM PDT 24
Peak memory 225960 kb
Host smart-39994ce5-e716-4ca9-b7f6-0a5aeb6491bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233433923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.4233433923
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.3840616900
Short name T452
Test name
Test status
Simulation time 263918447 ps
CPU time 4.36 seconds
Started Jul 12 05:36:19 PM PDT 24
Finished Jul 12 05:36:24 PM PDT 24
Peak memory 217568 kb
Host smart-ca14d06b-c366-466f-9abc-99a3b5e9dedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840616900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3840616900
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.3542547700
Short name T863
Test name
Test status
Simulation time 1142784118 ps
CPU time 32.22 seconds
Started Jul 12 05:36:32 PM PDT 24
Finished Jul 12 05:37:09 PM PDT 24
Peak memory 250908 kb
Host smart-7b25c9e8-027b-43e9-8f29-10c2c2b561be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542547700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3542547700
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.1868115282
Short name T331
Test name
Test status
Simulation time 72367734 ps
CPU time 8.47 seconds
Started Jul 12 05:36:29 PM PDT 24
Finished Jul 12 05:36:40 PM PDT 24
Peak memory 250912 kb
Host smart-558e575c-9931-4154-ae9c-0323974a2fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868115282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1868115282
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2155298573
Short name T3
Test name
Test status
Simulation time 54688335 ps
CPU time 0.88 seconds
Started Jul 12 05:36:30 PM PDT 24
Finished Jul 12 05:36:34 PM PDT 24
Peak memory 211888 kb
Host smart-1683a681-b752-4239-83e4-d534daee7920
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155298573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.2155298573
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.2088576413
Short name T858
Test name
Test status
Simulation time 44908055 ps
CPU time 1.02 seconds
Started Jul 12 05:35:30 PM PDT 24
Finished Jul 12 05:35:32 PM PDT 24
Peak memory 208920 kb
Host smart-9be15829-d317-4d69-8e57-9be8065a2c9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088576413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2088576413
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.1155021748
Short name T409
Test name
Test status
Simulation time 267755087 ps
CPU time 10.84 seconds
Started Jul 12 05:35:21 PM PDT 24
Finished Jul 12 05:35:32 PM PDT 24
Peak memory 218172 kb
Host smart-3f94c45d-b86d-42fe-82a5-24ff8b580e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155021748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.1155021748
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.3429694324
Short name T763
Test name
Test status
Simulation time 1452291191 ps
CPU time 10.31 seconds
Started Jul 12 05:35:23 PM PDT 24
Finished Jul 12 05:35:34 PM PDT 24
Peak memory 217304 kb
Host smart-a630ca47-e301-4af7-bdc3-983846756ff2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429694324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.3429694324
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1176434461
Short name T279
Test name
Test status
Simulation time 1906609990 ps
CPU time 43.79 seconds
Started Jul 12 05:35:25 PM PDT 24
Finished Jul 12 05:36:10 PM PDT 24
Peak memory 225976 kb
Host smart-5d98e237-45ad-4f17-94a1-b6b0f5b5e0cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176434461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1176434461
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.2017207013
Short name T765
Test name
Test status
Simulation time 538794609 ps
CPU time 7.81 seconds
Started Jul 12 05:35:25 PM PDT 24
Finished Jul 12 05:35:34 PM PDT 24
Peak memory 217640 kb
Host smart-45d95b7e-cd68-4059-840f-df2829e4990a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017207013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.2
017207013
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2979791990
Short name T728
Test name
Test status
Simulation time 521862964 ps
CPU time 8.85 seconds
Started Jul 12 05:35:20 PM PDT 24
Finished Jul 12 05:35:29 PM PDT 24
Peak memory 218160 kb
Host smart-3b958076-5d9b-4058-8c8d-b5a2f7735ed1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979791990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2979791990
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1471330758
Short name T297
Test name
Test status
Simulation time 912489702 ps
CPU time 26.4 seconds
Started Jul 12 05:35:23 PM PDT 24
Finished Jul 12 05:35:51 PM PDT 24
Peak memory 217648 kb
Host smart-bd50aafb-2ad2-4280-99ae-999a90cf75bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471330758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.1471330758
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1355632040
Short name T312
Test name
Test status
Simulation time 2325070806 ps
CPU time 11.41 seconds
Started Jul 12 05:35:23 PM PDT 24
Finished Jul 12 05:35:35 PM PDT 24
Peak memory 217680 kb
Host smart-05300fec-1297-476b-ac0f-1e7f8ec8b7a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355632040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1355632040
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.3670865983
Short name T99
Test name
Test status
Simulation time 11479775352 ps
CPU time 56.32 seconds
Started Jul 12 05:35:25 PM PDT 24
Finished Jul 12 05:36:23 PM PDT 24
Peak memory 275680 kb
Host smart-f6587bde-49bf-4336-be50-9b08cc57f687
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670865983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.3670865983
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.1117726084
Short name T779
Test name
Test status
Simulation time 1685451223 ps
CPU time 14.03 seconds
Started Jul 12 05:35:31 PM PDT 24
Finished Jul 12 05:35:47 PM PDT 24
Peak memory 222816 kb
Host smart-aa83478c-a4a0-4f1a-92b0-3bb478cb7c1d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117726084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.1117726084
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3935500975
Short name T842
Test name
Test status
Simulation time 383768536 ps
CPU time 3.38 seconds
Started Jul 12 05:35:21 PM PDT 24
Finished Jul 12 05:35:25 PM PDT 24
Peak memory 218372 kb
Host smart-dcb304c7-4495-473f-b859-f3d521b7357e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935500975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3935500975
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1137567498
Short name T836
Test name
Test status
Simulation time 324376110 ps
CPU time 8.76 seconds
Started Jul 12 05:35:24 PM PDT 24
Finished Jul 12 05:35:35 PM PDT 24
Peak memory 222856 kb
Host smart-fbeb4077-36f4-4c4d-8e6f-dfdde8cbe10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137567498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1137567498
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.131049576
Short name T80
Test name
Test status
Simulation time 312091249 ps
CPU time 31.4 seconds
Started Jul 12 05:35:31 PM PDT 24
Finished Jul 12 05:36:04 PM PDT 24
Peak memory 284356 kb
Host smart-88f986c7-38ef-4b2a-abdf-cbbe285cff13
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131049576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.131049576
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.809609144
Short name T271
Test name
Test status
Simulation time 1198473883 ps
CPU time 12.95 seconds
Started Jul 12 05:35:22 PM PDT 24
Finished Jul 12 05:35:36 PM PDT 24
Peak memory 225968 kb
Host smart-49374e41-d237-4fdc-993e-f26c10c1d3a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809609144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.809609144
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2726157892
Short name T741
Test name
Test status
Simulation time 362124842 ps
CPU time 11.33 seconds
Started Jul 12 05:35:32 PM PDT 24
Finished Jul 12 05:35:44 PM PDT 24
Peak memory 225980 kb
Host smart-0109506a-80f0-4fa2-9927-f700c9c52cda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726157892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2726157892
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.3621084661
Short name T585
Test name
Test status
Simulation time 278747286 ps
CPU time 10.85 seconds
Started Jul 12 05:35:29 PM PDT 24
Finished Jul 12 05:35:40 PM PDT 24
Peak memory 225972 kb
Host smart-c3b1f0e2-051f-4334-b726-3f9db4f3c922
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621084661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.3
621084661
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.3207046993
Short name T845
Test name
Test status
Simulation time 525303165 ps
CPU time 11.63 seconds
Started Jul 12 05:35:23 PM PDT 24
Finished Jul 12 05:35:36 PM PDT 24
Peak memory 224900 kb
Host smart-3d16e4d2-ee0e-44b6-8bce-9a8534c2265b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207046993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3207046993
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.4127874551
Short name T848
Test name
Test status
Simulation time 22952955 ps
CPU time 1.99 seconds
Started Jul 12 05:35:22 PM PDT 24
Finished Jul 12 05:35:25 PM PDT 24
Peak memory 223456 kb
Host smart-83467ed8-ca2b-4d12-914a-78235ad0a80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127874551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.4127874551
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.1639832472
Short name T390
Test name
Test status
Simulation time 201346078 ps
CPU time 22.48 seconds
Started Jul 12 05:35:25 PM PDT 24
Finished Jul 12 05:35:49 PM PDT 24
Peak memory 250940 kb
Host smart-40e0e694-e91f-4c30-9500-85506e2a5c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639832472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1639832472
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.4116503537
Short name T519
Test name
Test status
Simulation time 405261020 ps
CPU time 11.9 seconds
Started Jul 12 05:35:19 PM PDT 24
Finished Jul 12 05:35:31 PM PDT 24
Peak memory 250928 kb
Host smart-0750304c-65fb-4b28-b8eb-a1f6303f49aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116503537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.4116503537
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2625632548
Short name T20
Test name
Test status
Simulation time 1191681929 ps
CPU time 18.86 seconds
Started Jul 12 05:35:36 PM PDT 24
Finished Jul 12 05:35:57 PM PDT 24
Peak memory 226276 kb
Host smart-efc24df7-5c02-4ebf-a5be-b300b05a1f68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625632548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2625632548
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.4043769038
Short name T372
Test name
Test status
Simulation time 24355227 ps
CPU time 0.94 seconds
Started Jul 12 05:35:21 PM PDT 24
Finished Jul 12 05:35:23 PM PDT 24
Peak memory 211612 kb
Host smart-b44a130a-4cac-4933-bac2-1ef82255a612
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043769038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.4043769038
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1279160321
Short name T770
Test name
Test status
Simulation time 136117060 ps
CPU time 0.82 seconds
Started Jul 12 05:36:27 PM PDT 24
Finished Jul 12 05:36:30 PM PDT 24
Peak memory 208724 kb
Host smart-eb4f3891-4c41-4672-9976-64f13633506c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279160321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1279160321
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3814993143
Short name T168
Test name
Test status
Simulation time 744248868 ps
CPU time 17.14 seconds
Started Jul 12 05:36:17 PM PDT 24
Finished Jul 12 05:36:35 PM PDT 24
Peak memory 218052 kb
Host smart-a89d6bb3-0ac0-4bf2-acdc-d3b193cc2273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814993143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3814993143
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.2266173869
Short name T175
Test name
Test status
Simulation time 688266984 ps
CPU time 2.39 seconds
Started Jul 12 05:36:21 PM PDT 24
Finished Jul 12 05:36:25 PM PDT 24
Peak memory 217092 kb
Host smart-f0ee0324-a6d7-4946-9202-4e2a3bd95b61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266173869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.2266173869
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2978899704
Short name T771
Test name
Test status
Simulation time 133007432 ps
CPU time 3.54 seconds
Started Jul 12 05:36:21 PM PDT 24
Finished Jul 12 05:36:25 PM PDT 24
Peak memory 218152 kb
Host smart-15cac882-033d-48e0-b06c-e88ba3e38a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978899704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2978899704
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.2915201049
Short name T548
Test name
Test status
Simulation time 1372539222 ps
CPU time 19.63 seconds
Started Jul 12 05:36:27 PM PDT 24
Finished Jul 12 05:36:49 PM PDT 24
Peak memory 225836 kb
Host smart-991c3c2f-ee26-432b-9ded-460aa68cf74c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915201049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2915201049
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.1365063017
Short name T357
Test name
Test status
Simulation time 284967173 ps
CPU time 8.95 seconds
Started Jul 12 05:36:25 PM PDT 24
Finished Jul 12 05:36:35 PM PDT 24
Peak memory 225768 kb
Host smart-ecd86eab-c28f-45f7-963b-7206a83d2fd3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365063017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.1365063017
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1527993636
Short name T807
Test name
Test status
Simulation time 585889400 ps
CPU time 15.29 seconds
Started Jul 12 05:36:15 PM PDT 24
Finished Jul 12 05:36:31 PM PDT 24
Peak memory 218148 kb
Host smart-858de63d-e3b1-4754-95a1-befc1303b9db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527993636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1527993636
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.422806767
Short name T729
Test name
Test status
Simulation time 296672644 ps
CPU time 12.15 seconds
Started Jul 12 05:36:34 PM PDT 24
Finished Jul 12 05:36:50 PM PDT 24
Peak memory 225976 kb
Host smart-fe87dd5a-362b-4722-bc05-c6234e0ed3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422806767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.422806767
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.2169171044
Short name T378
Test name
Test status
Simulation time 21390304 ps
CPU time 1.48 seconds
Started Jul 12 05:36:29 PM PDT 24
Finished Jul 12 05:36:33 PM PDT 24
Peak memory 217528 kb
Host smart-377dca60-c588-47bf-b492-f4364e3a42e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169171044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.2169171044
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.2639362666
Short name T482
Test name
Test status
Simulation time 418308929 ps
CPU time 23.17 seconds
Started Jul 12 05:36:27 PM PDT 24
Finished Jul 12 05:36:51 PM PDT 24
Peak memory 250912 kb
Host smart-abd8c6ba-b870-4bc4-828e-1c248ab919b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639362666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2639362666
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.3853735399
Short name T244
Test name
Test status
Simulation time 70100049 ps
CPU time 8.19 seconds
Started Jul 12 05:36:16 PM PDT 24
Finished Jul 12 05:36:26 PM PDT 24
Peak memory 250936 kb
Host smart-f79b9060-d1ca-420e-b1f5-0e300dc9a117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853735399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.3853735399
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.4204831257
Short name T82
Test name
Test status
Simulation time 80311998372 ps
CPU time 611.66 seconds
Started Jul 12 05:36:23 PM PDT 24
Finished Jul 12 05:46:35 PM PDT 24
Peak memory 283748 kb
Host smart-8cf6cb41-0207-48fa-8f22-1dbc448e586a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204831257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.4204831257
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1540638414
Short name T715
Test name
Test status
Simulation time 15150551 ps
CPU time 0.85 seconds
Started Jul 12 05:36:26 PM PDT 24
Finished Jul 12 05:36:28 PM PDT 24
Peak memory 211920 kb
Host smart-88ac8b02-f788-46fa-83bd-4348b3355fdf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540638414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1540638414
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.1146992370
Short name T502
Test name
Test status
Simulation time 21471557 ps
CPU time 1 seconds
Started Jul 12 05:36:29 PM PDT 24
Finished Jul 12 05:36:31 PM PDT 24
Peak memory 208976 kb
Host smart-981b690d-1ab6-480c-b3e9-0427a043ac36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146992370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1146992370
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.2020286924
Short name T254
Test name
Test status
Simulation time 271701753 ps
CPU time 12.79 seconds
Started Jul 12 05:36:30 PM PDT 24
Finished Jul 12 05:36:47 PM PDT 24
Peak memory 225964 kb
Host smart-0db5da3e-d39d-44ce-a92d-bd9501d358be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020286924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.2020286924
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.2651035390
Short name T29
Test name
Test status
Simulation time 1602013634 ps
CPU time 3.65 seconds
Started Jul 12 05:36:24 PM PDT 24
Finished Jul 12 05:36:29 PM PDT 24
Peak memory 217212 kb
Host smart-df30cb73-f3cb-4c9e-9098-f7af44162394
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651035390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.2651035390
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.1001467066
Short name T661
Test name
Test status
Simulation time 23234632 ps
CPU time 1.95 seconds
Started Jul 12 05:36:29 PM PDT 24
Finished Jul 12 05:36:40 PM PDT 24
Peak memory 218028 kb
Host smart-b48fe7c8-e9f0-4147-804c-6ae2b120bea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001467066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1001467066
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.3122492407
Short name T767
Test name
Test status
Simulation time 722180760 ps
CPU time 14.81 seconds
Started Jul 12 05:36:17 PM PDT 24
Finished Jul 12 05:36:33 PM PDT 24
Peak memory 218164 kb
Host smart-6497cd37-6a1b-4825-a280-cfdb8ac471ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122492407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3122492407
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2539464537
Short name T447
Test name
Test status
Simulation time 233050584 ps
CPU time 10.6 seconds
Started Jul 12 05:36:32 PM PDT 24
Finished Jul 12 05:36:47 PM PDT 24
Peak memory 225944 kb
Host smart-cab1ac42-2218-4c6c-be2d-f61560b9493d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539464537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2539464537
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.2965494117
Short name T308
Test name
Test status
Simulation time 280247966 ps
CPU time 10.03 seconds
Started Jul 12 05:36:30 PM PDT 24
Finished Jul 12 05:36:44 PM PDT 24
Peak memory 218168 kb
Host smart-c09a9086-de1e-408c-b755-5f9e67313884
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965494117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
2965494117
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2916869657
Short name T348
Test name
Test status
Simulation time 194395947 ps
CPU time 8.74 seconds
Started Jul 12 05:36:26 PM PDT 24
Finished Jul 12 05:36:36 PM PDT 24
Peak memory 224796 kb
Host smart-1a5a3884-982e-4654-b00e-0de37bad186c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916869657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2916869657
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.2637565416
Short name T851
Test name
Test status
Simulation time 36823521 ps
CPU time 1.6 seconds
Started Jul 12 05:36:20 PM PDT 24
Finished Jul 12 05:36:22 PM PDT 24
Peak memory 213880 kb
Host smart-96ffa338-542e-4c1d-937a-159a06a26936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637565416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.2637565416
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.2992636857
Short name T590
Test name
Test status
Simulation time 2480276591 ps
CPU time 26.22 seconds
Started Jul 12 05:36:11 PM PDT 24
Finished Jul 12 05:36:39 PM PDT 24
Peak memory 251008 kb
Host smart-4b22eee7-9205-401a-8715-e1bc122c5774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992636857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2992636857
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.1538054090
Short name T530
Test name
Test status
Simulation time 41599788 ps
CPU time 2.8 seconds
Started Jul 12 05:36:24 PM PDT 24
Finished Jul 12 05:36:27 PM PDT 24
Peak memory 218152 kb
Host smart-01377c6b-3f6e-4749-82d4-798943fc2f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538054090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1538054090
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.4109175262
Short name T374
Test name
Test status
Simulation time 10353351563 ps
CPU time 298.7 seconds
Started Jul 12 05:36:28 PM PDT 24
Finished Jul 12 05:41:29 PM PDT 24
Peak memory 283812 kb
Host smart-ad14cb05-3912-4dfb-854b-6c31a5c9c45e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109175262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.4109175262
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3811986386
Short name T278
Test name
Test status
Simulation time 216568861 ps
CPU time 0.95 seconds
Started Jul 12 05:36:32 PM PDT 24
Finished Jul 12 05:36:37 PM PDT 24
Peak memory 212792 kb
Host smart-74956529-680d-4d59-8d58-148878a936b2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811986386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.3811986386
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.4094051623
Short name T814
Test name
Test status
Simulation time 22920862 ps
CPU time 0.88 seconds
Started Jul 12 05:36:30 PM PDT 24
Finished Jul 12 05:36:39 PM PDT 24
Peak memory 208812 kb
Host smart-752e1c7d-ba0d-4617-9f71-a6f24196b2f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094051623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.4094051623
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.3422916676
Short name T817
Test name
Test status
Simulation time 257150454 ps
CPU time 11.13 seconds
Started Jul 12 05:37:01 PM PDT 24
Finished Jul 12 05:37:16 PM PDT 24
Peak memory 218144 kb
Host smart-89c9cbda-8ba2-43a7-95c9-56169faa1df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422916676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3422916676
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.2747138009
Short name T860
Test name
Test status
Simulation time 632124314 ps
CPU time 2.64 seconds
Started Jul 12 05:36:32 PM PDT 24
Finished Jul 12 05:36:39 PM PDT 24
Peak memory 217160 kb
Host smart-6323c514-b725-4f0a-9cc0-5a9d57b0450f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747138009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.2747138009
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.1669917747
Short name T768
Test name
Test status
Simulation time 51594853 ps
CPU time 2.27 seconds
Started Jul 12 05:36:30 PM PDT 24
Finished Jul 12 05:36:36 PM PDT 24
Peak memory 218028 kb
Host smart-9daca925-bdb1-4e85-8357-62d74a0330ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669917747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1669917747
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.2677454864
Short name T23
Test name
Test status
Simulation time 2287297564 ps
CPU time 8.09 seconds
Started Jul 12 05:36:30 PM PDT 24
Finished Jul 12 05:36:41 PM PDT 24
Peak memory 226032 kb
Host smart-eefaf776-74f9-4539-8c0f-1faa63e9ffa7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677454864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.2677454864
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.4114424557
Short name T843
Test name
Test status
Simulation time 227895017 ps
CPU time 9.34 seconds
Started Jul 12 05:36:34 PM PDT 24
Finished Jul 12 05:36:47 PM PDT 24
Peak memory 218104 kb
Host smart-8f791e04-552c-4ea4-bd28-91a583cf7419
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114424557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
4114424557
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.3637004845
Short name T290
Test name
Test status
Simulation time 332811366 ps
CPU time 10.16 seconds
Started Jul 12 05:36:25 PM PDT 24
Finished Jul 12 05:36:36 PM PDT 24
Peak memory 218232 kb
Host smart-463de2db-f4f8-41cb-a4fa-40b9f80a7d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637004845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3637004845
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.2805416485
Short name T236
Test name
Test status
Simulation time 23877695 ps
CPU time 0.99 seconds
Started Jul 12 05:36:32 PM PDT 24
Finished Jul 12 05:36:37 PM PDT 24
Peak memory 217648 kb
Host smart-877ad357-b2a8-4a91-8acc-22a800c7f6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805416485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2805416485
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.281254924
Short name T563
Test name
Test status
Simulation time 1395296011 ps
CPU time 39.45 seconds
Started Jul 12 05:36:26 PM PDT 24
Finished Jul 12 05:37:06 PM PDT 24
Peak memory 250912 kb
Host smart-e062cc3a-60dc-4aa8-81e1-13986fb0c68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281254924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.281254924
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1957529914
Short name T527
Test name
Test status
Simulation time 324531710 ps
CPU time 2.8 seconds
Started Jul 12 05:36:28 PM PDT 24
Finished Jul 12 05:36:37 PM PDT 24
Peak memory 218108 kb
Host smart-60391a41-aefe-4bf2-9184-433dd0d3c90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957529914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1957529914
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.416523487
Short name T449
Test name
Test status
Simulation time 477934273 ps
CPU time 12.48 seconds
Started Jul 12 05:36:27 PM PDT 24
Finished Jul 12 05:36:40 PM PDT 24
Peak memory 225960 kb
Host smart-c4938e1d-6355-4ea5-b4f3-f3eeb7331bc0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416523487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.416523487
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.320395718
Short name T237
Test name
Test status
Simulation time 12071313 ps
CPU time 0.88 seconds
Started Jul 12 05:36:16 PM PDT 24
Finished Jul 12 05:36:18 PM PDT 24
Peak memory 211720 kb
Host smart-335e2ca3-41c2-4f1a-ad71-80b5071a898d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320395718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct
rl_volatile_unlock_smoke.320395718
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.409585355
Short name T791
Test name
Test status
Simulation time 57436501 ps
CPU time 1.03 seconds
Started Jul 12 05:36:26 PM PDT 24
Finished Jul 12 05:36:28 PM PDT 24
Peak memory 208936 kb
Host smart-46256b8d-2a4b-4a9b-a30d-f82f3caa1d20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409585355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.409585355
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3503809937
Short name T351
Test name
Test status
Simulation time 1109543949 ps
CPU time 14.84 seconds
Started Jul 12 05:36:30 PM PDT 24
Finished Jul 12 05:36:49 PM PDT 24
Peak memory 225968 kb
Host smart-58604df2-8b3d-4f28-a2fa-993e0b3fb8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503809937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3503809937
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.1612071002
Short name T792
Test name
Test status
Simulation time 2628836550 ps
CPU time 9.61 seconds
Started Jul 12 05:36:30 PM PDT 24
Finished Jul 12 05:36:44 PM PDT 24
Peak memory 217708 kb
Host smart-9ec97d99-76e8-434a-8465-7417d2789c21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612071002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1612071002
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.472934294
Short name T415
Test name
Test status
Simulation time 37631030 ps
CPU time 2.01 seconds
Started Jul 12 05:37:03 PM PDT 24
Finished Jul 12 05:37:09 PM PDT 24
Peak memory 218192 kb
Host smart-9367e6b2-931f-4aa5-b4f5-6ad31bb1440c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472934294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.472934294
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.144406662
Short name T396
Test name
Test status
Simulation time 1183539001 ps
CPU time 11.54 seconds
Started Jul 12 05:36:30 PM PDT 24
Finished Jul 12 05:36:44 PM PDT 24
Peak memory 225980 kb
Host smart-919ba355-971d-4541-8ee6-c857ebba98a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144406662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.144406662
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.2554520109
Short name T470
Test name
Test status
Simulation time 1927569673 ps
CPU time 16.99 seconds
Started Jul 12 05:36:28 PM PDT 24
Finished Jul 12 05:36:46 PM PDT 24
Peak memory 225968 kb
Host smart-ece8f391-02fa-4365-a79b-3be28916c9f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554520109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.2554520109
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3458270668
Short name T507
Test name
Test status
Simulation time 1180372214 ps
CPU time 10.96 seconds
Started Jul 12 05:36:31 PM PDT 24
Finished Jul 12 05:36:47 PM PDT 24
Peak memory 225844 kb
Host smart-33399af0-0769-4a5f-bc67-9aa4111275aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458270668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
3458270668
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.253907059
Short name T345
Test name
Test status
Simulation time 750490646 ps
CPU time 11.96 seconds
Started Jul 12 05:36:28 PM PDT 24
Finished Jul 12 05:36:44 PM PDT 24
Peak memory 218292 kb
Host smart-8ca6ced7-667d-4ac6-9021-c4d00a1331ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253907059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.253907059
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.745460892
Short name T426
Test name
Test status
Simulation time 705813614 ps
CPU time 4.34 seconds
Started Jul 12 05:36:31 PM PDT 24
Finished Jul 12 05:36:40 PM PDT 24
Peak memory 217684 kb
Host smart-97716712-61f1-476b-a776-486e4e2d7374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745460892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.745460892
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.2361812852
Short name T607
Test name
Test status
Simulation time 894945480 ps
CPU time 27.03 seconds
Started Jul 12 05:37:04 PM PDT 24
Finished Jul 12 05:37:35 PM PDT 24
Peak memory 247044 kb
Host smart-558528c7-9f5c-44d2-a305-c42540d2720f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361812852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.2361812852
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.934572620
Short name T187
Test name
Test status
Simulation time 289649785 ps
CPU time 8.71 seconds
Started Jul 12 05:36:31 PM PDT 24
Finished Jul 12 05:36:44 PM PDT 24
Peak memory 251140 kb
Host smart-0dacce0b-8588-4a27-86f8-d78e917ef49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934572620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.934572620
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.570876098
Short name T710
Test name
Test status
Simulation time 7900835663 ps
CPU time 157.73 seconds
Started Jul 12 05:36:31 PM PDT 24
Finished Jul 12 05:39:12 PM PDT 24
Peak memory 223984 kb
Host smart-335f4b43-7c20-42cb-b676-f24f3f955100
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570876098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.570876098
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.1069771975
Short name T58
Test name
Test status
Simulation time 28194433347 ps
CPU time 1125.47 seconds
Started Jul 12 05:36:26 PM PDT 24
Finished Jul 12 05:55:13 PM PDT 24
Peak memory 496740 kb
Host smart-8f761e75-7558-43a7-9cdf-c0fbdf625e97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1069771975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.1069771975
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3757854330
Short name T105
Test name
Test status
Simulation time 43243547 ps
CPU time 0.95 seconds
Started Jul 12 05:36:31 PM PDT 24
Finished Jul 12 05:36:36 PM PDT 24
Peak memory 211728 kb
Host smart-69736b46-9059-4473-bbfc-a497c18029e9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757854330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3757854330
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.2691345106
Short name T376
Test name
Test status
Simulation time 118265451 ps
CPU time 0.83 seconds
Started Jul 12 05:36:32 PM PDT 24
Finished Jul 12 05:36:37 PM PDT 24
Peak memory 208744 kb
Host smart-804e132e-740d-406b-a54e-1fc1cca16974
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691345106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.2691345106
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.3492298517
Short name T270
Test name
Test status
Simulation time 399700553 ps
CPU time 12.55 seconds
Started Jul 12 05:36:33 PM PDT 24
Finished Jul 12 05:36:50 PM PDT 24
Peak memory 217992 kb
Host smart-f18dc4d2-0e67-48c7-ad61-560e0adbfbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492298517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3492298517
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.1868144438
Short name T662
Test name
Test status
Simulation time 2074898617 ps
CPU time 12.36 seconds
Started Jul 12 05:36:40 PM PDT 24
Finished Jul 12 05:36:53 PM PDT 24
Peak memory 217360 kb
Host smart-db3a0e0b-04c5-4d1e-a4a6-ca7205d59b95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868144438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.1868144438
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3385838248
Short name T622
Test name
Test status
Simulation time 146640320 ps
CPU time 2.85 seconds
Started Jul 12 05:36:29 PM PDT 24
Finished Jul 12 05:36:34 PM PDT 24
Peak memory 222116 kb
Host smart-c76f893d-06f4-49b7-8b05-cea3586bdebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385838248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3385838248
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.615859631
Short name T497
Test name
Test status
Simulation time 1565827426 ps
CPU time 12.84 seconds
Started Jul 12 05:36:25 PM PDT 24
Finished Jul 12 05:36:39 PM PDT 24
Peak memory 225960 kb
Host smart-545c3c98-c0f4-472a-9e60-746a2a7190e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615859631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.615859631
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2377839977
Short name T22
Test name
Test status
Simulation time 259240824 ps
CPU time 10.13 seconds
Started Jul 12 05:36:31 PM PDT 24
Finished Jul 12 05:36:46 PM PDT 24
Peak memory 226068 kb
Host smart-c491f98c-24be-4eb5-85dc-508f067a6d77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377839977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.2377839977
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3349768608
Short name T540
Test name
Test status
Simulation time 2467862605 ps
CPU time 19.58 seconds
Started Jul 12 05:37:06 PM PDT 24
Finished Jul 12 05:37:31 PM PDT 24
Peak memory 218260 kb
Host smart-510b1822-aa43-4a54-9212-b80339132bc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349768608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3349768608
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.3230708847
Short name T189
Test name
Test status
Simulation time 87984777 ps
CPU time 1.47 seconds
Started Jul 12 05:36:27 PM PDT 24
Finished Jul 12 05:36:30 PM PDT 24
Peak memory 213828 kb
Host smart-d768e269-a166-43b1-8d3e-5ece2316e988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230708847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3230708847
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.4105365356
Short name T657
Test name
Test status
Simulation time 327051352 ps
CPU time 21.69 seconds
Started Jul 12 05:36:31 PM PDT 24
Finished Jul 12 05:36:58 PM PDT 24
Peak memory 245468 kb
Host smart-de5ca832-8bec-4dd8-9fe8-99f4da58c421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105365356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.4105365356
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.541120052
Short name T389
Test name
Test status
Simulation time 203593837 ps
CPU time 5.87 seconds
Started Jul 12 05:36:35 PM PDT 24
Finished Jul 12 05:36:44 PM PDT 24
Peak memory 247056 kb
Host smart-049dafaa-7283-4238-923f-602dcd532a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541120052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.541120052
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.448601688
Short name T54
Test name
Test status
Simulation time 44920380463 ps
CPU time 661.45 seconds
Started Jul 12 05:36:33 PM PDT 24
Finished Jul 12 05:47:39 PM PDT 24
Peak memory 283620 kb
Host smart-052eea16-05c5-49fe-9336-0921bbdad676
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448601688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.448601688
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.3240308191
Short name T158
Test name
Test status
Simulation time 237647631504 ps
CPU time 449.32 seconds
Started Jul 12 05:36:30 PM PDT 24
Finished Jul 12 05:44:03 PM PDT 24
Peak memory 340348 kb
Host smart-2b857fc5-1cdf-4748-8067-a8469df90740
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3240308191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.3240308191
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3292657473
Short name T689
Test name
Test status
Simulation time 49100937 ps
CPU time 0.97 seconds
Started Jul 12 05:36:30 PM PDT 24
Finished Jul 12 05:36:35 PM PDT 24
Peak memory 213128 kb
Host smart-665f0ba4-e2e9-4a74-ba08-5c9a68668e56
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292657473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3292657473
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.1637473062
Short name T824
Test name
Test status
Simulation time 28270232 ps
CPU time 0.87 seconds
Started Jul 12 05:37:06 PM PDT 24
Finished Jul 12 05:37:12 PM PDT 24
Peak memory 208956 kb
Host smart-1f36ae83-6af6-4019-a055-d09c11bf3204
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637473062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.1637473062
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.3071992166
Short name T697
Test name
Test status
Simulation time 191397504 ps
CPU time 10.22 seconds
Started Jul 12 05:37:01 PM PDT 24
Finished Jul 12 05:37:15 PM PDT 24
Peak memory 225852 kb
Host smart-b4c9756f-8e59-4a72-9c9f-3aec056e10d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071992166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3071992166
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3620896847
Short name T342
Test name
Test status
Simulation time 777868254 ps
CPU time 19.47 seconds
Started Jul 12 05:36:30 PM PDT 24
Finished Jul 12 05:36:52 PM PDT 24
Peak memory 217428 kb
Host smart-e2585b4f-6322-46df-960f-5c6551b8c2be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620896847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3620896847
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.2113357620
Short name T274
Test name
Test status
Simulation time 136839977 ps
CPU time 2.06 seconds
Started Jul 12 05:36:34 PM PDT 24
Finished Jul 12 05:36:40 PM PDT 24
Peak memory 218152 kb
Host smart-092deb27-10c2-45de-97da-0d84376dcfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113357620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2113357620
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.1708478454
Short name T702
Test name
Test status
Simulation time 993941143 ps
CPU time 11.54 seconds
Started Jul 12 05:36:30 PM PDT 24
Finished Jul 12 05:36:46 PM PDT 24
Peak memory 218832 kb
Host smart-83c873d1-61f4-41f1-9723-15f500103d67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708478454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1708478454
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.3841301400
Short name T722
Test name
Test status
Simulation time 289770187 ps
CPU time 12.2 seconds
Started Jul 12 05:36:29 PM PDT 24
Finished Jul 12 05:36:43 PM PDT 24
Peak memory 225984 kb
Host smart-e47690b1-174f-4283-beb0-a044941a0f7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841301400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.3841301400
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.674212168
Short name T798
Test name
Test status
Simulation time 502480335 ps
CPU time 16.33 seconds
Started Jul 12 05:36:31 PM PDT 24
Finished Jul 12 05:36:51 PM PDT 24
Peak memory 225996 kb
Host smart-5eb6f0c4-09e9-497f-916e-10bf20547d17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674212168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.674212168
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.829142477
Short name T53
Test name
Test status
Simulation time 1567970388 ps
CPU time 9.13 seconds
Started Jul 12 05:36:36 PM PDT 24
Finished Jul 12 05:36:48 PM PDT 24
Peak memory 224984 kb
Host smart-2093f658-dd32-41a1-b3da-f1e9b85d225f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829142477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.829142477
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3684852005
Short name T63
Test name
Test status
Simulation time 124253882 ps
CPU time 1.58 seconds
Started Jul 12 05:36:30 PM PDT 24
Finished Jul 12 05:36:35 PM PDT 24
Peak memory 217620 kb
Host smart-90ceaf86-9405-40d2-998f-43c750abeb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684852005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3684852005
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.1566374171
Short name T360
Test name
Test status
Simulation time 270346666 ps
CPU time 27.75 seconds
Started Jul 12 05:36:36 PM PDT 24
Finished Jul 12 05:37:07 PM PDT 24
Peak memory 250908 kb
Host smart-d75280d9-0d1c-4ae9-87ef-be1e21863a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566374171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.1566374171
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.917797100
Short name T685
Test name
Test status
Simulation time 390299295 ps
CPU time 6.77 seconds
Started Jul 12 05:36:31 PM PDT 24
Finished Jul 12 05:36:41 PM PDT 24
Peak memory 246916 kb
Host smart-e71ef671-4f55-47a3-b7e5-f9fe061ba81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917797100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.917797100
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.465204205
Short name T361
Test name
Test status
Simulation time 4615372124 ps
CPU time 154.18 seconds
Started Jul 12 05:36:31 PM PDT 24
Finished Jul 12 05:39:10 PM PDT 24
Peak memory 220180 kb
Host smart-e019e60c-b6c2-4809-8860-ffc945168adf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465204205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.465204205
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.4042123469
Short name T835
Test name
Test status
Simulation time 17735948310 ps
CPU time 305.91 seconds
Started Jul 12 05:36:26 PM PDT 24
Finished Jul 12 05:41:33 PM PDT 24
Peak memory 286536 kb
Host smart-7fdddc50-f333-4f3e-a20a-30e532b04dfc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4042123469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.4042123469
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1879591321
Short name T593
Test name
Test status
Simulation time 26484269 ps
CPU time 1.01 seconds
Started Jul 12 05:36:35 PM PDT 24
Finished Jul 12 05:36:39 PM PDT 24
Peak memory 217656 kb
Host smart-56838fc5-92d1-4706-889f-14a289001334
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879591321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.1879591321
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.369210957
Short name T655
Test name
Test status
Simulation time 22609214 ps
CPU time 0.91 seconds
Started Jul 12 05:36:37 PM PDT 24
Finished Jul 12 05:36:40 PM PDT 24
Peak memory 208972 kb
Host smart-94ba0334-e6e2-4c50-9a6f-506966800cb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369210957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.369210957
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.3511941571
Short name T556
Test name
Test status
Simulation time 1835072405 ps
CPU time 16.92 seconds
Started Jul 12 05:37:01 PM PDT 24
Finished Jul 12 05:37:22 PM PDT 24
Peak memory 218100 kb
Host smart-35a0416b-fbfd-4ebf-bea2-178d0ca153ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511941571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3511941571
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.4249713290
Short name T28
Test name
Test status
Simulation time 1235095664 ps
CPU time 3.41 seconds
Started Jul 12 06:44:02 PM PDT 24
Finished Jul 12 06:44:12 PM PDT 24
Peak memory 216904 kb
Host smart-3535c6e9-405f-4192-a3e4-28b6da7f6009
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249713290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.4249713290
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.810836345
Short name T832
Test name
Test status
Simulation time 1358118910 ps
CPU time 4.52 seconds
Started Jul 12 06:28:34 PM PDT 24
Finished Jul 12 06:28:39 PM PDT 24
Peak memory 218144 kb
Host smart-f7751ad9-1587-4241-b532-57fec5c1ddd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810836345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.810836345
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.416035481
Short name T861
Test name
Test status
Simulation time 583990762 ps
CPU time 12 seconds
Started Jul 12 06:28:42 PM PDT 24
Finished Jul 12 06:28:56 PM PDT 24
Peak memory 225964 kb
Host smart-b3c7e678-f175-4045-915b-27b4b0d91d13
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416035481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.416035481
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.1791664759
Short name T310
Test name
Test status
Simulation time 234266465 ps
CPU time 8.11 seconds
Started Jul 12 06:01:54 PM PDT 24
Finished Jul 12 06:02:03 PM PDT 24
Peak memory 225968 kb
Host smart-57d400d2-ba18-41c4-9d7d-7d78625224b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791664759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.1791664759
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1747509665
Short name T365
Test name
Test status
Simulation time 336329468 ps
CPU time 9.26 seconds
Started Jul 12 05:36:43 PM PDT 24
Finished Jul 12 05:36:53 PM PDT 24
Peak memory 218180 kb
Host smart-9c5992f2-fbef-470e-8eb7-0366ba7b0c74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747509665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1747509665
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.808853791
Short name T468
Test name
Test status
Simulation time 340785108 ps
CPU time 9.76 seconds
Started Jul 12 06:23:06 PM PDT 24
Finished Jul 12 06:23:16 PM PDT 24
Peak memory 225952 kb
Host smart-4532c666-9884-4343-bd6f-83cb7b99a45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808853791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.808853791
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.1524856512
Short name T436
Test name
Test status
Simulation time 28905941 ps
CPU time 2.38 seconds
Started Jul 12 05:36:29 PM PDT 24
Finished Jul 12 05:36:34 PM PDT 24
Peak memory 214300 kb
Host smart-0fd37938-aefb-44cc-8b5d-09567aa57290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524856512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1524856512
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1897588226
Short name T531
Test name
Test status
Simulation time 939785397 ps
CPU time 32.65 seconds
Started Jul 12 05:36:43 PM PDT 24
Finished Jul 12 05:37:16 PM PDT 24
Peak memory 250880 kb
Host smart-00bf25bb-4c10-46e8-9f8d-1089dffb96da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897588226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1897588226
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.1919047992
Short name T708
Test name
Test status
Simulation time 140945364 ps
CPU time 6.28 seconds
Started Jul 12 05:36:34 PM PDT 24
Finished Jul 12 05:36:44 PM PDT 24
Peak memory 247004 kb
Host smart-8d7e2857-96ef-40c5-ab10-a33ab91a0156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919047992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1919047992
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.3916975831
Short name T673
Test name
Test status
Simulation time 24722997051 ps
CPU time 146.02 seconds
Started Jul 12 05:37:01 PM PDT 24
Finished Jul 12 05:39:31 PM PDT 24
Peak memory 279512 kb
Host smart-6d27ffc3-2243-4582-9803-0bd80c623a52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916975831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.3916975831
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.2934274035
Short name T146
Test name
Test status
Simulation time 375370421091 ps
CPU time 820.96 seconds
Started Jul 12 05:36:31 PM PDT 24
Finished Jul 12 05:50:16 PM PDT 24
Peak memory 447696 kb
Host smart-c9f8fd40-a24b-465b-ad07-d5fe4aab88ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2934274035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.2934274035
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1619075802
Short name T283
Test name
Test status
Simulation time 41955680 ps
CPU time 1.04 seconds
Started Jul 12 05:36:29 PM PDT 24
Finished Jul 12 05:36:33 PM PDT 24
Peak memory 217644 kb
Host smart-bad4fa7d-55f2-45b3-980d-d9ccaa1f075a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619075802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1619075802
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.457350285
Short name T753
Test name
Test status
Simulation time 16236145 ps
CPU time 0.89 seconds
Started Jul 12 05:37:05 PM PDT 24
Finished Jul 12 05:37:11 PM PDT 24
Peak memory 208884 kb
Host smart-f653ffc3-b83a-41f0-8b1c-15423a8d195f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457350285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.457350285
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.15220387
Short name T282
Test name
Test status
Simulation time 2274186674 ps
CPU time 11.69 seconds
Started Jul 12 05:37:06 PM PDT 24
Finished Jul 12 05:37:24 PM PDT 24
Peak memory 218248 kb
Host smart-6acbdae1-2e79-40e1-8276-5101aff2028e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15220387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.15220387
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.291240823
Short name T425
Test name
Test status
Simulation time 802405866 ps
CPU time 8.73 seconds
Started Jul 12 05:37:10 PM PDT 24
Finished Jul 12 05:37:25 PM PDT 24
Peak memory 216972 kb
Host smart-2f254e20-96bc-4d1c-b737-679371b1a4e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291240823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.291240823
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.4138504470
Short name T813
Test name
Test status
Simulation time 147264834 ps
CPU time 4.08 seconds
Started Jul 12 05:38:31 PM PDT 24
Finished Jul 12 05:38:45 PM PDT 24
Peak memory 222732 kb
Host smart-8aed329c-5b38-4e12-84d3-c99a851090a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138504470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.4138504470
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.1199406174
Short name T178
Test name
Test status
Simulation time 1766092147 ps
CPU time 9.99 seconds
Started Jul 12 05:36:40 PM PDT 24
Finished Jul 12 05:36:51 PM PDT 24
Peak memory 218832 kb
Host smart-d3a52dd5-3584-4591-ad81-5885cbebb23e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199406174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.1199406174
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1724870710
Short name T406
Test name
Test status
Simulation time 1850141608 ps
CPU time 10.33 seconds
Started Jul 12 05:36:35 PM PDT 24
Finished Jul 12 05:36:49 PM PDT 24
Peak memory 225952 kb
Host smart-4b37ee1f-86bc-4bff-8a25-40aadeec8877
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724870710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.1724870710
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1656043056
Short name T711
Test name
Test status
Simulation time 954684947 ps
CPU time 14.27 seconds
Started Jul 12 05:36:38 PM PDT 24
Finished Jul 12 05:36:54 PM PDT 24
Peak memory 225844 kb
Host smart-c7f15b5f-7b78-4770-bb0e-b885bdcb1d7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656043056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1656043056
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.42244655
Short name T18
Test name
Test status
Simulation time 412476327 ps
CPU time 8.31 seconds
Started Jul 12 05:37:12 PM PDT 24
Finished Jul 12 05:37:26 PM PDT 24
Peak memory 218520 kb
Host smart-f23b7188-bfeb-4f32-9227-7f7fd4132087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42244655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.42244655
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.4097555688
Short name T392
Test name
Test status
Simulation time 80195372 ps
CPU time 1.68 seconds
Started Jul 12 05:36:38 PM PDT 24
Finished Jul 12 05:36:42 PM PDT 24
Peak memory 217636 kb
Host smart-8d7ecbe4-e70a-476c-ae4b-e658e08f6e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097555688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.4097555688
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3191449446
Short name T445
Test name
Test status
Simulation time 1292617862 ps
CPU time 23.84 seconds
Started Jul 12 05:36:37 PM PDT 24
Finished Jul 12 05:37:03 PM PDT 24
Peak memory 250792 kb
Host smart-80e9aeea-79f8-45ca-a076-f53faf7908ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191449446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3191449446
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.1095349880
Short name T846
Test name
Test status
Simulation time 82401877 ps
CPU time 6.96 seconds
Started Jul 12 05:36:37 PM PDT 24
Finished Jul 12 05:36:46 PM PDT 24
Peak memory 247144 kb
Host smart-e116540a-4090-42bf-bdd9-3c03c028e242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095349880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1095349880
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.477996619
Short name T45
Test name
Test status
Simulation time 9262480571 ps
CPU time 172.69 seconds
Started Jul 12 05:36:53 PM PDT 24
Finished Jul 12 05:39:47 PM PDT 24
Peak memory 250940 kb
Host smart-d657ea1d-dc05-424d-82a3-f8e0c9a9788e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477996619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.477996619
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.205072574
Short name T362
Test name
Test status
Simulation time 28805723 ps
CPU time 0.87 seconds
Started Jul 12 05:36:43 PM PDT 24
Finished Jul 12 05:36:44 PM PDT 24
Peak memory 208896 kb
Host smart-3360e8be-bab5-4379-bc27-bbaa3dff6e1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205072574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.205072574
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.566276196
Short name T42
Test name
Test status
Simulation time 451428430 ps
CPU time 18.5 seconds
Started Jul 12 05:36:36 PM PDT 24
Finished Jul 12 05:36:57 PM PDT 24
Peak memory 218104 kb
Host smart-12dbf798-a687-4cd7-b47f-7d0a7065dd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566276196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.566276196
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3323097910
Short name T32
Test name
Test status
Simulation time 1163411281 ps
CPU time 7.66 seconds
Started Jul 12 05:36:32 PM PDT 24
Finished Jul 12 05:36:43 PM PDT 24
Peak memory 217204 kb
Host smart-ab23778a-1307-475c-837e-d34bea7c48dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323097910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3323097910
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.622139470
Short name T553
Test name
Test status
Simulation time 277029398 ps
CPU time 3.12 seconds
Started Jul 12 05:36:57 PM PDT 24
Finished Jul 12 05:37:05 PM PDT 24
Peak memory 218156 kb
Host smart-b5691660-2e6c-480f-8b0f-27ef65cc68fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622139470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.622139470
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.1962332633
Short name T511
Test name
Test status
Simulation time 589026266 ps
CPU time 8.82 seconds
Started Jul 12 05:37:10 PM PDT 24
Finished Jul 12 05:37:25 PM PDT 24
Peak memory 225880 kb
Host smart-a5948529-c114-449d-924f-a0e8b308ee83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962332633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1962332633
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.4134909035
Short name T306
Test name
Test status
Simulation time 1390245305 ps
CPU time 11.24 seconds
Started Jul 12 05:37:12 PM PDT 24
Finished Jul 12 05:37:29 PM PDT 24
Peak memory 225880 kb
Host smart-b71b6b79-886b-46a7-9273-da8bdcf104fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134909035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.4134909035
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1371593912
Short name T340
Test name
Test status
Simulation time 1078244191 ps
CPU time 9.78 seconds
Started Jul 12 05:36:32 PM PDT 24
Finished Jul 12 05:36:49 PM PDT 24
Peak memory 218196 kb
Host smart-41192c8a-4737-4816-882c-130dfbdbf510
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371593912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
1371593912
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.1720421556
Short name T316
Test name
Test status
Simulation time 940148680 ps
CPU time 10.6 seconds
Started Jul 12 05:36:44 PM PDT 24
Finished Jul 12 05:36:55 PM PDT 24
Peak memory 218240 kb
Host smart-ae49f4b9-bc29-4f83-a000-a8d14cef3f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720421556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1720421556
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2927733529
Short name T61
Test name
Test status
Simulation time 127759051 ps
CPU time 3.63 seconds
Started Jul 12 05:37:04 PM PDT 24
Finished Jul 12 05:37:12 PM PDT 24
Peak memory 217664 kb
Host smart-9cd10356-7077-4719-ac7b-ab74047317b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927733529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2927733529
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.3624638028
Short name T276
Test name
Test status
Simulation time 221465240 ps
CPU time 16.52 seconds
Started Jul 12 05:36:50 PM PDT 24
Finished Jul 12 05:37:08 PM PDT 24
Peak memory 250824 kb
Host smart-95e5c0d5-3d78-4af2-8d83-eba5bbf5d3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624638028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3624638028
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2146174439
Short name T550
Test name
Test status
Simulation time 382756476 ps
CPU time 10.47 seconds
Started Jul 12 05:36:35 PM PDT 24
Finished Jul 12 05:36:49 PM PDT 24
Peak memory 250892 kb
Host smart-660993f6-aa8f-44d4-ac0d-a92edc27ef20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146174439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2146174439
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.1037652206
Short name T95
Test name
Test status
Simulation time 2817252309 ps
CPU time 63.01 seconds
Started Jul 12 05:36:44 PM PDT 24
Finished Jul 12 05:37:48 PM PDT 24
Peak memory 271404 kb
Host smart-2fa7091e-9a97-4ac3-8b94-d969498f3cee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037652206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.1037652206
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.1053965179
Short name T111
Test name
Test status
Simulation time 8146088358 ps
CPU time 282.37 seconds
Started Jul 12 05:38:31 PM PDT 24
Finished Jul 12 05:43:23 PM PDT 24
Peak memory 274508 kb
Host smart-4a954574-b7bd-495b-b8e0-3caeed034185
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1053965179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.1053965179
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.474236358
Short name T368
Test name
Test status
Simulation time 16924386 ps
CPU time 1 seconds
Started Jul 12 05:36:31 PM PDT 24
Finished Jul 12 05:36:36 PM PDT 24
Peak memory 217648 kb
Host smart-abcae1b2-83fa-4eb2-ab21-7b693b722f91
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474236358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ct
rl_volatile_unlock_smoke.474236358
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.3260053322
Short name T85
Test name
Test status
Simulation time 57487505 ps
CPU time 0.82 seconds
Started Jul 12 05:36:39 PM PDT 24
Finished Jul 12 05:36:41 PM PDT 24
Peak memory 208696 kb
Host smart-c604e4da-bf70-4868-ae91-24205468a13f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260053322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.3260053322
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.625105423
Short name T16
Test name
Test status
Simulation time 476888005 ps
CPU time 15.77 seconds
Started Jul 12 05:36:48 PM PDT 24
Finished Jul 12 05:37:05 PM PDT 24
Peak memory 218100 kb
Host smart-59d9ecde-ade7-49c2-bf97-46406e4341ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625105423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.625105423
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.990794681
Short name T804
Test name
Test status
Simulation time 43519145 ps
CPU time 2.71 seconds
Started Jul 12 05:36:35 PM PDT 24
Finished Jul 12 05:36:41 PM PDT 24
Peak memory 218120 kb
Host smart-f6ec76b4-feb9-46cd-af4f-86cabb0d70b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990794681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.990794681
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.33652500
Short name T94
Test name
Test status
Simulation time 406677416 ps
CPU time 15.81 seconds
Started Jul 12 05:37:07 PM PDT 24
Finished Jul 12 05:37:29 PM PDT 24
Peak memory 225884 kb
Host smart-e2f883a1-e90e-4aed-930a-9f0206ac2ce5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33652500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.33652500
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.4204120208
Short name T802
Test name
Test status
Simulation time 1601660410 ps
CPU time 8.65 seconds
Started Jul 12 05:36:37 PM PDT 24
Finished Jul 12 05:36:48 PM PDT 24
Peak memory 218140 kb
Host smart-2cd054c5-85c7-4409-acad-e1f7cce41d7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204120208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.4204120208
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.960359157
Short name T638
Test name
Test status
Simulation time 311670198 ps
CPU time 10.15 seconds
Started Jul 12 05:37:10 PM PDT 24
Finished Jul 12 05:37:27 PM PDT 24
Peak memory 217940 kb
Host smart-7803b6cd-4306-4e0c-b779-5d0c0f718240
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960359157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.960359157
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1070091923
Short name T665
Test name
Test status
Simulation time 500251747 ps
CPU time 8.2 seconds
Started Jul 12 05:36:44 PM PDT 24
Finished Jul 12 05:36:53 PM PDT 24
Peak memory 225892 kb
Host smart-5fb9b74e-7d5d-4d97-8425-4a6cf10d38b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070091923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1070091923
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.3800835875
Short name T784
Test name
Test status
Simulation time 101599321 ps
CPU time 1.52 seconds
Started Jul 12 05:36:50 PM PDT 24
Finished Jul 12 05:36:53 PM PDT 24
Peak memory 213844 kb
Host smart-27fb5c41-affa-4c29-953b-456733fc6387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800835875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.3800835875
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.2147717962
Short name T854
Test name
Test status
Simulation time 728052396 ps
CPU time 23.19 seconds
Started Jul 12 05:36:33 PM PDT 24
Finished Jul 12 05:37:01 PM PDT 24
Peak memory 250792 kb
Host smart-738dc7ff-55e6-4ef4-a3ea-07977a0998d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147717962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2147717962
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.4225189270
Short name T324
Test name
Test status
Simulation time 115983574 ps
CPU time 4.08 seconds
Started Jul 12 05:37:07 PM PDT 24
Finished Jul 12 05:37:18 PM PDT 24
Peak memory 223020 kb
Host smart-ae1129af-7e82-4e5a-826e-b859a13e8ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225189270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.4225189270
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1594081817
Short name T576
Test name
Test status
Simulation time 72954280009 ps
CPU time 185.97 seconds
Started Jul 12 05:36:34 PM PDT 24
Finished Jul 12 05:39:44 PM PDT 24
Peak memory 322244 kb
Host smart-9b71d9f3-f871-45a8-b2ea-8390bbcd763c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594081817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1594081817
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1781043009
Short name T305
Test name
Test status
Simulation time 27663822 ps
CPU time 1.17 seconds
Started Jul 12 05:36:33 PM PDT 24
Finished Jul 12 05:36:38 PM PDT 24
Peak memory 217704 kb
Host smart-1b7f3061-9191-427b-aff1-8b512436204e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781043009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.1781043009
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.501103212
Short name T329
Test name
Test status
Simulation time 20749585 ps
CPU time 1.18 seconds
Started Jul 12 05:35:30 PM PDT 24
Finished Jul 12 05:35:32 PM PDT 24
Peak memory 208892 kb
Host smart-86a268b1-cb28-4601-a225-38f289425236
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501103212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.501103212
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.314269628
Short name T730
Test name
Test status
Simulation time 26840436 ps
CPU time 0.8 seconds
Started Jul 12 05:35:37 PM PDT 24
Finished Jul 12 05:35:41 PM PDT 24
Peak memory 208892 kb
Host smart-4696ca13-9abf-476a-8c4f-d2e1019ce90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314269628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.314269628
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.31930575
Short name T364
Test name
Test status
Simulation time 866260966 ps
CPU time 12.91 seconds
Started Jul 12 05:35:35 PM PDT 24
Finished Jul 12 05:35:50 PM PDT 24
Peak memory 218152 kb
Host smart-eb64a979-3ce0-4dfa-92f7-c1627b268ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31930575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.31930575
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3075499243
Short name T191
Test name
Test status
Simulation time 759190715 ps
CPU time 11.43 seconds
Started Jul 12 05:35:36 PM PDT 24
Finished Jul 12 05:35:50 PM PDT 24
Peak memory 217432 kb
Host smart-72a34e17-9eed-437b-8351-4fdb805f4d91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075499243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3075499243
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.305705752
Short name T579
Test name
Test status
Simulation time 6614358520 ps
CPU time 34.03 seconds
Started Jul 12 05:35:37 PM PDT 24
Finished Jul 12 05:36:14 PM PDT 24
Peak memory 218876 kb
Host smart-e583203c-c632-44a1-b9f9-7d2f7679ee57
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305705752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_err
ors.305705752
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.329694578
Short name T701
Test name
Test status
Simulation time 229689289 ps
CPU time 6.58 seconds
Started Jul 12 05:35:33 PM PDT 24
Finished Jul 12 05:35:41 PM PDT 24
Peak memory 217568 kb
Host smart-8f36828b-5fa3-4097-afc9-48839c6c8224
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329694578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.329694578
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.3279796823
Short name T513
Test name
Test status
Simulation time 716965773 ps
CPU time 5.88 seconds
Started Jul 12 05:35:31 PM PDT 24
Finished Jul 12 05:35:38 PM PDT 24
Peak memory 218396 kb
Host smart-7c8c52cd-d470-480d-889a-75c6de5455c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279796823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.3279796823
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3590638469
Short name T418
Test name
Test status
Simulation time 767011104 ps
CPU time 11.01 seconds
Started Jul 12 05:35:30 PM PDT 24
Finished Jul 12 05:35:41 PM PDT 24
Peak memory 217748 kb
Host smart-3f9edb04-95a4-474b-a38d-161bc13a9d73
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590638469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.3590638469
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1626485009
Short name T238
Test name
Test status
Simulation time 499280233 ps
CPU time 10.09 seconds
Started Jul 12 05:35:32 PM PDT 24
Finished Jul 12 05:35:44 PM PDT 24
Peak memory 217604 kb
Host smart-8d472fc1-9a1b-4ab0-94b0-f40e6d4f3455
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626485009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1626485009
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.282036329
Short name T809
Test name
Test status
Simulation time 2187908274 ps
CPU time 46.47 seconds
Started Jul 12 05:35:34 PM PDT 24
Finished Jul 12 05:36:22 PM PDT 24
Peak memory 267992 kb
Host smart-d186fb86-b9e3-4d2b-b791-f4dbf00768e5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282036329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_state_failure.282036329
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.3740798225
Short name T266
Test name
Test status
Simulation time 2076881043 ps
CPU time 19.92 seconds
Started Jul 12 05:35:36 PM PDT 24
Finished Jul 12 05:35:57 PM PDT 24
Peak memory 250852 kb
Host smart-9da331fa-e587-44fd-94fa-652ed07fbc1c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740798225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.3740798225
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.2674372988
Short name T474
Test name
Test status
Simulation time 1053737947 ps
CPU time 3.04 seconds
Started Jul 12 05:36:23 PM PDT 24
Finished Jul 12 05:36:27 PM PDT 24
Peak memory 218140 kb
Host smart-da9acd02-1007-471b-a7ec-a62199fc152e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674372988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.2674372988
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.339198131
Short name T458
Test name
Test status
Simulation time 375525792 ps
CPU time 25.4 seconds
Started Jul 12 05:35:33 PM PDT 24
Finished Jul 12 05:36:01 PM PDT 24
Peak memory 214808 kb
Host smart-57759ce1-1706-43ef-8f59-58887f897e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339198131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.339198131
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.188734936
Short name T89
Test name
Test status
Simulation time 537849771 ps
CPU time 25.54 seconds
Started Jul 12 05:35:34 PM PDT 24
Finished Jul 12 05:36:01 PM PDT 24
Peak memory 281364 kb
Host smart-aadbd97d-b14e-4a5c-9d06-3d83b6aebf7b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188734936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.188734936
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.157811009
Short name T416
Test name
Test status
Simulation time 1135575309 ps
CPU time 13.19 seconds
Started Jul 12 05:35:33 PM PDT 24
Finished Jul 12 05:35:49 PM PDT 24
Peak memory 225968 kb
Host smart-e6c7feba-d399-44d9-8240-9f2aa58f65ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157811009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.157811009
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2616063092
Short name T612
Test name
Test status
Simulation time 1482311987 ps
CPU time 14.99 seconds
Started Jul 12 05:35:31 PM PDT 24
Finished Jul 12 05:35:47 PM PDT 24
Peak memory 225996 kb
Host smart-f1decda9-3770-4a52-8380-4df4c1021a81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616063092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2616063092
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1812520821
Short name T650
Test name
Test status
Simulation time 1455374014 ps
CPU time 12.77 seconds
Started Jul 12 05:35:32 PM PDT 24
Finished Jul 12 05:35:47 PM PDT 24
Peak memory 218184 kb
Host smart-56d9e453-beb8-4075-a73d-7754ab7d68fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812520821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
812520821
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.2422923367
Short name T466
Test name
Test status
Simulation time 654636931 ps
CPU time 8.02 seconds
Started Jul 12 05:35:36 PM PDT 24
Finished Jul 12 05:35:46 PM PDT 24
Peak memory 224744 kb
Host smart-cd9c1d5a-025b-4804-b793-d7706c611153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422923367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.2422923367
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.324909697
Short name T707
Test name
Test status
Simulation time 47683622 ps
CPU time 1.91 seconds
Started Jul 12 05:35:35 PM PDT 24
Finished Jul 12 05:35:39 PM PDT 24
Peak memory 217660 kb
Host smart-22c85400-dbeb-417d-965f-61bdb3974496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324909697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.324909697
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3000297191
Short name T515
Test name
Test status
Simulation time 669965411 ps
CPU time 33.53 seconds
Started Jul 12 05:35:32 PM PDT 24
Finished Jul 12 05:36:08 PM PDT 24
Peak memory 250900 kb
Host smart-3761b19e-e601-4ab6-8f23-9ee8cfb78125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000297191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3000297191
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1353204743
Short name T296
Test name
Test status
Simulation time 67692778 ps
CPU time 6.75 seconds
Started Jul 12 05:35:32 PM PDT 24
Finished Jul 12 05:35:40 PM PDT 24
Peak memory 242744 kb
Host smart-4e314082-d99b-4905-ac56-b67afb5a5511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353204743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1353204743
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1352913278
Short name T214
Test name
Test status
Simulation time 1777262513 ps
CPU time 66.09 seconds
Started Jul 12 05:35:31 PM PDT 24
Finished Jul 12 05:36:38 PM PDT 24
Peak memory 250908 kb
Host smart-d64182fc-bfe7-49e7-9fae-ac6eb20c4447
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352913278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1352913278
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.12097220
Short name T92
Test name
Test status
Simulation time 145648685516 ps
CPU time 631.75 seconds
Started Jul 12 05:35:33 PM PDT 24
Finished Jul 12 05:46:06 PM PDT 24
Peak memory 503900 kb
Host smart-d6271736-5634-47e7-8b44-b2c2d5387a17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=12097220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.12097220
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.3478535065
Short name T698
Test name
Test status
Simulation time 11430341 ps
CPU time 1 seconds
Started Jul 12 05:35:35 PM PDT 24
Finished Jul 12 05:35:37 PM PDT 24
Peak memory 211880 kb
Host smart-983f5716-d6e5-485a-9a4a-ca15cccbac28
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478535065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.3478535065
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1719900377
Short name T421
Test name
Test status
Simulation time 16988181 ps
CPU time 0.86 seconds
Started Jul 12 05:37:10 PM PDT 24
Finished Jul 12 05:37:18 PM PDT 24
Peak memory 208944 kb
Host smart-87682e3d-aa51-42ce-a2fe-1e705310e75b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719900377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1719900377
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.606801575
Short name T644
Test name
Test status
Simulation time 1144459215 ps
CPU time 10.51 seconds
Started Jul 12 05:36:55 PM PDT 24
Finished Jul 12 05:37:08 PM PDT 24
Peak memory 218384 kb
Host smart-c11b0d1f-4c61-41b7-9660-be1d38662e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606801575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.606801575
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.1213399942
Short name T743
Test name
Test status
Simulation time 368661776 ps
CPU time 5.13 seconds
Started Jul 12 05:36:45 PM PDT 24
Finished Jul 12 05:36:51 PM PDT 24
Peak memory 217652 kb
Host smart-56d0d32e-3ee5-435e-b0f7-3a4f8a35a709
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213399942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.1213399942
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3277645372
Short name T605
Test name
Test status
Simulation time 145330727 ps
CPU time 2.19 seconds
Started Jul 12 05:36:30 PM PDT 24
Finished Jul 12 05:36:35 PM PDT 24
Peak memory 222216 kb
Host smart-527022ae-68c5-4af1-a2f8-8b626ee4127e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277645372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3277645372
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.1034025906
Short name T816
Test name
Test status
Simulation time 1387289957 ps
CPU time 15.88 seconds
Started Jul 12 05:36:42 PM PDT 24
Finished Jul 12 05:37:04 PM PDT 24
Peak memory 225848 kb
Host smart-a9316010-eba6-47a4-93d2-32798a784eaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034025906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.1034025906
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.3173834663
Short name T451
Test name
Test status
Simulation time 211727266 ps
CPU time 9.12 seconds
Started Jul 12 05:37:07 PM PDT 24
Finished Jul 12 05:37:22 PM PDT 24
Peak memory 226196 kb
Host smart-6b0d08db-714e-4389-a3a5-e06161065a03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173834663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.3173834663
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1125987240
Short name T583
Test name
Test status
Simulation time 501054946 ps
CPU time 7.14 seconds
Started Jul 12 05:36:44 PM PDT 24
Finished Jul 12 05:36:52 PM PDT 24
Peak memory 225936 kb
Host smart-43a65d80-6511-45b4-8e29-c8b00b55e0c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125987240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1125987240
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.3793444702
Short name T459
Test name
Test status
Simulation time 556432947 ps
CPU time 11.89 seconds
Started Jul 12 05:36:31 PM PDT 24
Finished Jul 12 05:36:47 PM PDT 24
Peak memory 225956 kb
Host smart-7d2eeb6c-f637-498b-83fc-884346f7d25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793444702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3793444702
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.1440326536
Short name T749
Test name
Test status
Simulation time 487480629 ps
CPU time 2.71 seconds
Started Jul 12 05:36:40 PM PDT 24
Finished Jul 12 05:36:44 PM PDT 24
Peak memory 217652 kb
Host smart-99834602-1013-47c0-9d79-9bc056866781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440326536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.1440326536
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.4138830695
Short name T249
Test name
Test status
Simulation time 199816638 ps
CPU time 23.04 seconds
Started Jul 12 05:36:32 PM PDT 24
Finished Jul 12 05:37:00 PM PDT 24
Peak memory 250996 kb
Host smart-487cda38-e1f7-4ff1-907f-3e1f3ee67db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138830695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.4138830695
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3054444440
Short name T544
Test name
Test status
Simulation time 285194195 ps
CPU time 10.92 seconds
Started Jul 12 05:36:39 PM PDT 24
Finished Jul 12 05:36:51 PM PDT 24
Peak memory 250864 kb
Host smart-48c13395-2a42-47a0-a555-84fa906f95b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054444440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3054444440
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.1234006067
Short name T193
Test name
Test status
Simulation time 9877100870 ps
CPU time 278.71 seconds
Started Jul 12 05:36:40 PM PDT 24
Finished Jul 12 05:41:20 PM PDT 24
Peak memory 275144 kb
Host smart-d3be726a-47f6-4cb1-a307-349b13f2d24f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234006067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.1234006067
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3318770036
Short name T438
Test name
Test status
Simulation time 11569935 ps
CPU time 0.83 seconds
Started Jul 12 05:36:54 PM PDT 24
Finished Jul 12 05:36:57 PM PDT 24
Peak memory 211816 kb
Host smart-94724ab7-c465-4239-b1c3-250f33f7310b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318770036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3318770036
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.1402287329
Short name T103
Test name
Test status
Simulation time 25337814 ps
CPU time 0.94 seconds
Started Jul 12 05:37:08 PM PDT 24
Finished Jul 12 05:37:15 PM PDT 24
Peak memory 209152 kb
Host smart-8de2caf4-da2e-477a-a90b-36e6d879eafc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402287329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1402287329
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.3075925241
Short name T734
Test name
Test status
Simulation time 3211263192 ps
CPU time 13.32 seconds
Started Jul 12 05:36:29 PM PDT 24
Finished Jul 12 05:36:46 PM PDT 24
Peak memory 226044 kb
Host smart-67b570c3-57e0-47b1-8555-f90ae80c9e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075925241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3075925241
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.1704624530
Short name T815
Test name
Test status
Simulation time 38000636 ps
CPU time 1.72 seconds
Started Jul 12 05:36:45 PM PDT 24
Finished Jul 12 05:36:47 PM PDT 24
Peak memory 216940 kb
Host smart-b448e95f-f48a-4127-a8c6-8a528f5d1de6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704624530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.1704624530
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.2022385587
Short name T524
Test name
Test status
Simulation time 551778371 ps
CPU time 2.89 seconds
Started Jul 12 05:37:06 PM PDT 24
Finished Jul 12 05:37:15 PM PDT 24
Peak memory 222184 kb
Host smart-fdeb3758-fb63-4682-9977-d5bdf4c0ee8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022385587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.2022385587
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2155509918
Short name T737
Test name
Test status
Simulation time 1116602665 ps
CPU time 10.05 seconds
Started Jul 12 05:36:49 PM PDT 24
Finished Jul 12 05:37:01 PM PDT 24
Peak memory 226204 kb
Host smart-1540d22c-64c6-4a43-86af-023c8cac13a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155509918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2155509918
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2178908615
Short name T555
Test name
Test status
Simulation time 1870698072 ps
CPU time 11.58 seconds
Started Jul 12 05:36:44 PM PDT 24
Finished Jul 12 05:36:57 PM PDT 24
Peak memory 225976 kb
Host smart-5917585e-9d56-4a27-91e5-b28464c9fb83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178908615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.2178908615
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3074957858
Short name T379
Test name
Test status
Simulation time 653749237 ps
CPU time 9.09 seconds
Started Jul 12 05:36:57 PM PDT 24
Finished Jul 12 05:37:10 PM PDT 24
Peak memory 225976 kb
Host smart-3a2bc2d1-68aa-4f9d-a509-13ae192f53db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074957858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
3074957858
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.3929941636
Short name T541
Test name
Test status
Simulation time 924198015 ps
CPU time 7.11 seconds
Started Jul 12 05:36:39 PM PDT 24
Finished Jul 12 05:36:47 PM PDT 24
Peak memory 224792 kb
Host smart-67e225ca-b653-4e07-b67d-9e7a5aa9610a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929941636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3929941636
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.691347994
Short name T407
Test name
Test status
Simulation time 73137746 ps
CPU time 3.38 seconds
Started Jul 12 05:36:39 PM PDT 24
Finished Jul 12 05:36:49 PM PDT 24
Peak memory 217656 kb
Host smart-f20f6cf7-d688-4aae-8824-561fb4c77e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691347994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.691347994
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1304561756
Short name T339
Test name
Test status
Simulation time 2082685790 ps
CPU time 28.01 seconds
Started Jul 12 05:37:05 PM PDT 24
Finished Jul 12 05:37:38 PM PDT 24
Peak memory 246492 kb
Host smart-3142b309-2994-46f8-8463-a1d99542e25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304561756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1304561756
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.2058560235
Short name T424
Test name
Test status
Simulation time 69404253 ps
CPU time 6.65 seconds
Started Jul 12 05:37:05 PM PDT 24
Finished Jul 12 05:37:17 PM PDT 24
Peak memory 246952 kb
Host smart-3b3fe53b-2dc4-445a-8c09-517802426068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058560235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.2058560235
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.2214204583
Short name T862
Test name
Test status
Simulation time 53546975551 ps
CPU time 181.34 seconds
Started Jul 12 05:37:01 PM PDT 24
Finished Jul 12 05:40:06 PM PDT 24
Peak memory 283884 kb
Host smart-f9d3fa74-3f64-4343-8993-7adf2c2e3b88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214204583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.2214204583
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2409929552
Short name T618
Test name
Test status
Simulation time 25452999 ps
CPU time 0.84 seconds
Started Jul 12 05:36:31 PM PDT 24
Finished Jul 12 05:36:35 PM PDT 24
Peak memory 211780 kb
Host smart-6fe3dd11-3dad-45fa-a394-1e12e722f499
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409929552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2409929552
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.385380573
Short name T617
Test name
Test status
Simulation time 52094005 ps
CPU time 1.02 seconds
Started Jul 12 05:37:06 PM PDT 24
Finished Jul 12 05:37:13 PM PDT 24
Peak memory 208768 kb
Host smart-95bfe119-0834-4a30-b378-4797ae820a26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385380573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.385380573
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.3918519718
Short name T856
Test name
Test status
Simulation time 1253539913 ps
CPU time 14.57 seconds
Started Jul 12 05:37:06 PM PDT 24
Finished Jul 12 05:37:27 PM PDT 24
Peak memory 218048 kb
Host smart-dab4e672-c1fe-412a-9773-cf45569ddb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918519718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.3918519718
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2844520591
Short name T542
Test name
Test status
Simulation time 102215987 ps
CPU time 1.5 seconds
Started Jul 12 05:37:05 PM PDT 24
Finished Jul 12 05:37:11 PM PDT 24
Peak memory 217112 kb
Host smart-61a8dcab-ad62-4244-bd8a-1e09140cb3b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844520591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.2844520591
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.630347169
Short name T782
Test name
Test status
Simulation time 87477722 ps
CPU time 2.75 seconds
Started Jul 12 05:36:59 PM PDT 24
Finished Jul 12 05:37:06 PM PDT 24
Peak memory 218140 kb
Host smart-0623aacb-eb1c-4283-bdb5-7e175fa903b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630347169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.630347169
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.1736769618
Short name T670
Test name
Test status
Simulation time 3803254733 ps
CPU time 15.11 seconds
Started Jul 12 05:36:59 PM PDT 24
Finished Jul 12 05:37:18 PM PDT 24
Peak memory 226044 kb
Host smart-b2054a4f-ad20-418d-8fe9-6dfcf51a5502
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736769618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.1736769618
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.157402938
Short name T726
Test name
Test status
Simulation time 322180369 ps
CPU time 9.07 seconds
Started Jul 12 05:36:56 PM PDT 24
Finished Jul 12 05:37:09 PM PDT 24
Peak memory 225980 kb
Host smart-dc93790d-ffb5-47cf-bb74-ae05ea6f0512
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157402938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_di
gest.157402938
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.3409841621
Short name T399
Test name
Test status
Simulation time 257597443 ps
CPU time 10.56 seconds
Started Jul 12 05:36:49 PM PDT 24
Finished Jul 12 05:37:01 PM PDT 24
Peak memory 218152 kb
Host smart-5af8034b-94ba-4f16-bd4d-c8a73b0d9fd5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409841621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
3409841621
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.2141041778
Short name T179
Test name
Test status
Simulation time 758576468 ps
CPU time 7.19 seconds
Started Jul 12 05:36:53 PM PDT 24
Finished Jul 12 05:37:03 PM PDT 24
Peak memory 218176 kb
Host smart-b5f1aa58-6ed1-4bbd-a6c7-93381f1b1eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141041778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.2141041778
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.1978554146
Short name T630
Test name
Test status
Simulation time 43704214 ps
CPU time 2.57 seconds
Started Jul 12 05:36:58 PM PDT 24
Finished Jul 12 05:37:05 PM PDT 24
Peak memory 217888 kb
Host smart-45dc7dd4-eee8-4ba5-b6f3-80c579aa70b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978554146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.1978554146
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.1859997322
Short name T766
Test name
Test status
Simulation time 991036610 ps
CPU time 17.69 seconds
Started Jul 12 05:36:32 PM PDT 24
Finished Jul 12 05:36:54 PM PDT 24
Peak memory 250836 kb
Host smart-57dd6177-3591-4c5b-86c5-1335c03b0488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859997322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1859997322
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.3456007007
Short name T517
Test name
Test status
Simulation time 204801138 ps
CPU time 5.95 seconds
Started Jul 12 05:36:50 PM PDT 24
Finished Jul 12 05:36:57 PM PDT 24
Peak memory 246580 kb
Host smart-b0bf5ef7-83db-4373-a5c9-cc07f797ef26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456007007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3456007007
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.4201540677
Short name T778
Test name
Test status
Simulation time 30686275618 ps
CPU time 228.45 seconds
Started Jul 12 05:36:32 PM PDT 24
Finished Jul 12 05:40:24 PM PDT 24
Peak memory 259160 kb
Host smart-d8209ed4-859b-42b1-8a9f-3733a4040375
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201540677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.4201540677
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.555912857
Short name T150
Test name
Test status
Simulation time 24656645223 ps
CPU time 649.49 seconds
Started Jul 12 05:36:50 PM PDT 24
Finished Jul 12 05:47:41 PM PDT 24
Peak memory 273288 kb
Host smart-696d5dc4-adfe-4966-915c-3b52dc0cded3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=555912857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.555912857
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.730483933
Short name T353
Test name
Test status
Simulation time 41848537 ps
CPU time 0.95 seconds
Started Jul 12 05:36:48 PM PDT 24
Finished Jul 12 05:36:50 PM PDT 24
Peak memory 212896 kb
Host smart-7c37c7d2-e227-411c-a471-fcd4e40c9400
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730483933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ct
rl_volatile_unlock_smoke.730483933
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1503914816
Short name T580
Test name
Test status
Simulation time 56740282 ps
CPU time 1.1 seconds
Started Jul 12 05:36:56 PM PDT 24
Finished Jul 12 05:37:01 PM PDT 24
Peak memory 208908 kb
Host smart-13511a8b-ff73-453a-baae-9479aeb3f5c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503914816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1503914816
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.383124805
Short name T492
Test name
Test status
Simulation time 1177808792 ps
CPU time 12.19 seconds
Started Jul 12 05:36:35 PM PDT 24
Finished Jul 12 05:36:51 PM PDT 24
Peak memory 225944 kb
Host smart-2d093781-6c5b-4dc7-8449-1a6b05566121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383124805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.383124805
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.4177469445
Short name T536
Test name
Test status
Simulation time 527484385 ps
CPU time 9.77 seconds
Started Jul 12 05:36:46 PM PDT 24
Finished Jul 12 05:36:57 PM PDT 24
Peak memory 217156 kb
Host smart-87e635c3-d1dc-4995-8f10-f750bd876283
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177469445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.4177469445
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1555885376
Short name T432
Test name
Test status
Simulation time 168657293 ps
CPU time 2.11 seconds
Started Jul 12 05:37:06 PM PDT 24
Finished Jul 12 05:37:14 PM PDT 24
Peak memory 218136 kb
Host smart-3858b862-a9a0-4cad-8864-d6aa6d16d7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555885376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1555885376
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.742960911
Short name T226
Test name
Test status
Simulation time 1550557726 ps
CPU time 13.91 seconds
Started Jul 12 05:36:55 PM PDT 24
Finished Jul 12 05:37:12 PM PDT 24
Peak memory 225964 kb
Host smart-c3606ec6-07d3-4aab-94d1-3a21ad74c877
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742960911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.742960911
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.732138964
Short name T233
Test name
Test status
Simulation time 4247764563 ps
CPU time 9.72 seconds
Started Jul 12 05:37:08 PM PDT 24
Finished Jul 12 05:37:24 PM PDT 24
Peak memory 226256 kb
Host smart-49ee3d70-02b8-48c4-a9ce-439ea04ab74b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732138964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_di
gest.732138964
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.1687812941
Short name T756
Test name
Test status
Simulation time 2004343973 ps
CPU time 7.97 seconds
Started Jul 12 05:36:56 PM PDT 24
Finished Jul 12 05:37:07 PM PDT 24
Peak memory 225956 kb
Host smart-b207cf33-8073-4dea-9e8f-604dddcdd83a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687812941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
1687812941
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.586922073
Short name T503
Test name
Test status
Simulation time 267546885 ps
CPU time 7.19 seconds
Started Jul 12 05:36:50 PM PDT 24
Finished Jul 12 05:36:59 PM PDT 24
Peak memory 225068 kb
Host smart-69bd2055-4439-4360-9242-fba55a182542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586922073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.586922073
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.3772189504
Short name T260
Test name
Test status
Simulation time 53357177 ps
CPU time 2.88 seconds
Started Jul 12 05:37:14 PM PDT 24
Finished Jul 12 05:37:22 PM PDT 24
Peak memory 217636 kb
Host smart-77e948c2-743b-4ec5-80a4-6a70f4f01ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772189504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3772189504
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1442521640
Short name T285
Test name
Test status
Simulation time 82648568 ps
CPU time 7.08 seconds
Started Jul 12 05:37:06 PM PDT 24
Finished Jul 12 05:37:19 PM PDT 24
Peak memory 247168 kb
Host smart-e3d0179b-8bd0-471d-8d20-dffacf9526ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442521640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1442521640
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.3028963092
Short name T262
Test name
Test status
Simulation time 2793350893 ps
CPU time 106.49 seconds
Started Jul 12 05:36:57 PM PDT 24
Finished Jul 12 05:38:48 PM PDT 24
Peak memory 421204 kb
Host smart-5b5dc66e-3529-4633-b9ff-702ad75f0cf2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028963092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.3028963092
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.870294489
Short name T174
Test name
Test status
Simulation time 761731009940 ps
CPU time 1026.71 seconds
Started Jul 12 05:36:59 PM PDT 24
Finished Jul 12 05:54:10 PM PDT 24
Peak memory 562380 kb
Host smart-b02e1316-72e3-47e9-a4f0-9fca3345ac8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=870294489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.870294489
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.1538090800
Short name T410
Test name
Test status
Simulation time 26084758 ps
CPU time 0.86 seconds
Started Jul 12 05:36:57 PM PDT 24
Finished Jul 12 05:37:01 PM PDT 24
Peak memory 211764 kb
Host smart-67fd10b3-838d-4b19-9280-5ec990eaf3da
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538090800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.1538090800
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2040535163
Short name T27
Test name
Test status
Simulation time 18146582 ps
CPU time 0.91 seconds
Started Jul 12 05:36:42 PM PDT 24
Finished Jul 12 05:36:44 PM PDT 24
Peak memory 208924 kb
Host smart-af7998a3-4e74-429e-8c66-ba3f68ce5f16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040535163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2040535163
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.3324188583
Short name T231
Test name
Test status
Simulation time 389424854 ps
CPU time 17.78 seconds
Started Jul 12 05:36:47 PM PDT 24
Finished Jul 12 05:37:06 PM PDT 24
Peak memory 226000 kb
Host smart-a8d4dd4a-0218-4476-96a2-4fefd385865d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324188583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.3324188583
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.1132430970
Short name T639
Test name
Test status
Simulation time 538515654 ps
CPU time 13.54 seconds
Started Jul 12 05:37:01 PM PDT 24
Finished Jul 12 05:37:18 PM PDT 24
Peak memory 217424 kb
Host smart-4689d6e5-c9c5-49bf-970e-4b24be8e9c24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132430970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.1132430970
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.2168392669
Short name T588
Test name
Test status
Simulation time 207779949 ps
CPU time 1.89 seconds
Started Jul 12 05:36:46 PM PDT 24
Finished Jul 12 05:36:49 PM PDT 24
Peak memory 218164 kb
Host smart-8ea76397-af4d-435c-911e-bb4c326cc0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168392669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2168392669
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.566631251
Short name T745
Test name
Test status
Simulation time 1470316697 ps
CPU time 21.62 seconds
Started Jul 12 05:37:03 PM PDT 24
Finished Jul 12 05:37:29 PM PDT 24
Peak memory 225960 kb
Host smart-6d55a718-a70f-4935-a6d0-68698e57f6b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566631251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.566631251
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.910106044
Short name T591
Test name
Test status
Simulation time 326313341 ps
CPU time 13.75 seconds
Started Jul 12 05:36:57 PM PDT 24
Finished Jul 12 05:37:20 PM PDT 24
Peak memory 225920 kb
Host smart-cf1b8be1-5325-44f3-9353-7c921aa7453d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910106044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.910106044
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3195393286
Short name T498
Test name
Test status
Simulation time 729660487 ps
CPU time 7.85 seconds
Started Jul 12 05:36:57 PM PDT 24
Finished Jul 12 05:37:10 PM PDT 24
Peak memory 218064 kb
Host smart-19c674b6-e96d-4094-a044-a6d3a98eb1f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195393286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3195393286
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.357973058
Short name T177
Test name
Test status
Simulation time 1563337608 ps
CPU time 14.35 seconds
Started Jul 12 05:37:06 PM PDT 24
Finished Jul 12 05:37:26 PM PDT 24
Peak memory 225964 kb
Host smart-5c6b5328-e5c2-43f4-9df6-20dab8b01801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357973058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.357973058
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.3180608976
Short name T67
Test name
Test status
Simulation time 164419733 ps
CPU time 2.32 seconds
Started Jul 12 05:37:09 PM PDT 24
Finished Jul 12 05:37:18 PM PDT 24
Peak memory 217596 kb
Host smart-52e0581c-79ed-4199-aaa3-7f3cf850243f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180608976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3180608976
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.721409187
Short name T395
Test name
Test status
Simulation time 533435867 ps
CPU time 20.9 seconds
Started Jul 12 05:36:32 PM PDT 24
Finished Jul 12 05:36:57 PM PDT 24
Peak memory 250924 kb
Host smart-314274df-18b6-4620-a3ff-ab8d44a5b657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721409187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.721409187
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.1994681495
Short name T36
Test name
Test status
Simulation time 314659285 ps
CPU time 9.72 seconds
Started Jul 12 05:36:47 PM PDT 24
Finished Jul 12 05:36:58 PM PDT 24
Peak memory 250860 kb
Host smart-82ad6a7a-c016-49ff-8c08-16c5771866d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994681495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1994681495
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.1921161438
Short name T785
Test name
Test status
Simulation time 5968447701 ps
CPU time 105.07 seconds
Started Jul 12 05:37:01 PM PDT 24
Finished Jul 12 05:38:50 PM PDT 24
Peak memory 252192 kb
Host smart-68a2fef3-3490-441f-b3fb-8427f7de2583
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921161438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.1921161438
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1750846689
Short name T417
Test name
Test status
Simulation time 31518581 ps
CPU time 0.88 seconds
Started Jul 12 05:36:50 PM PDT 24
Finished Jul 12 05:36:52 PM PDT 24
Peak memory 211812 kb
Host smart-02ffb4cc-caa3-4e06-b732-8884c67b1a82
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750846689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1750846689
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.4103934293
Short name T759
Test name
Test status
Simulation time 46951618 ps
CPU time 0.96 seconds
Started Jul 12 05:36:59 PM PDT 24
Finished Jul 12 05:37:04 PM PDT 24
Peak memory 208744 kb
Host smart-8cb5d5be-a54e-42f4-8b1b-d8a0332e5446
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103934293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.4103934293
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.720098484
Short name T600
Test name
Test status
Simulation time 589165738 ps
CPU time 9.48 seconds
Started Jul 12 05:36:39 PM PDT 24
Finished Jul 12 05:36:50 PM PDT 24
Peak memory 225844 kb
Host smart-44ac2229-71c7-4fae-b09a-5a1f7475029c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720098484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.720098484
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2974216844
Short name T599
Test name
Test status
Simulation time 990497918 ps
CPU time 3.82 seconds
Started Jul 12 05:36:44 PM PDT 24
Finished Jul 12 05:36:49 PM PDT 24
Peak memory 217132 kb
Host smart-17d2b32d-d8ec-4dbd-8004-88a03b8d49b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974216844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2974216844
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.834571055
Short name T59
Test name
Test status
Simulation time 321421721 ps
CPU time 3.5 seconds
Started Jul 12 05:36:45 PM PDT 24
Finished Jul 12 05:36:50 PM PDT 24
Peak memory 218128 kb
Host smart-fcfe7138-1b85-428c-be76-537872d7c849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834571055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.834571055
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.829389442
Short name T43
Test name
Test status
Simulation time 1347331369 ps
CPU time 13.04 seconds
Started Jul 12 05:37:09 PM PDT 24
Finished Jul 12 05:37:29 PM PDT 24
Peak memory 218660 kb
Host smart-4b00c56a-e559-4e82-9018-2c03f3ea7960
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829389442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.829389442
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.266888485
Short name T413
Test name
Test status
Simulation time 272650083 ps
CPU time 10.6 seconds
Started Jul 12 05:36:55 PM PDT 24
Finished Jul 12 05:37:09 PM PDT 24
Peak memory 225996 kb
Host smart-81f03314-1c4e-423c-872a-cc0da43d4694
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266888485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_di
gest.266888485
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.276671007
Short name T344
Test name
Test status
Simulation time 4644741743 ps
CPU time 14.51 seconds
Started Jul 12 05:36:53 PM PDT 24
Finished Jul 12 05:37:11 PM PDT 24
Peak memory 225928 kb
Host smart-88a70b48-58e7-449f-bc40-01eee2a61799
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276671007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.276671007
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.4156021849
Short name T483
Test name
Test status
Simulation time 2204703140 ps
CPU time 12.46 seconds
Started Jul 12 05:36:52 PM PDT 24
Finished Jul 12 05:37:06 PM PDT 24
Peak memory 225908 kb
Host smart-871f05dc-aed5-427b-af84-98fdf0c9f2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156021849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.4156021849
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3117930353
Short name T439
Test name
Test status
Simulation time 107507946 ps
CPU time 1.61 seconds
Started Jul 12 05:36:45 PM PDT 24
Finished Jul 12 05:36:47 PM PDT 24
Peak memory 213872 kb
Host smart-0769d3f5-a87e-40aa-8092-29878fdd8bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117930353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3117930353
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.4081781109
Short name T558
Test name
Test status
Simulation time 847815080 ps
CPU time 26.39 seconds
Started Jul 12 05:36:54 PM PDT 24
Finished Jul 12 05:37:24 PM PDT 24
Peak memory 250908 kb
Host smart-703b1645-e32c-497e-96cd-e4ac7b878068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081781109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.4081781109
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.18921364
Short name T559
Test name
Test status
Simulation time 92475910 ps
CPU time 9.51 seconds
Started Jul 12 05:36:54 PM PDT 24
Finished Jul 12 05:37:13 PM PDT 24
Peak memory 250924 kb
Host smart-81a9d6f8-9f55-44c6-93d6-d6f1a858344c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18921364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.18921364
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.1933120027
Short name T346
Test name
Test status
Simulation time 1698255577 ps
CPU time 54.61 seconds
Started Jul 12 05:36:45 PM PDT 24
Finished Jul 12 05:37:40 PM PDT 24
Peak memory 269276 kb
Host smart-bece992e-b304-4282-a609-7a93ded955a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933120027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.1933120027
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3811968500
Short name T821
Test name
Test status
Simulation time 44178645 ps
CPU time 0.89 seconds
Started Jul 12 05:36:49 PM PDT 24
Finished Jul 12 05:36:51 PM PDT 24
Peak memory 211844 kb
Host smart-31de483c-8971-473e-85c1-a5a9a719cdd5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811968500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.3811968500
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.2777554611
Short name T252
Test name
Test status
Simulation time 44154729 ps
CPU time 0.99 seconds
Started Jul 12 05:37:05 PM PDT 24
Finished Jul 12 05:37:11 PM PDT 24
Peak memory 208972 kb
Host smart-be4f5801-8518-4813-9c19-595dd625c9e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777554611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.2777554611
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.1486035040
Short name T620
Test name
Test status
Simulation time 1118042859 ps
CPU time 9.41 seconds
Started Jul 12 05:36:53 PM PDT 24
Finished Jul 12 05:37:05 PM PDT 24
Peak memory 217984 kb
Host smart-1f5a4eb6-c698-46cf-9302-5c6951071737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486035040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.1486035040
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3501170874
Short name T414
Test name
Test status
Simulation time 517092010 ps
CPU time 3.76 seconds
Started Jul 12 05:37:48 PM PDT 24
Finished Jul 12 05:38:05 PM PDT 24
Peak memory 216560 kb
Host smart-6906aacb-33ca-4d99-b710-352ae5dd1938
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501170874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.3501170874
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.2702951408
Short name T793
Test name
Test status
Simulation time 55087638 ps
CPU time 2.08 seconds
Started Jul 12 05:36:54 PM PDT 24
Finished Jul 12 05:36:59 PM PDT 24
Peak memory 222004 kb
Host smart-6e0d457d-f6b7-4f62-9dbe-9c2fe36a590a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702951408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2702951408
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.2108862600
Short name T383
Test name
Test status
Simulation time 336249846 ps
CPU time 14.84 seconds
Started Jul 12 05:36:53 PM PDT 24
Finished Jul 12 05:37:10 PM PDT 24
Peak memory 225940 kb
Host smart-3c391cfe-d821-4b2e-81db-a3c235e4eeb1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108862600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.2108862600
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.589690020
Short name T460
Test name
Test status
Simulation time 367520456 ps
CPU time 9.69 seconds
Started Jul 12 05:36:40 PM PDT 24
Finished Jul 12 05:36:51 PM PDT 24
Peak memory 225968 kb
Host smart-358f6c63-eebc-4f8b-ba94-7e32bacdbc94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589690020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.589690020
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.1986947422
Short name T455
Test name
Test status
Simulation time 1310907282 ps
CPU time 10.82 seconds
Started Jul 12 05:38:01 PM PDT 24
Finished Jul 12 05:38:34 PM PDT 24
Peak memory 217828 kb
Host smart-2f6c193f-409c-476a-8e08-169ce720ea5c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986947422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
1986947422
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2824653934
Short name T263
Test name
Test status
Simulation time 39160827 ps
CPU time 2.46 seconds
Started Jul 12 05:37:01 PM PDT 24
Finished Jul 12 05:37:07 PM PDT 24
Peak memory 217696 kb
Host smart-88eccf54-d3de-4d48-bb56-6ef9f4878683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824653934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2824653934
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3200589743
Short name T777
Test name
Test status
Simulation time 397389259 ps
CPU time 24.14 seconds
Started Jul 12 05:36:59 PM PDT 24
Finished Jul 12 05:37:27 PM PDT 24
Peak memory 250912 kb
Host smart-782c75f8-1d52-467c-b2cf-4cb99d38bb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200589743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3200589743
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.1622353919
Short name T867
Test name
Test status
Simulation time 120301940 ps
CPU time 6.4 seconds
Started Jul 12 05:36:49 PM PDT 24
Finished Jul 12 05:36:56 PM PDT 24
Peak memory 250380 kb
Host smart-64588feb-4aa2-437d-b2b5-916663938396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622353919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.1622353919
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.1648563067
Short name T300
Test name
Test status
Simulation time 21348505152 ps
CPU time 137.44 seconds
Started Jul 12 05:38:01 PM PDT 24
Finished Jul 12 05:40:41 PM PDT 24
Peak memory 421608 kb
Host smart-f76ee86d-231e-49a0-a82e-a51a853ddf5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648563067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.1648563067
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2424449463
Short name T664
Test name
Test status
Simulation time 11788426 ps
CPU time 1.08 seconds
Started Jul 12 05:36:44 PM PDT 24
Finished Jul 12 05:36:46 PM PDT 24
Peak memory 211928 kb
Host smart-1d134a89-7412-4217-a261-b5c0bafc04ed
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424449463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.2424449463
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.470675317
Short name T740
Test name
Test status
Simulation time 111027171 ps
CPU time 1.01 seconds
Started Jul 12 05:37:09 PM PDT 24
Finished Jul 12 05:37:16 PM PDT 24
Peak memory 208780 kb
Host smart-3dd24153-1afd-4091-bb58-1f6a5fb769c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470675317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.470675317
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1526939676
Short name T633
Test name
Test status
Simulation time 837132866 ps
CPU time 9.67 seconds
Started Jul 12 05:37:08 PM PDT 24
Finished Jul 12 05:37:24 PM PDT 24
Peak memory 218104 kb
Host smart-4dfa0afb-ae92-4c27-ae16-08f7a4f71cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526939676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1526939676
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.3735130536
Short name T412
Test name
Test status
Simulation time 690134416 ps
CPU time 1.9 seconds
Started Jul 12 05:37:46 PM PDT 24
Finished Jul 12 05:38:00 PM PDT 24
Peak memory 215328 kb
Host smart-24458cd0-c5f2-462c-b306-7efbf6aee0d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735130536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.3735130536
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3855531346
Short name T716
Test name
Test status
Simulation time 291254800 ps
CPU time 2.47 seconds
Started Jul 12 05:37:01 PM PDT 24
Finished Jul 12 05:37:08 PM PDT 24
Peak memory 218164 kb
Host smart-fbad14ec-c366-462d-90bd-b1f0d5dbc02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855531346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3855531346
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.3908132326
Short name T171
Test name
Test status
Simulation time 1049134730 ps
CPU time 9.27 seconds
Started Jul 12 05:36:52 PM PDT 24
Finished Jul 12 05:37:03 PM PDT 24
Peak memory 225996 kb
Host smart-64215bea-31c1-47fa-bca2-589d67f0c916
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908132326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.3908132326
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2137553281
Short name T799
Test name
Test status
Simulation time 366063409 ps
CPU time 8.31 seconds
Started Jul 12 05:36:55 PM PDT 24
Finished Jul 12 05:37:06 PM PDT 24
Peak memory 218184 kb
Host smart-ae58db86-1f54-42c7-b869-186a4c5f9c49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137553281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2137553281
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.2913088388
Short name T294
Test name
Test status
Simulation time 1028487704 ps
CPU time 9.93 seconds
Started Jul 12 05:36:43 PM PDT 24
Finished Jul 12 05:36:53 PM PDT 24
Peak memory 225468 kb
Host smart-fbc16361-78c7-46d3-9c54-0039634c9bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913088388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.2913088388
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.4294478054
Short name T38
Test name
Test status
Simulation time 110235191 ps
CPU time 2.48 seconds
Started Jul 12 05:37:48 PM PDT 24
Finished Jul 12 05:38:04 PM PDT 24
Peak memory 213976 kb
Host smart-64f475fb-ae37-46c7-a176-72f02eecdae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294478054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.4294478054
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.226909735
Short name T473
Test name
Test status
Simulation time 1113766684 ps
CPU time 28.36 seconds
Started Jul 12 05:36:58 PM PDT 24
Finished Jul 12 05:37:31 PM PDT 24
Peak memory 250916 kb
Host smart-41860061-2ab9-4bc1-a471-f9d923d9d6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226909735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.226909735
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1975135585
Short name T277
Test name
Test status
Simulation time 342762310 ps
CPU time 6.23 seconds
Started Jul 12 05:37:46 PM PDT 24
Finished Jul 12 05:38:04 PM PDT 24
Peak memory 245704 kb
Host smart-210ed3be-92ea-4429-98b8-fc91bf3d43ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975135585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1975135585
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2355827087
Short name T663
Test name
Test status
Simulation time 1721960794 ps
CPU time 61.51 seconds
Started Jul 12 05:37:13 PM PDT 24
Finished Jul 12 05:38:20 PM PDT 24
Peak memory 247452 kb
Host smart-0a092e94-1326-4c19-9709-b914beb25b94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355827087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2355827087
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.1717117322
Short name T93
Test name
Test status
Simulation time 210571072913 ps
CPU time 1426.08 seconds
Started Jul 12 05:36:52 PM PDT 24
Finished Jul 12 06:00:41 PM PDT 24
Peak memory 496752 kb
Host smart-835a3819-3c02-438c-a807-fca3c682025f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1717117322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.1717117322
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3658733805
Short name T83
Test name
Test status
Simulation time 14669166 ps
CPU time 0.93 seconds
Started Jul 12 05:37:47 PM PDT 24
Finished Jul 12 05:38:01 PM PDT 24
Peak memory 211368 kb
Host smart-d938025e-92e6-4997-9e0c-bfa42cda92a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658733805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3658733805
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.991854069
Short name T235
Test name
Test status
Simulation time 670895489 ps
CPU time 16.47 seconds
Started Jul 12 05:36:56 PM PDT 24
Finished Jul 12 05:37:15 PM PDT 24
Peak memory 218004 kb
Host smart-931e6261-1e90-4c3b-9990-694fe7bd7752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991854069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.991854069
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.3688452682
Short name T194
Test name
Test status
Simulation time 444303409 ps
CPU time 5.27 seconds
Started Jul 12 05:37:01 PM PDT 24
Finished Jul 12 05:37:11 PM PDT 24
Peak memory 217168 kb
Host smart-d3945475-a82f-4110-af22-4a6731c5dc2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688452682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.3688452682
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3232935995
Short name T309
Test name
Test status
Simulation time 57947739 ps
CPU time 2.09 seconds
Started Jul 12 05:36:48 PM PDT 24
Finished Jul 12 05:36:52 PM PDT 24
Peak memory 218156 kb
Host smart-0f8af90e-0d34-4444-a7c6-5433fb8cdef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232935995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3232935995
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1423774832
Short name T393
Test name
Test status
Simulation time 368611090 ps
CPU time 9.11 seconds
Started Jul 12 05:36:57 PM PDT 24
Finished Jul 12 05:37:11 PM PDT 24
Peak memory 225924 kb
Host smart-59aa5bf7-0bcf-48cd-b6a3-494cf1857b50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423774832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.1423774832
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.2059632798
Short name T731
Test name
Test status
Simulation time 374269514 ps
CPU time 7.86 seconds
Started Jul 12 05:36:58 PM PDT 24
Finished Jul 12 05:37:11 PM PDT 24
Peak memory 224776 kb
Host smart-9393896a-07ed-4f9a-8a2c-93f77d252663
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059632798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
2059632798
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.133768180
Short name T371
Test name
Test status
Simulation time 618384220 ps
CPU time 11.8 seconds
Started Jul 12 05:37:09 PM PDT 24
Finished Jul 12 05:37:27 PM PDT 24
Peak memory 225916 kb
Host smart-55fb5a7d-9d8d-4e8e-b214-ee93eabba3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133768180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.133768180
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.661559393
Short name T629
Test name
Test status
Simulation time 17688390 ps
CPU time 1.4 seconds
Started Jul 12 05:37:12 PM PDT 24
Finished Jul 12 05:37:19 PM PDT 24
Peak memory 213460 kb
Host smart-a34b21e1-0303-4df0-94bf-80c550dad077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661559393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.661559393
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3411434645
Short name T97
Test name
Test status
Simulation time 1946824349 ps
CPU time 16.73 seconds
Started Jul 12 05:36:55 PM PDT 24
Finished Jul 12 05:37:15 PM PDT 24
Peak memory 250928 kb
Host smart-2ee8bcad-dd2f-4e54-842a-5437aa6aca2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411434645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3411434645
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3786937525
Short name T561
Test name
Test status
Simulation time 92418864 ps
CPU time 7.76 seconds
Started Jul 12 05:36:51 PM PDT 24
Finished Jul 12 05:37:00 PM PDT 24
Peak memory 250804 kb
Host smart-204b8681-e64f-4afe-a549-4f28d0a7154b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786937525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3786937525
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.2101498180
Short name T106
Test name
Test status
Simulation time 135199192127 ps
CPU time 1123.62 seconds
Started Jul 12 05:36:49 PM PDT 24
Finished Jul 12 05:55:34 PM PDT 24
Peak memory 356432 kb
Host smart-8a205e17-70f4-47e3-ba14-0a6773041b15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2101498180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.2101498180
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.593711895
Short name T750
Test name
Test status
Simulation time 26492826 ps
CPU time 0.92 seconds
Started Jul 12 05:36:59 PM PDT 24
Finished Jul 12 05:37:04 PM PDT 24
Peak memory 211668 kb
Host smart-e3bf65dd-8d43-4c4f-9500-e4d453aaccb1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593711895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.593711895
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1831442961
Short name T66
Test name
Test status
Simulation time 152652235 ps
CPU time 0.93 seconds
Started Jul 12 05:37:10 PM PDT 24
Finished Jul 12 05:37:18 PM PDT 24
Peak memory 208924 kb
Host smart-ce7aef23-967b-4444-9a65-6d203c1ee480
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831442961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1831442961
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.1109563631
Short name T575
Test name
Test status
Simulation time 864224989 ps
CPU time 21.55 seconds
Started Jul 12 05:43:53 PM PDT 24
Finished Jul 12 05:44:16 PM PDT 24
Peak memory 218140 kb
Host smart-0a2b65d9-7ae7-4cf0-a2df-c55bf0290c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109563631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1109563631
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.104897163
Short name T30
Test name
Test status
Simulation time 387142207 ps
CPU time 1.84 seconds
Started Jul 12 05:36:49 PM PDT 24
Finished Jul 12 05:36:52 PM PDT 24
Peak memory 217084 kb
Host smart-6975e5a5-fa7d-4025-846b-5408d1af1764
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104897163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.104897163
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.3170509686
Short name T433
Test name
Test status
Simulation time 253466334 ps
CPU time 3.55 seconds
Started Jul 12 05:37:08 PM PDT 24
Finished Jul 12 05:37:18 PM PDT 24
Peak memory 218152 kb
Host smart-a4766452-1998-4b11-912f-d6e0c1fd60a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170509686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.3170509686
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3666692958
Short name T499
Test name
Test status
Simulation time 288985362 ps
CPU time 12.17 seconds
Started Jul 12 05:36:52 PM PDT 24
Finished Jul 12 05:37:06 PM PDT 24
Peak memory 225872 kb
Host smart-1d3d30c0-15c6-4124-9c10-4fa16e6aa5fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666692958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3666692958
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.1103142307
Short name T751
Test name
Test status
Simulation time 1524998322 ps
CPU time 10.7 seconds
Started Jul 12 05:37:08 PM PDT 24
Finished Jul 12 05:37:25 PM PDT 24
Peak memory 225900 kb
Host smart-46927bfe-6327-468b-9f8a-dff2a613de44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103142307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.1103142307
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.121434200
Short name T615
Test name
Test status
Simulation time 1110591134 ps
CPU time 9.1 seconds
Started Jul 12 05:36:57 PM PDT 24
Finished Jul 12 05:37:11 PM PDT 24
Peak memory 218064 kb
Host smart-619c9e09-a3b4-4fac-9bde-8a9f52574bdb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121434200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.121434200
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.2349279795
Short name T246
Test name
Test status
Simulation time 296847524 ps
CPU time 9.56 seconds
Started Jul 12 05:36:48 PM PDT 24
Finished Jul 12 05:36:59 PM PDT 24
Peak memory 218252 kb
Host smart-cff4e61d-6221-46b1-8e61-5c56b2ada9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349279795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2349279795
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.210252119
Short name T404
Test name
Test status
Simulation time 25017486 ps
CPU time 1.85 seconds
Started Jul 12 05:37:00 PM PDT 24
Finished Jul 12 05:37:05 PM PDT 24
Peak memory 214128 kb
Host smart-acffb7b6-0588-4aa9-a91d-667b244d0cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210252119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.210252119
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.2988359739
Short name T87
Test name
Test status
Simulation time 261305881 ps
CPU time 37.88 seconds
Started Jul 12 05:36:48 PM PDT 24
Finished Jul 12 05:37:27 PM PDT 24
Peak memory 250800 kb
Host smart-78cba584-fdbe-4c66-b5b2-024a8ba3e12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988359739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2988359739
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.287894662
Short name T637
Test name
Test status
Simulation time 235934182 ps
CPU time 7.38 seconds
Started Jul 12 05:36:58 PM PDT 24
Finished Jul 12 05:37:10 PM PDT 24
Peak memory 250932 kb
Host smart-3dc66b12-ed38-47fc-a66d-7635664d259a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287894662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.287894662
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.957819823
Short name T347
Test name
Test status
Simulation time 2682130256 ps
CPU time 11.95 seconds
Started Jul 12 05:36:54 PM PDT 24
Finished Jul 12 05:37:08 PM PDT 24
Peak memory 226028 kb
Host smart-05dd6211-c58d-4e52-8949-e499bf5abfd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957819823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.957819823
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1564635835
Short name T534
Test name
Test status
Simulation time 36148970 ps
CPU time 1.03 seconds
Started Jul 12 05:36:54 PM PDT 24
Finished Jul 12 05:36:59 PM PDT 24
Peak memory 212060 kb
Host smart-ecfa9b1d-e0f8-400f-9779-b9b28ea5494f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564635835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1564635835
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.1929503327
Short name T258
Test name
Test status
Simulation time 74428584 ps
CPU time 0.93 seconds
Started Jul 12 05:35:40 PM PDT 24
Finished Jul 12 05:35:44 PM PDT 24
Peak memory 208872 kb
Host smart-20abd1ab-2158-487c-80c5-db39e7a56a95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929503327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.1929503327
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3709510529
Short name T592
Test name
Test status
Simulation time 34950923 ps
CPU time 0.79 seconds
Started Jul 12 05:35:33 PM PDT 24
Finished Jul 12 05:35:36 PM PDT 24
Peak memory 208776 kb
Host smart-e0eedfaa-d778-438f-b734-9fa3cd4e0ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709510529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3709510529
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1007074763
Short name T14
Test name
Test status
Simulation time 4602849927 ps
CPU time 9.85 seconds
Started Jul 12 05:35:33 PM PDT 24
Finished Jul 12 05:35:45 PM PDT 24
Peak memory 226060 kb
Host smart-e67aeb70-5526-4b7c-8f5e-6b7c61fbc9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007074763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1007074763
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.3311488297
Short name T709
Test name
Test status
Simulation time 4992703468 ps
CPU time 21.99 seconds
Started Jul 12 05:35:37 PM PDT 24
Finished Jul 12 05:36:02 PM PDT 24
Peak memory 217660 kb
Host smart-e9f82300-5792-4b27-b056-1b5c35843d23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311488297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3311488297
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.731790243
Short name T291
Test name
Test status
Simulation time 1459697192 ps
CPU time 26.38 seconds
Started Jul 12 05:35:32 PM PDT 24
Finished Jul 12 05:36:01 PM PDT 24
Peak memory 225936 kb
Host smart-2c22bb06-b8db-4933-b775-d9c98c10ca5e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731790243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_err
ors.731790243
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.454365263
Short name T65
Test name
Test status
Simulation time 810519607 ps
CPU time 9.41 seconds
Started Jul 12 05:35:32 PM PDT 24
Finished Jul 12 05:35:43 PM PDT 24
Peak memory 217548 kb
Host smart-c05077c1-4dc2-4755-a663-0b855e4736ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454365263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.454365263
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.814370576
Short name T224
Test name
Test status
Simulation time 470204730 ps
CPU time 7.26 seconds
Started Jul 12 05:35:35 PM PDT 24
Finished Jul 12 05:35:44 PM PDT 24
Peak memory 218164 kb
Host smart-2f1ac953-3996-4164-98f2-1e68ef9100cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814370576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.814370576
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1561234771
Short name T760
Test name
Test status
Simulation time 1296797702 ps
CPU time 20.29 seconds
Started Jul 12 05:35:31 PM PDT 24
Finished Jul 12 05:35:52 PM PDT 24
Peak memory 217588 kb
Host smart-f9c611d0-288b-4688-9f6d-a7015bb07e90
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561234771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1561234771
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2874358697
Short name T273
Test name
Test status
Simulation time 638421683 ps
CPU time 8.29 seconds
Started Jul 12 05:35:30 PM PDT 24
Finished Jul 12 05:35:39 PM PDT 24
Peak memory 217700 kb
Host smart-2349c248-842c-499e-a9ed-117da9a14a9c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874358697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2874358697
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2217306558
Short name T818
Test name
Test status
Simulation time 7687006798 ps
CPU time 74.82 seconds
Started Jul 12 05:35:33 PM PDT 24
Finished Jul 12 05:36:50 PM PDT 24
Peak memory 281540 kb
Host smart-e698a85a-e17f-47a4-a1d1-6ddf84655412
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217306558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2217306558
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2432497520
Short name T828
Test name
Test status
Simulation time 771150447 ps
CPU time 7.16 seconds
Started Jul 12 05:35:37 PM PDT 24
Finished Jul 12 05:35:47 PM PDT 24
Peak memory 218136 kb
Host smart-9b2f4914-7a71-4e47-adfb-75a998e36de8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432497520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.2432497520
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3613339060
Short name T547
Test name
Test status
Simulation time 234961117 ps
CPU time 2.7 seconds
Started Jul 12 05:35:32 PM PDT 24
Finished Jul 12 05:35:37 PM PDT 24
Peak memory 218156 kb
Host smart-07355b06-8aaf-40e8-b1f9-a38627938fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613339060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3613339060
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.656568879
Short name T543
Test name
Test status
Simulation time 2061459200 ps
CPU time 6.51 seconds
Started Jul 12 05:35:36 PM PDT 24
Finished Jul 12 05:35:44 PM PDT 24
Peak memory 217660 kb
Host smart-47fd981d-54f3-4b99-a422-4fe10ff4028b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656568879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.656568879
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.2701406078
Short name T52
Test name
Test status
Simulation time 422885097 ps
CPU time 33.88 seconds
Started Jul 12 05:35:40 PM PDT 24
Finished Jul 12 05:36:17 PM PDT 24
Peak memory 268892 kb
Host smart-92f5fc95-61e1-42eb-9585-ec11ffc5784c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701406078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2701406078
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1233069574
Short name T683
Test name
Test status
Simulation time 294070497 ps
CPU time 15.51 seconds
Started Jul 12 05:35:33 PM PDT 24
Finished Jul 12 05:35:50 PM PDT 24
Peak memory 218820 kb
Host smart-ad219e63-cab7-4bb8-879c-f2cb788efbd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233069574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1233069574
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.890773392
Short name T272
Test name
Test status
Simulation time 364960466 ps
CPU time 12.56 seconds
Started Jul 12 05:35:32 PM PDT 24
Finished Jul 12 05:35:46 PM PDT 24
Peak memory 225956 kb
Host smart-bf507241-bcb5-4695-8862-32050937b02e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890773392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_dig
est.890773392
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.2814510152
Short name T304
Test name
Test status
Simulation time 859568813 ps
CPU time 8.06 seconds
Started Jul 12 05:35:33 PM PDT 24
Finished Jul 12 05:35:43 PM PDT 24
Peak memory 218196 kb
Host smart-f66b7bf2-b4b2-4df0-8e40-1ec1d48bc2fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814510152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.2
814510152
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.842896971
Short name T509
Test name
Test status
Simulation time 166734379 ps
CPU time 7.4 seconds
Started Jul 12 05:35:37 PM PDT 24
Finished Jul 12 05:35:48 PM PDT 24
Peak memory 225976 kb
Host smart-1733bbda-9e3a-4025-b350-3c7f25920f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842896971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.842896971
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3774899132
Short name T319
Test name
Test status
Simulation time 58054288 ps
CPU time 2.77 seconds
Started Jul 12 05:35:33 PM PDT 24
Finished Jul 12 05:35:38 PM PDT 24
Peak memory 214588 kb
Host smart-9686572c-95ba-4bce-a128-89cb4890a4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774899132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3774899132
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.920504238
Short name T104
Test name
Test status
Simulation time 693641246 ps
CPU time 20.43 seconds
Started Jul 12 05:35:31 PM PDT 24
Finished Jul 12 05:35:53 PM PDT 24
Peak memory 250900 kb
Host smart-b5122b45-fada-4553-bcfb-5bec1a74a158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920504238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.920504238
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3869298516
Short name T490
Test name
Test status
Simulation time 125600772 ps
CPU time 3.5 seconds
Started Jul 12 05:35:28 PM PDT 24
Finished Jul 12 05:35:33 PM PDT 24
Peak memory 218056 kb
Host smart-cf0389c0-e310-45e8-b2fa-e91bf9d9138a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869298516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3869298516
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.331735362
Short name T694
Test name
Test status
Simulation time 615297939 ps
CPU time 25.44 seconds
Started Jul 12 05:35:36 PM PDT 24
Finished Jul 12 05:36:03 PM PDT 24
Peak memory 217292 kb
Host smart-986332fe-dc69-4a8f-a3c4-d2d2987fe073
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331735362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.331735362
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1802901953
Short name T184
Test name
Test status
Simulation time 25222064 ps
CPU time 0.93 seconds
Started Jul 12 05:35:37 PM PDT 24
Finished Jul 12 05:35:42 PM PDT 24
Peak memory 211852 kb
Host smart-e5040cdd-43f2-4ef7-a624-6179d96d1aaf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802901953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.1802901953
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.3226062645
Short name T471
Test name
Test status
Simulation time 17446696 ps
CPU time 1.05 seconds
Started Jul 12 05:37:06 PM PDT 24
Finished Jul 12 05:37:11 PM PDT 24
Peak memory 208984 kb
Host smart-9464fbb4-d65e-471e-b391-61884bcf60a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226062645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3226062645
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2031441794
Short name T581
Test name
Test status
Simulation time 1648038676 ps
CPU time 13.99 seconds
Started Jul 12 05:36:54 PM PDT 24
Finished Jul 12 05:37:11 PM PDT 24
Peak memory 218148 kb
Host smart-bd11e27a-b4ea-4d58-88be-584f26d75530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031441794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2031441794
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1286657923
Short name T647
Test name
Test status
Simulation time 586673251 ps
CPU time 13.32 seconds
Started Jul 12 05:36:54 PM PDT 24
Finished Jul 12 05:37:10 PM PDT 24
Peak memory 217044 kb
Host smart-75605147-9292-42c9-b886-86ba8ababb75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286657923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1286657923
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.2684806182
Short name T188
Test name
Test status
Simulation time 70674567 ps
CPU time 3.63 seconds
Started Jul 12 05:37:02 PM PDT 24
Finished Jul 12 05:37:09 PM PDT 24
Peak memory 222440 kb
Host smart-9614ea83-46e1-41ad-8698-6da7068bcdaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684806182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2684806182
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1649426109
Short name T566
Test name
Test status
Simulation time 367564088 ps
CPU time 10.7 seconds
Started Jul 12 05:37:01 PM PDT 24
Finished Jul 12 05:37:15 PM PDT 24
Peak memory 225952 kb
Host smart-20ec8eff-cf3b-4aef-831a-349529284e3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649426109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1649426109
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.90302735
Short name T382
Test name
Test status
Simulation time 1331481059 ps
CPU time 7.81 seconds
Started Jul 12 05:37:01 PM PDT 24
Finished Jul 12 05:37:13 PM PDT 24
Peak memory 218044 kb
Host smart-c3d70b46-0294-47f8-8066-84af16dbe6b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90302735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.90302735
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.4152405521
Short name T811
Test name
Test status
Simulation time 3511413577 ps
CPU time 10.11 seconds
Started Jul 12 05:36:51 PM PDT 24
Finished Jul 12 05:37:02 PM PDT 24
Peak memory 225996 kb
Host smart-9ff4fb5e-89ff-4548-9390-36b1171c2db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152405521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.4152405521
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.352293084
Short name T72
Test name
Test status
Simulation time 30673273 ps
CPU time 2.11 seconds
Started Jul 12 05:36:57 PM PDT 24
Finished Jul 12 05:37:03 PM PDT 24
Peak memory 214024 kb
Host smart-9f7d867d-705e-4d10-84f3-09f48967577c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352293084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.352293084
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.3149844224
Short name T264
Test name
Test status
Simulation time 432710632 ps
CPU time 20.89 seconds
Started Jul 12 05:37:06 PM PDT 24
Finished Jul 12 05:37:32 PM PDT 24
Peak memory 250908 kb
Host smart-df88ef4a-e25c-4d65-977c-46454ba57635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149844224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.3149844224
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.886162164
Short name T865
Test name
Test status
Simulation time 365662937 ps
CPU time 8.22 seconds
Started Jul 12 05:37:06 PM PDT 24
Finished Jul 12 05:37:20 PM PDT 24
Peak memory 250948 kb
Host smart-07c7d985-f7c1-48e3-b6df-67c792189461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886162164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.886162164
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1780902362
Short name T797
Test name
Test status
Simulation time 6213265166 ps
CPU time 231.82 seconds
Started Jul 12 05:36:43 PM PDT 24
Finished Jul 12 05:40:36 PM PDT 24
Peak memory 283824 kb
Host smart-18df918b-5649-4c99-8f08-1191edd61233
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780902362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1780902362
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3002933119
Short name T313
Test name
Test status
Simulation time 59736839 ps
CPU time 0.86 seconds
Started Jul 12 05:36:56 PM PDT 24
Finished Jul 12 05:37:01 PM PDT 24
Peak memory 212864 kb
Host smart-aa4557e4-46c2-43ab-b03a-18ceb4670ff4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002933119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3002933119
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.3077370399
Short name T834
Test name
Test status
Simulation time 57353636 ps
CPU time 0.88 seconds
Started Jul 12 05:37:14 PM PDT 24
Finished Jul 12 05:37:20 PM PDT 24
Peak memory 208772 kb
Host smart-2c8cbbff-c662-4eb0-b484-142403ee5d31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077370399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.3077370399
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2624148311
Short name T350
Test name
Test status
Simulation time 1199271529 ps
CPU time 13.81 seconds
Started Jul 12 05:36:56 PM PDT 24
Finished Jul 12 05:37:14 PM PDT 24
Peak memory 217180 kb
Host smart-7ee95144-1ebe-4eca-bc7b-cd8ae76ead6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624148311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.2624148311
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.3073820196
Short name T101
Test name
Test status
Simulation time 75720560 ps
CPU time 2.92 seconds
Started Jul 12 05:36:52 PM PDT 24
Finished Jul 12 05:36:56 PM PDT 24
Peak memory 218136 kb
Host smart-3390dc6e-a0c9-4c61-a320-6665da6cf263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073820196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.3073820196
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.3820711470
Short name T844
Test name
Test status
Simulation time 604480036 ps
CPU time 17.9 seconds
Started Jul 12 05:36:51 PM PDT 24
Finished Jul 12 05:37:10 PM PDT 24
Peak memory 226196 kb
Host smart-94ba84a3-3da9-46b6-abda-b2b404496fc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820711470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.3820711470
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.497347961
Short name T525
Test name
Test status
Simulation time 316651188 ps
CPU time 7.68 seconds
Started Jul 12 05:36:53 PM PDT 24
Finished Jul 12 05:37:04 PM PDT 24
Peak memory 218272 kb
Host smart-4acdabb9-709b-4ae2-ac15-cf931e44e656
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497347961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.497347961
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3320252014
Short name T598
Test name
Test status
Simulation time 1527265724 ps
CPU time 10.77 seconds
Started Jul 12 05:37:02 PM PDT 24
Finished Jul 12 05:37:17 PM PDT 24
Peak memory 225620 kb
Host smart-64159714-84e0-44c6-bdc2-d6a599d7b45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320252014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3320252014
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1483701095
Short name T228
Test name
Test status
Simulation time 45342935 ps
CPU time 1.09 seconds
Started Jul 12 05:36:56 PM PDT 24
Finished Jul 12 05:37:00 PM PDT 24
Peak memory 213600 kb
Host smart-33cf5302-ca09-4d9a-bcf7-356d5bd45105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483701095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1483701095
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.3909728113
Short name T405
Test name
Test status
Simulation time 614847343 ps
CPU time 26.32 seconds
Started Jul 12 05:37:04 PM PDT 24
Finished Jul 12 05:37:35 PM PDT 24
Peak memory 250992 kb
Host smart-408f11fd-7df1-4a7e-a894-5e97f2f8acec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909728113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.3909728113
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.2735287525
Short name T314
Test name
Test status
Simulation time 58379828 ps
CPU time 6.23 seconds
Started Jul 12 05:37:10 PM PDT 24
Finished Jul 12 05:37:23 PM PDT 24
Peak memory 244820 kb
Host smart-cfde52a0-d2f8-43a8-8627-fa6a2123b0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735287525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.2735287525
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2675637550
Short name T839
Test name
Test status
Simulation time 14813685200 ps
CPU time 221.79 seconds
Started Jul 12 05:37:05 PM PDT 24
Finished Jul 12 05:40:52 PM PDT 24
Peak memory 259056 kb
Host smart-063ee5c5-909f-4f3f-be43-fc166b6d28e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675637550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2675637550
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2040054955
Short name T594
Test name
Test status
Simulation time 96029383 ps
CPU time 0.94 seconds
Started Jul 12 05:37:14 PM PDT 24
Finished Jul 12 05:37:21 PM PDT 24
Peak memory 211720 kb
Host smart-b3706551-c0b7-4808-96f0-ef023539bf60
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040054955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.2040054955
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1789628790
Short name T613
Test name
Test status
Simulation time 21902826 ps
CPU time 1.3 seconds
Started Jul 12 05:37:21 PM PDT 24
Finished Jul 12 05:37:29 PM PDT 24
Peak memory 209108 kb
Host smart-f24cf33a-7989-4e51-bd3e-e64fea2029b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789628790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1789628790
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.507925793
Short name T757
Test name
Test status
Simulation time 639664871 ps
CPU time 15.54 seconds
Started Jul 12 05:36:58 PM PDT 24
Finished Jul 12 05:37:18 PM PDT 24
Peak memory 218144 kb
Host smart-12609825-0511-42e0-b3a3-c398cee4cf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507925793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.507925793
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3936818964
Short name T788
Test name
Test status
Simulation time 602629995 ps
CPU time 4.56 seconds
Started Jul 12 05:37:03 PM PDT 24
Finished Jul 12 05:37:12 PM PDT 24
Peak memory 216988 kb
Host smart-9106a2fa-cb67-47b9-83c9-f1528f3dc261
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936818964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3936818964
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2302694623
Short name T520
Test name
Test status
Simulation time 251597222 ps
CPU time 3.3 seconds
Started Jul 12 05:37:05 PM PDT 24
Finished Jul 12 05:37:13 PM PDT 24
Peak memory 218072 kb
Host smart-748ba278-9ecc-4559-a1ad-bba69067161b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302694623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2302694623
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.746805849
Short name T744
Test name
Test status
Simulation time 1566625858 ps
CPU time 11.49 seconds
Started Jul 12 05:37:07 PM PDT 24
Finished Jul 12 05:37:24 PM PDT 24
Peak memory 218204 kb
Host smart-63d2e8b4-fd06-43b0-a881-8904be897a91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746805849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.746805849
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.152301612
Short name T86
Test name
Test status
Simulation time 500682700 ps
CPU time 11.03 seconds
Started Jul 12 05:37:13 PM PDT 24
Finished Jul 12 05:37:30 PM PDT 24
Peak memory 225720 kb
Host smart-441a77da-0691-497e-b313-f95ae9633007
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152301612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_di
gest.152301612
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3292459450
Short name T789
Test name
Test status
Simulation time 1007735388 ps
CPU time 9.14 seconds
Started Jul 12 05:37:17 PM PDT 24
Finished Jul 12 05:37:33 PM PDT 24
Peak memory 218184 kb
Host smart-a448fd9b-c96f-408d-b988-0f4f7b2f106a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292459450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
3292459450
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3318204506
Short name T500
Test name
Test status
Simulation time 534271529 ps
CPU time 7.2 seconds
Started Jul 12 05:37:03 PM PDT 24
Finished Jul 12 05:37:14 PM PDT 24
Peak memory 218136 kb
Host smart-2f1aba07-ca65-4bf1-b3f5-9719151c4b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318204506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3318204506
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.4245801310
Short name T693
Test name
Test status
Simulation time 103183660 ps
CPU time 2.31 seconds
Started Jul 12 05:37:12 PM PDT 24
Finished Jul 12 05:37:20 PM PDT 24
Peak memory 217544 kb
Host smart-791ec66a-f6fc-4bc0-abdb-c72d70c2b4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245801310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.4245801310
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.1196867760
Short name T261
Test name
Test status
Simulation time 848552860 ps
CPU time 22.88 seconds
Started Jul 12 05:37:14 PM PDT 24
Finished Jul 12 05:37:43 PM PDT 24
Peak memory 250916 kb
Host smart-ea1c9036-f963-4d71-98d8-533830eb7b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196867760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1196867760
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.2123936792
Short name T456
Test name
Test status
Simulation time 64346730 ps
CPU time 6.53 seconds
Started Jul 12 05:36:52 PM PDT 24
Finished Jul 12 05:37:01 PM PDT 24
Peak memory 246356 kb
Host smart-b87fa496-c6c4-4807-a452-00e38455feb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123936792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2123936792
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.2785237918
Short name T489
Test name
Test status
Simulation time 2069910946 ps
CPU time 61.69 seconds
Started Jul 12 05:36:57 PM PDT 24
Finished Jul 12 05:38:03 PM PDT 24
Peak memory 250864 kb
Host smart-c5abf865-fc81-420d-b967-863e847ab9a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785237918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.2785237918
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.331556664
Short name T149
Test name
Test status
Simulation time 92745144888 ps
CPU time 1012.08 seconds
Started Jul 12 05:36:52 PM PDT 24
Finished Jul 12 05:53:47 PM PDT 24
Peak memory 447636 kb
Host smart-9e667fcf-1188-411b-b9a2-5b55db4056df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=331556664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.331556664
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2883527902
Short name T251
Test name
Test status
Simulation time 26730915 ps
CPU time 0.91 seconds
Started Jul 12 05:36:57 PM PDT 24
Finished Jul 12 05:37:01 PM PDT 24
Peak memory 211788 kb
Host smart-b168e0ef-cb11-4bef-90c1-3b42058a1008
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883527902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2883527902
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.1218794857
Short name T723
Test name
Test status
Simulation time 17141138 ps
CPU time 0.93 seconds
Started Jul 12 05:37:16 PM PDT 24
Finished Jul 12 05:37:24 PM PDT 24
Peak memory 208908 kb
Host smart-f17b0052-b377-4c98-b138-e923e8d46353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218794857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.1218794857
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.627571435
Short name T666
Test name
Test status
Simulation time 986309801 ps
CPU time 11.22 seconds
Started Jul 12 05:37:00 PM PDT 24
Finished Jul 12 05:37:15 PM PDT 24
Peak memory 218096 kb
Host smart-fa6d9dab-6e78-411e-b7ce-7ed15d85dfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627571435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.627571435
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3637296218
Short name T190
Test name
Test status
Simulation time 53349010 ps
CPU time 1.99 seconds
Started Jul 12 05:36:56 PM PDT 24
Finished Jul 12 05:37:01 PM PDT 24
Peak memory 216996 kb
Host smart-2206583c-5f43-4ec9-8593-b1531916732a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637296218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.3637296218
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.1830962000
Short name T501
Test name
Test status
Simulation time 229940102 ps
CPU time 2.69 seconds
Started Jul 12 05:37:00 PM PDT 24
Finished Jul 12 05:37:07 PM PDT 24
Peak memory 218132 kb
Host smart-b031fbf2-4de5-475c-930e-0cc09b6da5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830962000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1830962000
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.3529359894
Short name T429
Test name
Test status
Simulation time 434192907 ps
CPU time 19.62 seconds
Started Jul 12 05:36:54 PM PDT 24
Finished Jul 12 05:37:17 PM PDT 24
Peak memory 225984 kb
Host smart-5e240944-b00a-46e2-868f-a406fc75cdcb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529359894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.3529359894
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2601500264
Short name T366
Test name
Test status
Simulation time 630383996 ps
CPU time 9.02 seconds
Started Jul 12 05:36:49 PM PDT 24
Finished Jul 12 05:37:00 PM PDT 24
Peak memory 225972 kb
Host smart-a93183bc-e2eb-4bc3-95ed-7093ce63e464
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601500264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.2601500264
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.928322568
Short name T408
Test name
Test status
Simulation time 3634456297 ps
CPU time 7.29 seconds
Started Jul 12 05:36:48 PM PDT 24
Finished Jul 12 05:36:56 PM PDT 24
Peak memory 226068 kb
Host smart-f1bb8741-0757-483f-bc8c-2f9d68a7e041
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928322568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.928322568
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2023270529
Short name T311
Test name
Test status
Simulation time 285420384 ps
CPU time 10.31 seconds
Started Jul 12 05:37:10 PM PDT 24
Finished Jul 12 05:37:26 PM PDT 24
Peak memory 225496 kb
Host smart-b53d113f-8adf-45a7-b916-dae6aed0b556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023270529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2023270529
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.3495204596
Short name T79
Test name
Test status
Simulation time 24126237 ps
CPU time 1.87 seconds
Started Jul 12 05:37:13 PM PDT 24
Finished Jul 12 05:37:21 PM PDT 24
Peak memory 217672 kb
Host smart-0ddb2a21-cc0e-4e58-b8c6-de11d0498a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495204596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3495204596
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.3441996019
Short name T494
Test name
Test status
Simulation time 291352183 ps
CPU time 33.16 seconds
Started Jul 12 05:37:11 PM PDT 24
Finished Jul 12 05:37:50 PM PDT 24
Peak memory 250908 kb
Host smart-85ea1a33-b2c1-4df2-8bed-f8fb735c9972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441996019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3441996019
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.571250022
Short name T422
Test name
Test status
Simulation time 276208288 ps
CPU time 7.28 seconds
Started Jul 12 05:36:52 PM PDT 24
Finished Jul 12 05:37:00 PM PDT 24
Peak memory 250908 kb
Host smart-5541a849-9433-4bc4-b716-bd7f6a142358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571250022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.571250022
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1474627929
Short name T783
Test name
Test status
Simulation time 3475664613 ps
CPU time 137.15 seconds
Started Jul 12 05:37:06 PM PDT 24
Finished Jul 12 05:39:29 PM PDT 24
Peak memory 248724 kb
Host smart-e9f35942-de3f-4f44-b06b-d5510c97d99c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474627929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1474627929
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.4023006514
Short name T250
Test name
Test status
Simulation time 20163132 ps
CPU time 0.85 seconds
Started Jul 12 05:37:00 PM PDT 24
Finished Jul 12 05:37:04 PM PDT 24
Peak memory 212904 kb
Host smart-23d94dd2-e1cb-4e14-9f98-a6f5d7da68ab
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023006514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.4023006514
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.2799984905
Short name T552
Test name
Test status
Simulation time 16621084 ps
CPU time 1.1 seconds
Started Jul 12 05:37:08 PM PDT 24
Finished Jul 12 05:37:16 PM PDT 24
Peak memory 208916 kb
Host smart-796ca4c0-b8f1-48bb-9b3a-15b0ea8acb23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799984905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.2799984905
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2394203209
Short name T318
Test name
Test status
Simulation time 371940362 ps
CPU time 14.53 seconds
Started Jul 12 05:37:18 PM PDT 24
Finished Jul 12 05:37:39 PM PDT 24
Peak memory 218044 kb
Host smart-5502d4d1-01f5-4888-8de1-ee012d1af9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394203209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2394203209
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.298241832
Short name T493
Test name
Test status
Simulation time 563977769 ps
CPU time 5.74 seconds
Started Jul 12 05:36:55 PM PDT 24
Finished Jul 12 05:37:04 PM PDT 24
Peak memory 217316 kb
Host smart-bb7faf5f-a6ea-4eee-9279-78b5cca70011
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298241832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.298241832
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.3485230335
Short name T2
Test name
Test status
Simulation time 18727646 ps
CPU time 1.52 seconds
Started Jul 12 05:37:04 PM PDT 24
Finished Jul 12 05:37:10 PM PDT 24
Peak memory 218152 kb
Host smart-47382da6-e858-40e1-b5ca-3dfaf4934897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485230335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.3485230335
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.204902193
Short name T19
Test name
Test status
Simulation time 197245837 ps
CPU time 8.6 seconds
Started Jul 12 05:37:05 PM PDT 24
Finished Jul 12 05:37:19 PM PDT 24
Peak memory 225980 kb
Host smart-df4b7da1-56a4-46f3-b142-caa758a6aab9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204902193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.204902193
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.4178940468
Short name T487
Test name
Test status
Simulation time 1966936513 ps
CPU time 12.15 seconds
Started Jul 12 05:37:13 PM PDT 24
Finished Jul 12 05:37:32 PM PDT 24
Peak memory 218044 kb
Host smart-f78be4d2-c56d-48f0-9447-6b4cfd1a61a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178940468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.4178940468
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.3377990148
Short name T275
Test name
Test status
Simulation time 686970507 ps
CPU time 6.4 seconds
Started Jul 12 05:37:22 PM PDT 24
Finished Jul 12 05:37:36 PM PDT 24
Peak memory 225840 kb
Host smart-449cd047-ba48-45f3-864e-37a13bbf7512
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377990148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
3377990148
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.61128264
Short name T822
Test name
Test status
Simulation time 3535540464 ps
CPU time 7.82 seconds
Started Jul 12 05:37:18 PM PDT 24
Finished Jul 12 05:37:32 PM PDT 24
Peak memory 218368 kb
Host smart-e4f3f536-e7f6-4485-a4f2-c1f3b14dcb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61128264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.61128264
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.806941027
Short name T186
Test name
Test status
Simulation time 19541743 ps
CPU time 1.65 seconds
Started Jul 12 05:37:19 PM PDT 24
Finished Jul 12 05:37:27 PM PDT 24
Peak memory 213996 kb
Host smart-a3ab79e1-f1d6-42c4-a1c0-e2f966942efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806941027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.806941027
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.618395932
Short name T632
Test name
Test status
Simulation time 339754502 ps
CPU time 28.55 seconds
Started Jul 12 05:37:09 PM PDT 24
Finished Jul 12 05:37:44 PM PDT 24
Peak memory 250916 kb
Host smart-5b18d6d3-7d78-465e-8cca-8ab45549121f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618395932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.618395932
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3018418504
Short name T463
Test name
Test status
Simulation time 545242773 ps
CPU time 8.46 seconds
Started Jul 12 05:37:11 PM PDT 24
Finished Jul 12 05:37:26 PM PDT 24
Peak memory 250896 kb
Host smart-c5df28f4-5c31-4e0a-8589-2445d6748362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018418504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3018418504
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.1117002727
Short name T57
Test name
Test status
Simulation time 19196711913 ps
CPU time 232.93 seconds
Started Jul 12 05:37:12 PM PDT 24
Finished Jul 12 05:41:11 PM PDT 24
Peak memory 250964 kb
Host smart-1139e0c4-8315-455c-b42a-c410908d9e62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117002727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.1117002727
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.767054208
Short name T800
Test name
Test status
Simulation time 11415576 ps
CPU time 1 seconds
Started Jul 12 05:37:04 PM PDT 24
Finished Jul 12 05:37:09 PM PDT 24
Peak memory 211752 kb
Host smart-9eef37f9-dc38-4523-9884-41554b5fe25e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767054208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ct
rl_volatile_unlock_smoke.767054208
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.748301171
Short name T850
Test name
Test status
Simulation time 79523833 ps
CPU time 1.2 seconds
Started Jul 12 05:37:04 PM PDT 24
Finished Jul 12 05:37:10 PM PDT 24
Peak memory 208944 kb
Host smart-ef696d6f-1042-4c05-b7e4-3fa3606052c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748301171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.748301171
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1731840419
Short name T349
Test name
Test status
Simulation time 489856580 ps
CPU time 10.87 seconds
Started Jul 12 05:37:12 PM PDT 24
Finished Jul 12 05:37:29 PM PDT 24
Peak memory 218140 kb
Host smart-74139d1a-13a4-4eb6-9a4c-70d45b2b8f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731840419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1731840419
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.86775400
Short name T567
Test name
Test status
Simulation time 97965644 ps
CPU time 1.72 seconds
Started Jul 12 05:37:10 PM PDT 24
Finished Jul 12 05:37:18 PM PDT 24
Peak memory 217036 kb
Host smart-93a54f10-fb57-4d90-86ac-c8ac33b892b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86775400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.86775400
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2352510719
Short name T625
Test name
Test status
Simulation time 84068949 ps
CPU time 2.62 seconds
Started Jul 12 05:37:18 PM PDT 24
Finished Jul 12 05:37:27 PM PDT 24
Peak memory 218028 kb
Host smart-f5418f4e-ac96-4db7-aac4-d2fcfae91426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352510719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2352510719
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.2624172580
Short name T537
Test name
Test status
Simulation time 2252328233 ps
CPU time 17.04 seconds
Started Jul 12 05:37:13 PM PDT 24
Finished Jul 12 05:37:36 PM PDT 24
Peak memory 226044 kb
Host smart-7223d702-c619-40d6-a758-1ce04bcbc02f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624172580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.2624172580
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1646520707
Short name T495
Test name
Test status
Simulation time 355729251 ps
CPU time 10.84 seconds
Started Jul 12 05:37:12 PM PDT 24
Finished Jul 12 05:37:29 PM PDT 24
Peak memory 225960 kb
Host smart-9775523a-ee06-4b42-b6cb-40474c232e11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646520707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.1646520707
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.3351455906
Short name T338
Test name
Test status
Simulation time 4393368424 ps
CPU time 13.64 seconds
Started Jul 12 05:37:12 PM PDT 24
Finished Jul 12 05:37:31 PM PDT 24
Peak memory 226024 kb
Host smart-81c032f5-2eb0-4162-b97b-cada69cab08f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351455906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
3351455906
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.2641387276
Short name T446
Test name
Test status
Simulation time 708717847 ps
CPU time 8.79 seconds
Started Jul 12 05:37:05 PM PDT 24
Finished Jul 12 05:37:18 PM PDT 24
Peak memory 225912 kb
Host smart-feb95033-74fe-40c9-befa-d31901623ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641387276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2641387276
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.1119380693
Short name T584
Test name
Test status
Simulation time 178946669 ps
CPU time 2.97 seconds
Started Jul 12 05:37:16 PM PDT 24
Finished Jul 12 05:37:26 PM PDT 24
Peak memory 214700 kb
Host smart-39fb0637-66ac-4fec-898b-7efd07391086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119380693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.1119380693
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.3929102425
Short name T400
Test name
Test status
Simulation time 292338584 ps
CPU time 31.33 seconds
Started Jul 12 05:37:19 PM PDT 24
Finished Jul 12 05:37:57 PM PDT 24
Peak memory 250848 kb
Host smart-da39c31b-f96d-4fff-a091-8a3112af7a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929102425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.3929102425
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.646368997
Short name T281
Test name
Test status
Simulation time 55666842 ps
CPU time 6.67 seconds
Started Jul 12 05:36:58 PM PDT 24
Finished Jul 12 05:37:09 PM PDT 24
Peak memory 244912 kb
Host smart-c7333d7f-7d4d-4561-b10c-4d21e5e5fdf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646368997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.646368997
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.2783688814
Short name T47
Test name
Test status
Simulation time 4613704383 ps
CPU time 111.68 seconds
Started Jul 12 05:37:16 PM PDT 24
Finished Jul 12 05:39:14 PM PDT 24
Peak memory 293928 kb
Host smart-d9c65cb8-9bad-4988-b87a-79b17f2216db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783688814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.2783688814
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1677183621
Short name T428
Test name
Test status
Simulation time 21023138 ps
CPU time 0.97 seconds
Started Jul 12 05:36:50 PM PDT 24
Finished Jul 12 05:36:53 PM PDT 24
Peak memory 211868 kb
Host smart-e43afcca-4e9b-40e1-80e1-402e2403a89b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677183621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1677183621
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.2400844925
Short name T359
Test name
Test status
Simulation time 15022952 ps
CPU time 0.87 seconds
Started Jul 12 05:37:19 PM PDT 24
Finished Jul 12 05:37:28 PM PDT 24
Peak memory 208884 kb
Host smart-81c426a1-eb59-4c36-a08b-bba3599e6c31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400844925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2400844925
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.1653921413
Short name T322
Test name
Test status
Simulation time 1368045329 ps
CPU time 9.89 seconds
Started Jul 12 05:37:14 PM PDT 24
Finished Jul 12 05:37:30 PM PDT 24
Peak memory 225852 kb
Host smart-716cfc1f-d232-4e4b-ae1c-e3df0499d008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653921413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1653921413
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.3479210401
Short name T742
Test name
Test status
Simulation time 3933112071 ps
CPU time 6.4 seconds
Started Jul 12 05:37:00 PM PDT 24
Finished Jul 12 05:37:11 PM PDT 24
Peak memory 217680 kb
Host smart-40e232fe-d958-445a-8612-18fec7b5aab0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479210401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.3479210401
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.556501891
Short name T385
Test name
Test status
Simulation time 67392603 ps
CPU time 2.36 seconds
Started Jul 12 05:37:10 PM PDT 24
Finished Jul 12 05:37:24 PM PDT 24
Peak memory 218152 kb
Host smart-c0eba746-deff-46e7-925c-729235484936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556501891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.556501891
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.4210793956
Short name T640
Test name
Test status
Simulation time 1480791551 ps
CPU time 14.82 seconds
Started Jul 12 05:37:03 PM PDT 24
Finished Jul 12 05:37:22 PM PDT 24
Peak memory 219860 kb
Host smart-9124a70f-2e4f-4d93-a5bd-374a9987f1e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210793956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.4210793956
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.2494684716
Short name T229
Test name
Test status
Simulation time 807713751 ps
CPU time 18.68 seconds
Started Jul 12 05:37:17 PM PDT 24
Finished Jul 12 05:37:43 PM PDT 24
Peak memory 225960 kb
Host smart-47c4512c-c7fc-4bd2-b055-cdeb9e14e4c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494684716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.2494684716
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.1844634842
Short name T259
Test name
Test status
Simulation time 1104171711 ps
CPU time 7.52 seconds
Started Jul 12 05:37:15 PM PDT 24
Finished Jul 12 05:37:28 PM PDT 24
Peak memory 218048 kb
Host smart-b1f6353f-14d5-41b0-84a0-034973cd2d60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844634842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
1844634842
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.2075564560
Short name T341
Test name
Test status
Simulation time 687924104 ps
CPU time 9.14 seconds
Started Jul 12 05:37:18 PM PDT 24
Finished Jul 12 05:37:34 PM PDT 24
Peak memory 225916 kb
Host smart-c6f50d24-e0a0-4d78-b48f-c2aa9ab810d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075564560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.2075564560
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.2960611805
Short name T77
Test name
Test status
Simulation time 244620802 ps
CPU time 2.79 seconds
Started Jul 12 05:37:23 PM PDT 24
Finished Jul 12 05:37:33 PM PDT 24
Peak memory 217612 kb
Host smart-ef7a9b2d-6553-4c04-bf71-a9bff566fe36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960611805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.2960611805
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.1353034104
Short name T91
Test name
Test status
Simulation time 486301612 ps
CPU time 24.08 seconds
Started Jul 12 05:37:18 PM PDT 24
Finished Jul 12 05:37:49 PM PDT 24
Peak memory 250916 kb
Host smart-07e27bc4-339c-414a-a721-3890e4355ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353034104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1353034104
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.3462830775
Short name T532
Test name
Test status
Simulation time 430181264 ps
CPU time 7.74 seconds
Started Jul 12 05:37:09 PM PDT 24
Finished Jul 12 05:37:23 PM PDT 24
Peak memory 251032 kb
Host smart-6c3557a8-a149-4710-a8d1-3fbd4fdcff5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462830775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.3462830775
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.3352922333
Short name T295
Test name
Test status
Simulation time 15456475723 ps
CPU time 259.91 seconds
Started Jul 12 05:37:18 PM PDT 24
Finished Jul 12 05:41:45 PM PDT 24
Peak memory 283660 kb
Host smart-1c3e6a8a-3ba8-4035-9991-06ad8fd5f7fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352922333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.3352922333
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.3241224192
Short name T143
Test name
Test status
Simulation time 13131350129 ps
CPU time 289.45 seconds
Started Jul 12 05:37:17 PM PDT 24
Finished Jul 12 05:42:13 PM PDT 24
Peak memory 332900 kb
Host smart-ea181afc-23f0-45d0-b573-634d0f496282
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3241224192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.3241224192
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3582221856
Short name T181
Test name
Test status
Simulation time 66664600 ps
CPU time 0.95 seconds
Started Jul 12 05:37:14 PM PDT 24
Finished Jul 12 05:37:21 PM PDT 24
Peak memory 211736 kb
Host smart-909a08f4-87d7-49d3-abf4-768e76c27a40
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582221856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3582221856
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.2095071365
Short name T786
Test name
Test status
Simulation time 15846967 ps
CPU time 1.15 seconds
Started Jul 12 05:37:18 PM PDT 24
Finished Jul 12 05:37:32 PM PDT 24
Peak memory 208940 kb
Host smart-c2ce6657-f850-4856-83c0-f97a3c4f8238
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095071365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2095071365
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.3590959552
Short name T522
Test name
Test status
Simulation time 3475030972 ps
CPU time 9.82 seconds
Started Jul 12 05:37:16 PM PDT 24
Finished Jul 12 05:37:32 PM PDT 24
Peak memory 226024 kb
Host smart-8a832d25-d3ba-4f91-ae36-3b5bd7ed163f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590959552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.3590959552
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.2758049666
Short name T764
Test name
Test status
Simulation time 507512644 ps
CPU time 12.11 seconds
Started Jul 12 05:37:17 PM PDT 24
Finished Jul 12 05:37:37 PM PDT 24
Peak memory 217228 kb
Host smart-acd8432f-a034-4466-a068-3eb074427660
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758049666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.2758049666
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.348411261
Short name T754
Test name
Test status
Simulation time 163299875 ps
CPU time 4.41 seconds
Started Jul 12 05:37:18 PM PDT 24
Finished Jul 12 05:37:29 PM PDT 24
Peak memory 218144 kb
Host smart-d625d06d-55fe-4055-b348-b520e5d78f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348411261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.348411261
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.1436642786
Short name T245
Test name
Test status
Simulation time 434577472 ps
CPU time 18.79 seconds
Started Jul 12 05:37:01 PM PDT 24
Finished Jul 12 05:37:23 PM PDT 24
Peak memory 225852 kb
Host smart-fed58c8d-85c5-4d91-b943-907d0a75e467
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436642786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.1436642786
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.1378324575
Short name T564
Test name
Test status
Simulation time 2060187558 ps
CPU time 14.46 seconds
Started Jul 12 05:37:22 PM PDT 24
Finished Jul 12 05:37:44 PM PDT 24
Peak memory 225960 kb
Host smart-bce180d1-17f0-496f-8d82-fed42e8ecc1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378324575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.1378324575
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3599878359
Short name T354
Test name
Test status
Simulation time 2215254953 ps
CPU time 18.51 seconds
Started Jul 12 05:36:59 PM PDT 24
Finished Jul 12 05:37:21 PM PDT 24
Peak memory 225240 kb
Host smart-dc2fe932-eb83-4d82-ab34-a081a81b8d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599878359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3599878359
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.537927692
Short name T614
Test name
Test status
Simulation time 35973012 ps
CPU time 1.89 seconds
Started Jul 12 05:37:08 PM PDT 24
Finished Jul 12 05:37:17 PM PDT 24
Peak memory 217656 kb
Host smart-1e247a6f-a887-4e58-9bcc-33c8fc613faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537927692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.537927692
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.1496433402
Short name T521
Test name
Test status
Simulation time 338593619 ps
CPU time 27.47 seconds
Started Jul 12 05:37:06 PM PDT 24
Finished Jul 12 05:37:39 PM PDT 24
Peak memory 250908 kb
Host smart-160417d0-cbcc-4e40-b87c-1246896b5fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496433402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1496433402
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2871630340
Short name T152
Test name
Test status
Simulation time 94802382 ps
CPU time 7.4 seconds
Started Jul 12 05:37:04 PM PDT 24
Finished Jul 12 05:37:16 PM PDT 24
Peak memory 247128 kb
Host smart-9cb4e461-49c6-4cb7-8039-f0aa7dfebb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871630340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2871630340
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.1586411921
Short name T514
Test name
Test status
Simulation time 13768501965 ps
CPU time 32.02 seconds
Started Jul 12 05:37:01 PM PDT 24
Finished Jul 12 05:37:37 PM PDT 24
Peak memory 250936 kb
Host smart-d23380b5-4b9f-4d09-9703-58d2022b1e6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586411921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.1586411921
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3106002291
Short name T696
Test name
Test status
Simulation time 22218746 ps
CPU time 0.97 seconds
Started Jul 12 05:37:19 PM PDT 24
Finished Jul 12 05:37:27 PM PDT 24
Peak memory 211716 kb
Host smart-afc17234-37ae-4783-9c36-a15a30a70ec9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106002291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.3106002291
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.2347959146
Short name T440
Test name
Test status
Simulation time 90892162 ps
CPU time 1.21 seconds
Started Jul 12 05:37:16 PM PDT 24
Finished Jul 12 05:37:23 PM PDT 24
Peak memory 209136 kb
Host smart-d00da22a-5212-4a4b-ae86-57b8bca2f725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347959146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.2347959146
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.771287742
Short name T679
Test name
Test status
Simulation time 646211869 ps
CPU time 15.79 seconds
Started Jul 12 05:37:03 PM PDT 24
Finished Jul 12 05:37:24 PM PDT 24
Peak memory 218152 kb
Host smart-10ace623-3d95-4ea9-901b-988dd51605c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771287742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.771287742
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.1996247081
Short name T33
Test name
Test status
Simulation time 1096922239 ps
CPU time 3.62 seconds
Started Jul 12 05:37:20 PM PDT 24
Finished Jul 12 05:37:30 PM PDT 24
Peak memory 217076 kb
Host smart-922950e4-bb1a-46d8-9b4b-f2a8d7466b8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996247081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.1996247081
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.3825548056
Short name T794
Test name
Test status
Simulation time 55155936 ps
CPU time 2.37 seconds
Started Jul 12 05:37:06 PM PDT 24
Finished Jul 12 05:37:13 PM PDT 24
Peak memory 218160 kb
Host smart-bb272fde-1af9-420c-a8a1-0b31cb3bc1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825548056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3825548056
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.401840614
Short name T298
Test name
Test status
Simulation time 2688131068 ps
CPU time 16.04 seconds
Started Jul 12 05:37:20 PM PDT 24
Finished Jul 12 05:37:43 PM PDT 24
Peak memory 219112 kb
Host smart-bd2b6cb4-8d22-4106-8a63-f827633cb222
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401840614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.401840614
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.4028466272
Short name T375
Test name
Test status
Simulation time 262608031 ps
CPU time 10.73 seconds
Started Jul 12 05:37:04 PM PDT 24
Finished Jul 12 05:37:19 PM PDT 24
Peak memory 225944 kb
Host smart-8cd122b5-c1be-4c65-b3cf-b727e927aa69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028466272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.4028466272
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.4193243021
Short name T435
Test name
Test status
Simulation time 2242206661 ps
CPU time 18.51 seconds
Started Jul 12 05:37:27 PM PDT 24
Finished Jul 12 05:37:52 PM PDT 24
Peak memory 225952 kb
Host smart-2bed4fac-49d2-4623-8939-18b7f1195f99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193243021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
4193243021
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.1227044449
Short name T565
Test name
Test status
Simulation time 344620692 ps
CPU time 6.6 seconds
Started Jul 12 05:37:11 PM PDT 24
Finished Jul 12 05:37:24 PM PDT 24
Peak memory 224728 kb
Host smart-8b3ccdc7-932c-488d-b8f1-50c56e56a777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227044449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1227044449
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.2488318156
Short name T76
Test name
Test status
Simulation time 584510461 ps
CPU time 2.01 seconds
Started Jul 12 05:37:01 PM PDT 24
Finished Jul 12 05:37:06 PM PDT 24
Peak memory 214032 kb
Host smart-ac1d05dd-bf87-4a68-8935-7644fbffe8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488318156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.2488318156
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1807509356
Short name T562
Test name
Test status
Simulation time 1511372979 ps
CPU time 26.14 seconds
Started Jul 12 05:37:12 PM PDT 24
Finished Jul 12 05:37:44 PM PDT 24
Peak memory 250912 kb
Host smart-7a3d41a4-4027-4647-b9b7-3369682dcf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807509356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1807509356
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3106078179
Short name T478
Test name
Test status
Simulation time 646780298 ps
CPU time 8.96 seconds
Started Jul 12 05:37:17 PM PDT 24
Finished Jul 12 05:37:32 PM PDT 24
Peak memory 250784 kb
Host smart-3b3301db-3b79-4e8c-a2f1-096131bc7c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106078179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3106078179
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.565747949
Short name T486
Test name
Test status
Simulation time 1656362268 ps
CPU time 41.93 seconds
Started Jul 12 05:37:16 PM PDT 24
Finished Jul 12 05:38:04 PM PDT 24
Peak memory 245108 kb
Host smart-84f3b279-a8ca-4d74-9860-a348ed7a1e67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565747949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.565747949
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.4159015736
Short name T317
Test name
Test status
Simulation time 60307286 ps
CPU time 1.18 seconds
Started Jul 12 05:37:09 PM PDT 24
Finished Jul 12 05:37:16 PM PDT 24
Peak memory 213180 kb
Host smart-faf28de7-7cf5-40e8-a412-c4c3148939e4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159015736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.4159015736
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.1656506804
Short name T151
Test name
Test status
Simulation time 80032428 ps
CPU time 0.89 seconds
Started Jul 12 05:37:08 PM PDT 24
Finished Jul 12 05:37:15 PM PDT 24
Peak memory 208868 kb
Host smart-d22a64f6-738b-4026-b9c2-39aaf4c1902c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656506804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.1656506804
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2846020629
Short name T17
Test name
Test status
Simulation time 339439026 ps
CPU time 16.27 seconds
Started Jul 12 05:37:05 PM PDT 24
Finished Jul 12 05:37:27 PM PDT 24
Peak memory 218172 kb
Host smart-bc263064-9640-4cbc-8b04-fac0e3a91f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846020629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2846020629
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.2484160225
Short name T369
Test name
Test status
Simulation time 286421554 ps
CPU time 4.08 seconds
Started Jul 12 05:37:14 PM PDT 24
Finished Jul 12 05:37:23 PM PDT 24
Peak memory 217072 kb
Host smart-ecf6dcf8-fbea-420b-baca-417a1a151085
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484160225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.2484160225
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.1011759129
Short name T448
Test name
Test status
Simulation time 197332326 ps
CPU time 2.68 seconds
Started Jul 12 05:37:05 PM PDT 24
Finished Jul 12 05:37:13 PM PDT 24
Peak memory 218148 kb
Host smart-66cf60c0-587c-487d-8fe5-0058e8a062d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011759129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.1011759129
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.3278429963
Short name T704
Test name
Test status
Simulation time 998186484 ps
CPU time 11.36 seconds
Started Jul 12 05:37:13 PM PDT 24
Finished Jul 12 05:37:30 PM PDT 24
Peak memory 225984 kb
Host smart-ee498454-415f-4904-b5ba-faa418665fe2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278429963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.3278429963
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2829275442
Short name T769
Test name
Test status
Simulation time 1301210595 ps
CPU time 13.47 seconds
Started Jul 12 05:37:28 PM PDT 24
Finished Jul 12 05:37:47 PM PDT 24
Peak memory 225952 kb
Host smart-b2676726-60f7-4f06-ba41-eba81a2733f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829275442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.2829275442
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2018680612
Short name T450
Test name
Test status
Simulation time 412701482 ps
CPU time 10.42 seconds
Started Jul 12 05:37:15 PM PDT 24
Finished Jul 12 05:37:32 PM PDT 24
Peak memory 225860 kb
Host smart-af00652e-2e67-4fe7-ac7b-62fa77014c8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018680612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2018680612
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.4077712199
Short name T479
Test name
Test status
Simulation time 227078066 ps
CPU time 7.42 seconds
Started Jul 12 05:37:22 PM PDT 24
Finished Jul 12 05:37:37 PM PDT 24
Peak memory 224960 kb
Host smart-968b8043-6314-4389-aadb-d028a6012106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077712199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.4077712199
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.986718203
Short name T464
Test name
Test status
Simulation time 16752067 ps
CPU time 1.52 seconds
Started Jul 12 05:37:19 PM PDT 24
Finished Jul 12 05:37:27 PM PDT 24
Peak memory 223196 kb
Host smart-adfd2e4b-a5e4-4882-9e00-a3113ba516e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986718203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.986718203
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.3411920678
Short name T671
Test name
Test status
Simulation time 194079978 ps
CPU time 27.15 seconds
Started Jul 12 05:37:03 PM PDT 24
Finished Jul 12 05:37:34 PM PDT 24
Peak memory 250908 kb
Host smart-941dd44f-530b-489f-ab30-38ff7f7bcc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411920678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3411920678
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.3446674253
Short name T165
Test name
Test status
Simulation time 122213400 ps
CPU time 8.89 seconds
Started Jul 12 05:37:15 PM PDT 24
Finished Jul 12 05:37:31 PM PDT 24
Peak memory 250820 kb
Host smart-b18c2312-7d8a-4df5-8df1-cb4efffaad83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446674253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3446674253
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3206225134
Short name T645
Test name
Test status
Simulation time 7468898924 ps
CPU time 54.89 seconds
Started Jul 12 05:37:17 PM PDT 24
Finished Jul 12 05:38:20 PM PDT 24
Peak memory 277076 kb
Host smart-f186c9c6-e3b2-4311-bea6-b6a22df1961b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206225134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3206225134
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.415198985
Short name T727
Test name
Test status
Simulation time 11668847 ps
CPU time 1 seconds
Started Jul 12 05:37:15 PM PDT 24
Finished Jul 12 05:37:23 PM PDT 24
Peak memory 211768 kb
Host smart-c33b363b-b7ab-48a8-8c1e-031d3023f088
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415198985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ct
rl_volatile_unlock_smoke.415198985
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3928409269
Short name T774
Test name
Test status
Simulation time 17441904 ps
CPU time 0.9 seconds
Started Jul 12 05:35:44 PM PDT 24
Finished Jul 12 05:35:49 PM PDT 24
Peak memory 208800 kb
Host smart-5fed6234-1596-45ad-a701-528eaaff92ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928409269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3928409269
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2059230839
Short name T220
Test name
Test status
Simulation time 13536556 ps
CPU time 0.86 seconds
Started Jul 12 05:35:36 PM PDT 24
Finished Jul 12 05:35:40 PM PDT 24
Peak memory 208640 kb
Host smart-c0a743d2-7a19-41ad-a5ed-e1b5308c5f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059230839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2059230839
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.1199258638
Short name T504
Test name
Test status
Simulation time 691639665 ps
CPU time 16.45 seconds
Started Jul 12 05:35:36 PM PDT 24
Finished Jul 12 05:35:55 PM PDT 24
Peak memory 218152 kb
Host smart-6dfe5119-23ed-4668-ac21-550a1bb4d722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199258638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1199258638
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2859107920
Short name T582
Test name
Test status
Simulation time 789956264 ps
CPU time 2.64 seconds
Started Jul 12 05:35:37 PM PDT 24
Finished Jul 12 05:35:43 PM PDT 24
Peak memory 217024 kb
Host smart-80583497-6572-43c7-82e5-2bbe9060da31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859107920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2859107920
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.3500582950
Short name T570
Test name
Test status
Simulation time 1259513407 ps
CPU time 21.92 seconds
Started Jul 12 05:35:41 PM PDT 24
Finished Jul 12 05:36:05 PM PDT 24
Peak memory 218160 kb
Host smart-12e4059b-fcc3-4946-9622-23764bd44cee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500582950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.3500582950
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.60433863
Short name T24
Test name
Test status
Simulation time 155946100 ps
CPU time 4.64 seconds
Started Jul 12 05:45:22 PM PDT 24
Finished Jul 12 05:45:28 PM PDT 24
Peak memory 217364 kb
Host smart-c2cce901-e8f0-4fdb-9c11-2e046ce29295
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60433863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.60433863
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3822634762
Short name T604
Test name
Test status
Simulation time 290555734 ps
CPU time 3.23 seconds
Started Jul 12 05:35:36 PM PDT 24
Finished Jul 12 05:35:42 PM PDT 24
Peak memory 218144 kb
Host smart-51340986-2419-46f9-939a-66cc26a6f5df
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822634762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3822634762
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3973390967
Short name T453
Test name
Test status
Simulation time 8151235992 ps
CPU time 21.75 seconds
Started Jul 12 05:35:43 PM PDT 24
Finished Jul 12 05:36:09 PM PDT 24
Peak memory 217704 kb
Host smart-315feecc-a6c2-4a7c-a28e-81686b8bcdf6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973390967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.3973390967
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1198230163
Short name T491
Test name
Test status
Simulation time 490872678 ps
CPU time 4.28 seconds
Started Jul 12 05:35:44 PM PDT 24
Finished Jul 12 05:35:52 PM PDT 24
Peak memory 217772 kb
Host smart-79128a10-5866-4d29-a688-ef3ca3ac6bb7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198230163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1198230163
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.387735577
Short name T643
Test name
Test status
Simulation time 788575149 ps
CPU time 7.5 seconds
Started Jul 12 05:35:39 PM PDT 24
Finished Jul 12 05:35:49 PM PDT 24
Peak memory 222672 kb
Host smart-439cddeb-d11f-4489-b79e-0e1946a3a769
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387735577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_state_post_trans.387735577
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1536755587
Short name T649
Test name
Test status
Simulation time 45679415 ps
CPU time 2.5 seconds
Started Jul 12 05:35:37 PM PDT 24
Finished Jul 12 05:35:43 PM PDT 24
Peak memory 218128 kb
Host smart-3302b0be-1e4d-4af2-a50a-54eeb084b7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536755587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1536755587
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.2682268046
Short name T98
Test name
Test status
Simulation time 222708321 ps
CPU time 5.78 seconds
Started Jul 12 05:35:38 PM PDT 24
Finished Jul 12 05:35:48 PM PDT 24
Peak memory 217548 kb
Host smart-7d7a334d-1689-4eef-bff4-2585c6357f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682268046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2682268046
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2011883820
Short name T4
Test name
Test status
Simulation time 243709971 ps
CPU time 8.46 seconds
Started Jul 12 05:35:36 PM PDT 24
Finished Jul 12 05:35:47 PM PDT 24
Peak memory 225868 kb
Host smart-716d8c54-2e81-41fd-bf44-56b6ccdfcc48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011883820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.2011883820
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3584317800
Short name T678
Test name
Test status
Simulation time 213069276 ps
CPU time 8.22 seconds
Started Jul 12 05:35:42 PM PDT 24
Finished Jul 12 05:35:53 PM PDT 24
Peak memory 225724 kb
Host smart-3b2af660-6b77-4844-b594-edccf39ad147
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584317800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
584317800
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.2839459618
Short name T50
Test name
Test status
Simulation time 502852209 ps
CPU time 10.14 seconds
Started Jul 12 05:35:44 PM PDT 24
Finished Jul 12 05:35:58 PM PDT 24
Peak memory 226080 kb
Host smart-3befd459-5e2d-4503-9d57-da65538e53b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839459618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.2839459618
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.3299045715
Short name T62
Test name
Test status
Simulation time 132741396 ps
CPU time 1.84 seconds
Started Jul 12 05:35:44 PM PDT 24
Finished Jul 12 05:35:50 PM PDT 24
Peak memory 217572 kb
Host smart-0ca0e3f8-f5c7-4586-80ab-e4da25b15c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299045715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3299045715
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.812064255
Short name T299
Test name
Test status
Simulation time 945603636 ps
CPU time 23.41 seconds
Started Jul 12 05:35:49 PM PDT 24
Finished Jul 12 05:36:16 PM PDT 24
Peak memory 250900 kb
Host smart-49539c72-ba70-4283-a653-315a433e113f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812064255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.812064255
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.4112349966
Short name T169
Test name
Test status
Simulation time 363658754 ps
CPU time 6.38 seconds
Started Jul 12 05:35:38 PM PDT 24
Finished Jul 12 05:35:48 PM PDT 24
Peak memory 242840 kb
Host smart-804950ad-3522-4008-86d7-2f99d41aafdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112349966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.4112349966
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.3181792111
Short name T772
Test name
Test status
Simulation time 2875271467 ps
CPU time 29.01 seconds
Started Jul 12 05:35:37 PM PDT 24
Finished Jul 12 05:36:10 PM PDT 24
Peak memory 250956 kb
Host smart-5b00ffa8-33dd-4dc9-9ef9-d62d187fa34c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181792111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.3181792111
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.2760073976
Short name T216
Test name
Test status
Simulation time 379207710318 ps
CPU time 801.54 seconds
Started Jul 12 05:35:39 PM PDT 24
Finished Jul 12 05:49:04 PM PDT 24
Peak memory 447556 kb
Host smart-7570e11e-7810-44f3-b565-8420a0eca369
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2760073976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.2760073976
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2201933618
Short name T518
Test name
Test status
Simulation time 18404030 ps
CPU time 0.83 seconds
Started Jul 12 05:35:40 PM PDT 24
Finished Jul 12 05:35:43 PM PDT 24
Peak memory 211820 kb
Host smart-819aa2a8-29dc-4062-a630-7fe9718c24bf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201933618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.2201933618
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.2953244748
Short name T430
Test name
Test status
Simulation time 50160987 ps
CPU time 1.03 seconds
Started Jul 12 05:35:38 PM PDT 24
Finished Jul 12 05:35:42 PM PDT 24
Peak memory 209000 kb
Host smart-9e9ccd66-6e0c-48b0-8d50-06b024df6da9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953244748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2953244748
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3305808015
Short name T855
Test name
Test status
Simulation time 33460014 ps
CPU time 0.83 seconds
Started Jul 12 05:35:41 PM PDT 24
Finished Jul 12 05:35:44 PM PDT 24
Peak memory 208832 kb
Host smart-a3aa673c-0558-4432-9bb8-4b145ccd20bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305808015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3305808015
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.1975463625
Short name T243
Test name
Test status
Simulation time 787162056 ps
CPU time 21.39 seconds
Started Jul 12 05:35:37 PM PDT 24
Finished Jul 12 05:36:02 PM PDT 24
Peak memory 218140 kb
Host smart-d010c9b2-c553-4930-a3c4-2dc4359d0f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975463625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1975463625
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1421727227
Short name T810
Test name
Test status
Simulation time 254077938 ps
CPU time 6.94 seconds
Started Jul 12 05:35:39 PM PDT 24
Finished Jul 12 05:35:49 PM PDT 24
Peak memory 217244 kb
Host smart-7795aabb-d556-4814-b8e4-e4b647afd9ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421727227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1421727227
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.286314956
Short name T668
Test name
Test status
Simulation time 5606306868 ps
CPU time 83.95 seconds
Started Jul 12 05:35:39 PM PDT 24
Finished Jul 12 05:37:07 PM PDT 24
Peak memory 219964 kb
Host smart-2550853c-f016-4216-bd46-c600c1e53efe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286314956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_err
ors.286314956
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.4048891929
Short name T688
Test name
Test status
Simulation time 2242643358 ps
CPU time 9.45 seconds
Started Jul 12 05:35:46 PM PDT 24
Finished Jul 12 05:35:59 PM PDT 24
Peak memory 217640 kb
Host smart-02e82ecf-24d5-4d69-9834-2dd69ad4307d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048891929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.4
048891929
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.960417288
Short name T806
Test name
Test status
Simulation time 741903305 ps
CPU time 12.64 seconds
Started Jul 12 05:35:40 PM PDT 24
Finished Jul 12 05:35:56 PM PDT 24
Peak memory 218144 kb
Host smart-82fc0f65-21d0-4678-b6c3-8a5b465aba95
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960417288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
prog_failure.960417288
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3593904838
Short name T78
Test name
Test status
Simulation time 1261349396 ps
CPU time 18.82 seconds
Started Jul 12 05:35:44 PM PDT 24
Finished Jul 12 05:36:07 PM PDT 24
Peak memory 217520 kb
Host smart-16123b8c-b7ea-4b12-b198-40a59c2ce8fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593904838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.3593904838
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.2100618442
Short name T240
Test name
Test status
Simulation time 201934804 ps
CPU time 2.87 seconds
Started Jul 12 05:35:42 PM PDT 24
Finished Jul 12 05:35:48 PM PDT 24
Peak memory 217708 kb
Host smart-41975a06-9596-42ad-975f-1ffd8c9203f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100618442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
2100618442
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.3010569665
Short name T692
Test name
Test status
Simulation time 7298195082 ps
CPU time 47.22 seconds
Started Jul 12 05:35:44 PM PDT 24
Finished Jul 12 05:36:35 PM PDT 24
Peak memory 276856 kb
Host smart-e154cf03-aeb6-4397-b5f2-0a80e9063487
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010569665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.3010569665
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2273613010
Short name T427
Test name
Test status
Simulation time 1694098216 ps
CPU time 6.39 seconds
Started Jul 12 05:35:40 PM PDT 24
Finished Jul 12 05:35:49 PM PDT 24
Peak memory 226300 kb
Host smart-1b156160-6f85-4fd6-b6c6-658ac3241dae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273613010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.2273613010
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3319601776
Short name T776
Test name
Test status
Simulation time 206198769 ps
CPU time 1.62 seconds
Started Jul 12 05:35:43 PM PDT 24
Finished Jul 12 05:35:49 PM PDT 24
Peak memory 221544 kb
Host smart-48da3ecd-7f03-4072-8e56-5c50ce095aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319601776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3319601776
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3679032180
Short name T180
Test name
Test status
Simulation time 322536891 ps
CPU time 11.55 seconds
Started Jul 12 05:35:43 PM PDT 24
Finished Jul 12 05:35:59 PM PDT 24
Peak memory 214696 kb
Host smart-56ae348c-975d-477f-9bd5-f7cd46ebc274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679032180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3679032180
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.118950552
Short name T488
Test name
Test status
Simulation time 1447621674 ps
CPU time 13.74 seconds
Started Jul 12 05:35:40 PM PDT 24
Finished Jul 12 05:35:56 PM PDT 24
Peak memory 219408 kb
Host smart-c41f528e-53de-4e65-84ad-051ee65dc083
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118950552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.118950552
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.4095037469
Short name T242
Test name
Test status
Simulation time 524583169 ps
CPU time 10.31 seconds
Started Jul 12 05:35:42 PM PDT 24
Finished Jul 12 05:35:55 PM PDT 24
Peak memory 225708 kb
Host smart-e17fbf21-c42e-41f2-b079-8ac1a4563c48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095037469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.4095037469
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.1971670921
Short name T781
Test name
Test status
Simulation time 564455949 ps
CPU time 10.34 seconds
Started Jul 12 05:35:43 PM PDT 24
Finished Jul 12 05:35:57 PM PDT 24
Peak memory 225888 kb
Host smart-5f6ec4aa-1677-42ab-81ab-c9864293ccf5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971670921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.1
971670921
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.2072782340
Short name T166
Test name
Test status
Simulation time 424677963 ps
CPU time 6.32 seconds
Started Jul 12 05:35:39 PM PDT 24
Finished Jul 12 05:35:48 PM PDT 24
Peak memory 224428 kb
Host smart-ee0ee502-c4b2-4d80-b320-7ed7276c60ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072782340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2072782340
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.2371226223
Short name T627
Test name
Test status
Simulation time 144263789 ps
CPU time 2.48 seconds
Started Jul 12 05:35:38 PM PDT 24
Finished Jul 12 05:35:44 PM PDT 24
Peak memory 223820 kb
Host smart-075173fd-8691-4687-a457-3c5c6963269b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371226223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.2371226223
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3698356097
Short name T557
Test name
Test status
Simulation time 381233851 ps
CPU time 26.93 seconds
Started Jul 12 05:35:37 PM PDT 24
Finished Jul 12 05:36:08 PM PDT 24
Peak memory 250820 kb
Host smart-665d33ce-5bc9-4586-a54a-49423913ebab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698356097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3698356097
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.1368347874
Short name T185
Test name
Test status
Simulation time 57925672 ps
CPU time 8.82 seconds
Started Jul 12 05:37:13 PM PDT 24
Finished Jul 12 05:37:27 PM PDT 24
Peak memory 250864 kb
Host smart-a0c3c567-5800-463b-8111-acd51109cb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368347874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.1368347874
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.3930680132
Short name T572
Test name
Test status
Simulation time 11160853453 ps
CPU time 338.66 seconds
Started Jul 12 05:35:42 PM PDT 24
Finished Jul 12 05:41:24 PM PDT 24
Peak memory 250988 kb
Host smart-19805685-900d-41c0-b142-fcf61c41e875
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930680132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.3930680132
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.605914352
Short name T719
Test name
Test status
Simulation time 36751528104 ps
CPU time 402.46 seconds
Started Jul 12 05:35:44 PM PDT 24
Finished Jul 12 05:42:31 PM PDT 24
Peak memory 283668 kb
Host smart-b9da3139-6856-4141-9f10-323e370fe81c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=605914352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.605914352
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.163951430
Short name T603
Test name
Test status
Simulation time 117424938 ps
CPU time 1.09 seconds
Started Jul 12 05:35:41 PM PDT 24
Finished Jul 12 05:35:45 PM PDT 24
Peak memory 213012 kb
Host smart-62c7e33f-aeda-4231-bb8e-7f3176610518
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163951430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctr
l_volatile_unlock_smoke.163951430
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.3400179537
Short name T336
Test name
Test status
Simulation time 213721482 ps
CPU time 0.95 seconds
Started Jul 12 05:35:39 PM PDT 24
Finished Jul 12 05:35:43 PM PDT 24
Peak memory 208848 kb
Host smart-49f0cdce-df9a-40c6-9583-a7cfc947f6e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400179537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.3400179537
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2256214734
Short name T222
Test name
Test status
Simulation time 32110346 ps
CPU time 0.78 seconds
Started Jul 12 05:35:43 PM PDT 24
Finished Jul 12 05:35:48 PM PDT 24
Peak memory 208840 kb
Host smart-1c43f9fe-2985-41fe-ac4d-3ba42970c89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256214734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2256214734
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.1089356985
Short name T303
Test name
Test status
Simulation time 1371997100 ps
CPU time 10.7 seconds
Started Jul 12 05:35:43 PM PDT 24
Finished Jul 12 05:35:58 PM PDT 24
Peak memory 225972 kb
Host smart-e911653f-d6af-431e-910b-ecdd44967d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089356985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.1089356985
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.2785691022
Short name T669
Test name
Test status
Simulation time 1475552810 ps
CPU time 13.35 seconds
Started Jul 12 05:35:45 PM PDT 24
Finished Jul 12 05:36:02 PM PDT 24
Peak memory 217212 kb
Host smart-71f44389-7552-4d0f-9d50-6ae6904453b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785691022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.2785691022
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.829089699
Short name T44
Test name
Test status
Simulation time 3771276879 ps
CPU time 103.12 seconds
Started Jul 12 05:35:43 PM PDT 24
Finished Jul 12 05:37:29 PM PDT 24
Peak memory 221052 kb
Host smart-9ad5e161-ab96-42de-876c-9583a535f0e5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829089699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_err
ors.829089699
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.150506083
Short name T808
Test name
Test status
Simulation time 1263760476 ps
CPU time 12.24 seconds
Started Jul 12 05:35:43 PM PDT 24
Finished Jul 12 05:35:59 PM PDT 24
Peak memory 217616 kb
Host smart-6147cda3-29cd-445a-bdee-c4688f8f6d32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150506083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.150506083
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1177262842
Short name T496
Test name
Test status
Simulation time 1597740340 ps
CPU time 7.11 seconds
Started Jul 12 05:35:44 PM PDT 24
Finished Jul 12 05:35:55 PM PDT 24
Peak memory 224000 kb
Host smart-e3d6c7bf-9fb1-49ea-a016-1ed84f6d23ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177262842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1177262842
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1782152267
Short name T667
Test name
Test status
Simulation time 3783144797 ps
CPU time 13.84 seconds
Started Jul 12 05:36:24 PM PDT 24
Finished Jul 12 05:36:38 PM PDT 24
Peak memory 217596 kb
Host smart-3d5cc980-535e-412b-bd98-65b18e41f113
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782152267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.1782152267
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1854443968
Short name T539
Test name
Test status
Simulation time 3633729931 ps
CPU time 7.51 seconds
Started Jul 12 05:35:39 PM PDT 24
Finished Jul 12 05:35:49 PM PDT 24
Peak memory 217700 kb
Host smart-f7fc4e58-d6d5-4548-bfc1-50fae0bb4852
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854443968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1854443968
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1669173138
Short name T333
Test name
Test status
Simulation time 1201302204 ps
CPU time 34.47 seconds
Started Jul 12 05:35:42 PM PDT 24
Finished Jul 12 05:36:19 PM PDT 24
Peak memory 251368 kb
Host smart-cacbc235-80d3-4399-aa92-26e3c26f201a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669173138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1669173138
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2666034813
Short name T533
Test name
Test status
Simulation time 1035742740 ps
CPU time 11.73 seconds
Started Jul 12 05:35:38 PM PDT 24
Finished Jul 12 05:35:53 PM PDT 24
Peak memory 246508 kb
Host smart-cbc943df-127d-41b4-b1a3-ed1e01964515
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666034813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2666034813
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.80900296
Short name T388
Test name
Test status
Simulation time 71676656 ps
CPU time 3.69 seconds
Started Jul 12 05:35:38 PM PDT 24
Finished Jul 12 05:35:46 PM PDT 24
Peak memory 218168 kb
Host smart-1c502dd6-9cc3-4c32-a028-19b6a19703dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80900296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.80900296
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3386761368
Short name T56
Test name
Test status
Simulation time 390242734 ps
CPU time 13.73 seconds
Started Jul 12 05:35:43 PM PDT 24
Finished Jul 12 05:36:01 PM PDT 24
Peak memory 214592 kb
Host smart-b6c19980-121c-4c34-ad5b-42d9ba6b8ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386761368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3386761368
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3199214147
Short name T183
Test name
Test status
Simulation time 284207384 ps
CPU time 9.57 seconds
Started Jul 12 05:35:43 PM PDT 24
Finished Jul 12 05:35:57 PM PDT 24
Peak memory 225916 kb
Host smart-84aeb747-a936-4671-8239-63b4b9532327
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199214147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3199214147
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.3046588399
Short name T280
Test name
Test status
Simulation time 863591423 ps
CPU time 5.71 seconds
Started Jul 12 05:35:37 PM PDT 24
Finished Jul 12 05:35:46 PM PDT 24
Peak memory 218144 kb
Host smart-b16af77d-a292-4c7a-bca9-2cb968064243
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046588399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.3
046588399
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.572753789
Short name T381
Test name
Test status
Simulation time 300711894 ps
CPU time 8.66 seconds
Started Jul 12 05:35:45 PM PDT 24
Finished Jul 12 05:35:57 PM PDT 24
Peak memory 225884 kb
Host smart-dec1a46a-8452-4a10-9de0-a56819d59d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572753789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.572753789
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2181601527
Short name T307
Test name
Test status
Simulation time 81567886 ps
CPU time 1.48 seconds
Started Jul 12 05:35:40 PM PDT 24
Finished Jul 12 05:35:44 PM PDT 24
Peak memory 217668 kb
Host smart-154b60be-8b70-414d-9bcd-d3c4d97007fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181601527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2181601527
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1368502466
Short name T293
Test name
Test status
Simulation time 1923881090 ps
CPU time 27.38 seconds
Started Jul 12 05:35:42 PM PDT 24
Finished Jul 12 05:36:12 PM PDT 24
Peak memory 245840 kb
Host smart-15f75fec-c36a-41ee-8286-4612653c3d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368502466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1368502466
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.2660195809
Short name T546
Test name
Test status
Simulation time 68848314 ps
CPU time 6.99 seconds
Started Jul 12 05:35:44 PM PDT 24
Finished Jul 12 05:35:55 PM PDT 24
Peak memory 251040 kb
Host smart-cd0324db-9e8e-4ac0-bb26-d74b1590ba77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660195809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2660195809
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.413337045
Short name T25
Test name
Test status
Simulation time 13025318578 ps
CPU time 79.58 seconds
Started Jul 12 05:35:42 PM PDT 24
Finished Jul 12 05:37:04 PM PDT 24
Peak memory 283588 kb
Host smart-566767ca-57b2-4f63-bcd4-be4cf680b087
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413337045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.413337045
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.3685375429
Short name T626
Test name
Test status
Simulation time 70985258 ps
CPU time 0.97 seconds
Started Jul 12 05:35:41 PM PDT 24
Finished Jul 12 05:35:44 PM PDT 24
Peak memory 212852 kb
Host smart-f132fd8e-2c9b-4fc6-b619-690518298456
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685375429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.3685375429
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1356192191
Short name T864
Test name
Test status
Simulation time 14629077 ps
CPU time 1.03 seconds
Started Jul 12 05:35:54 PM PDT 24
Finished Jul 12 05:35:57 PM PDT 24
Peak memory 208528 kb
Host smart-54409082-db54-41a3-a519-995116b9d926
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356192191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1356192191
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.60380131
Short name T218
Test name
Test status
Simulation time 165176052 ps
CPU time 0.83 seconds
Started Jul 12 05:35:45 PM PDT 24
Finished Jul 12 05:35:50 PM PDT 24
Peak memory 208932 kb
Host smart-316ac060-b7ee-4bee-b8e1-3744280f0dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60380131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.60380131
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.3022473995
Short name T232
Test name
Test status
Simulation time 1185833545 ps
CPU time 18.1 seconds
Started Jul 12 05:35:45 PM PDT 24
Finished Jul 12 05:36:07 PM PDT 24
Peak memory 225988 kb
Host smart-73ac8adb-f86c-468a-89e9-d7ed23eda914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022473995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3022473995
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.3943128063
Short name T31
Test name
Test status
Simulation time 909858862 ps
CPU time 2.42 seconds
Started Jul 12 05:35:49 PM PDT 24
Finished Jul 12 05:35:54 PM PDT 24
Peak memory 217024 kb
Host smart-ca8e710d-dd3f-4578-aeff-dde2ab0c6729
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943128063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3943128063
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.2548615179
Short name T88
Test name
Test status
Simulation time 1132057073 ps
CPU time 27.42 seconds
Started Jul 12 05:35:47 PM PDT 24
Finished Jul 12 05:36:18 PM PDT 24
Peak memory 218172 kb
Host smart-841754cb-9d42-404e-891d-7b045a497d2c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548615179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.2548615179
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1521632056
Short name T10
Test name
Test status
Simulation time 1556080490 ps
CPU time 36.34 seconds
Started Jul 12 05:35:48 PM PDT 24
Finished Jul 12 05:36:28 PM PDT 24
Peak memory 217736 kb
Host smart-00bd4fb6-e09e-41da-997d-4fe194bd690e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521632056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.1
521632056
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3298658730
Short name T302
Test name
Test status
Simulation time 457686328 ps
CPU time 6.59 seconds
Started Jul 12 05:35:45 PM PDT 24
Finished Jul 12 05:35:56 PM PDT 24
Peak memory 223892 kb
Host smart-356c2f2f-d823-4835-b7bd-f7c19c95b35f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298658730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3298658730
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3668859001
Short name T73
Test name
Test status
Simulation time 1371127851 ps
CPU time 18.16 seconds
Started Jul 12 05:35:45 PM PDT 24
Finished Jul 12 05:36:07 PM PDT 24
Peak memory 217656 kb
Host smart-1d6021b4-aebb-43b5-abd6-29efcfe635f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668859001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.3668859001
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2456604951
Short name T595
Test name
Test status
Simulation time 356779038 ps
CPU time 5.31 seconds
Started Jul 12 05:35:44 PM PDT 24
Finished Jul 12 05:35:53 PM PDT 24
Peak memory 217608 kb
Host smart-6f70f80c-13d5-453d-8d30-cda446b8db27
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456604951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2456604951
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3510338835
Short name T292
Test name
Test status
Simulation time 2162760956 ps
CPU time 34.75 seconds
Started Jul 12 05:35:53 PM PDT 24
Finished Jul 12 05:36:30 PM PDT 24
Peak memory 250952 kb
Host smart-5f08853e-0418-42ca-a19c-cf5220840cc6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510338835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.3510338835
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1642755308
Short name T332
Test name
Test status
Simulation time 1711614507 ps
CPU time 17.45 seconds
Started Jul 12 05:35:49 PM PDT 24
Finished Jul 12 05:36:09 PM PDT 24
Peak memory 250908 kb
Host smart-138ba961-1d10-4829-a581-0b4294654296
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642755308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.1642755308
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.1789161305
Short name T733
Test name
Test status
Simulation time 528208101 ps
CPU time 3.49 seconds
Started Jul 12 05:35:42 PM PDT 24
Finished Jul 12 05:35:48 PM PDT 24
Peak memory 218116 kb
Host smart-942ae294-2a8a-4190-a9f9-5d88f4f76975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789161305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1789161305
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3543474553
Short name T420
Test name
Test status
Simulation time 2296944352 ps
CPU time 10.36 seconds
Started Jul 12 05:35:52 PM PDT 24
Finished Jul 12 05:36:05 PM PDT 24
Peak memory 217584 kb
Host smart-b9d62694-22d5-4807-a656-d2a335958007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543474553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3543474553
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.1699988448
Short name T325
Test name
Test status
Simulation time 1291148422 ps
CPU time 12.73 seconds
Started Jul 12 05:35:44 PM PDT 24
Finished Jul 12 05:36:01 PM PDT 24
Peak memory 225968 kb
Host smart-1c79ef51-7f1b-4580-9ce8-e6adb74bcd00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699988448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.1699988448
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2267090887
Short name T654
Test name
Test status
Simulation time 198200812 ps
CPU time 7.91 seconds
Started Jul 12 05:35:46 PM PDT 24
Finished Jul 12 05:35:58 PM PDT 24
Peak memory 225980 kb
Host smart-1cb26992-b153-40bb-b186-5caec3acffef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267090887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2267090887
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.4069570465
Short name T714
Test name
Test status
Simulation time 681437606 ps
CPU time 9.8 seconds
Started Jul 12 05:35:46 PM PDT 24
Finished Jul 12 05:36:00 PM PDT 24
Peak memory 225916 kb
Host smart-c3a9d078-45ac-4201-a90f-90f3a84a8aab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069570465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.4
069570465
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.1916973017
Short name T485
Test name
Test status
Simulation time 1023453191 ps
CPU time 6.95 seconds
Started Jul 12 05:35:43 PM PDT 24
Finished Jul 12 05:35:54 PM PDT 24
Peak memory 224432 kb
Host smart-67e7965b-7390-49b8-813d-b4e05ef9d8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916973017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.1916973017
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.818696745
Short name T68
Test name
Test status
Simulation time 256528656 ps
CPU time 3.15 seconds
Started Jul 12 05:35:45 PM PDT 24
Finished Jul 12 05:35:52 PM PDT 24
Peak memory 217596 kb
Host smart-38f47c82-f866-4cf8-be84-5ca8700a1968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818696745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.818696745
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.2497064970
Short name T227
Test name
Test status
Simulation time 1561757346 ps
CPU time 34.34 seconds
Started Jul 12 05:35:43 PM PDT 24
Finished Jul 12 05:36:20 PM PDT 24
Peak memory 250888 kb
Host smart-d0ac13c9-eb27-461c-8d09-923ebd8b5f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497064970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2497064970
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.1268543341
Short name T384
Test name
Test status
Simulation time 97502262 ps
CPU time 7.85 seconds
Started Jul 12 05:35:46 PM PDT 24
Finished Jul 12 05:35:58 PM PDT 24
Peak memory 251064 kb
Host smart-616b9bc2-9525-46d0-a9eb-a71bd203c5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268543341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.1268543341
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.221421491
Short name T827
Test name
Test status
Simulation time 4590236200 ps
CPU time 91.97 seconds
Started Jul 12 05:35:47 PM PDT 24
Finished Jul 12 05:37:23 PM PDT 24
Peak memory 283548 kb
Host smart-6b18a648-0864-40ed-96fa-4edced4018ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221421491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.221421491
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.619986745
Short name T619
Test name
Test status
Simulation time 14238828 ps
CPU time 0.97 seconds
Started Jul 12 05:35:45 PM PDT 24
Finished Jul 12 05:35:51 PM PDT 24
Peak memory 211656 kb
Host smart-85f77e84-1a01-46ae-b6ea-a195c08e67c1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619986745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr
l_volatile_unlock_smoke.619986745
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3132106103
Short name T510
Test name
Test status
Simulation time 99126648 ps
CPU time 1.06 seconds
Started Jul 12 05:35:49 PM PDT 24
Finished Jul 12 05:35:53 PM PDT 24
Peak memory 208872 kb
Host smart-b8a01757-8c45-452e-a434-aa48ab2ff1e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132106103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3132106103
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2177203327
Short name T217
Test name
Test status
Simulation time 19003808 ps
CPU time 0.95 seconds
Started Jul 12 05:35:43 PM PDT 24
Finished Jul 12 05:35:48 PM PDT 24
Peak memory 208888 kb
Host smart-2fcfd404-eeb8-43ae-9699-ba37f10cb2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177203327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2177203327
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1715300513
Short name T837
Test name
Test status
Simulation time 280003910 ps
CPU time 11.33 seconds
Started Jul 12 05:35:52 PM PDT 24
Finished Jul 12 05:36:06 PM PDT 24
Peak memory 217964 kb
Host smart-a3347348-ebf7-46ce-a24c-9434759a6d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715300513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1715300513
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.916595018
Short name T213
Test name
Test status
Simulation time 106665764 ps
CPU time 1.92 seconds
Started Jul 12 05:35:48 PM PDT 24
Finished Jul 12 05:35:54 PM PDT 24
Peak memory 216968 kb
Host smart-24702316-c91c-4d88-ae5d-1873ba1b960d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916595018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.916595018
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.2023849152
Short name T717
Test name
Test status
Simulation time 5391513025 ps
CPU time 29.98 seconds
Started Jul 12 05:35:47 PM PDT 24
Finished Jul 12 05:36:21 PM PDT 24
Peak memory 218096 kb
Host smart-fab8abcd-8f4e-4f4a-86d9-de135330c6a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023849152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.2023849152
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.3993129177
Short name T787
Test name
Test status
Simulation time 954110423 ps
CPU time 23.36 seconds
Started Jul 12 05:35:46 PM PDT 24
Finished Jul 12 05:36:14 PM PDT 24
Peak memory 217592 kb
Host smart-2fcf79c5-2a96-4302-9744-dd487ea41255
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993129177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.3
993129177
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1070360160
Short name T367
Test name
Test status
Simulation time 1565478823 ps
CPU time 5.1 seconds
Started Jul 12 05:35:45 PM PDT 24
Finished Jul 12 05:35:54 PM PDT 24
Peak memory 218052 kb
Host smart-d8c9e07b-3149-49d1-86d6-ccd2b9cc4745
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070360160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.1070360160
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.423772187
Short name T484
Test name
Test status
Simulation time 2364785854 ps
CPU time 22.39 seconds
Started Jul 12 05:35:54 PM PDT 24
Finished Jul 12 05:36:18 PM PDT 24
Peak memory 217564 kb
Host smart-a0429d82-3ad7-4c13-8a87-f0e182468498
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423772187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_regwen_during_op.423772187
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.1385492708
Short name T167
Test name
Test status
Simulation time 361144232 ps
CPU time 6.06 seconds
Started Jul 12 05:35:48 PM PDT 24
Finished Jul 12 05:35:58 PM PDT 24
Peak memory 217640 kb
Host smart-a4921237-c958-4998-b8e2-f44d4f67c039
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385492708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
1385492708
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1449455456
Short name T628
Test name
Test status
Simulation time 4355846822 ps
CPU time 54.29 seconds
Started Jul 12 05:35:46 PM PDT 24
Finished Jul 12 05:36:44 PM PDT 24
Peak memory 278684 kb
Host smart-dbc74fda-cd12-4cc7-aeab-3d6e3bcf214a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449455456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.1449455456
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1441561865
Short name T472
Test name
Test status
Simulation time 4095810167 ps
CPU time 36.24 seconds
Started Jul 12 05:35:54 PM PDT 24
Finished Jul 12 05:36:32 PM PDT 24
Peak memory 250788 kb
Host smart-74124f55-9705-4b88-85a8-6fdb824e94f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441561865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1441561865
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.2264549622
Short name T505
Test name
Test status
Simulation time 55185733 ps
CPU time 2.26 seconds
Started Jul 12 05:35:51 PM PDT 24
Finished Jul 12 05:35:55 PM PDT 24
Peak memory 222096 kb
Host smart-5a6f4984-5463-401d-b43e-072f573dada7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264549622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2264549622
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.416617423
Short name T574
Test name
Test status
Simulation time 2358811121 ps
CPU time 17.78 seconds
Started Jul 12 05:35:46 PM PDT 24
Finished Jul 12 05:36:08 PM PDT 24
Peak memory 214868 kb
Host smart-1f51220e-ab45-49fd-8e03-d8116ce2eede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416617423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.416617423
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1655025844
Short name T857
Test name
Test status
Simulation time 299979132 ps
CPU time 10.72 seconds
Started Jul 12 05:35:43 PM PDT 24
Finished Jul 12 05:35:58 PM PDT 24
Peak memory 225968 kb
Host smart-e591bc17-fdce-4f91-9355-c77417538d7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655025844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1655025844
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.3088881672
Short name T230
Test name
Test status
Simulation time 350597014 ps
CPU time 15.75 seconds
Started Jul 12 05:35:59 PM PDT 24
Finished Jul 12 05:36:16 PM PDT 24
Peak memory 225844 kb
Host smart-11d5d910-354a-41a2-8097-7034bb2f1401
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088881672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.3088881672
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1884133531
Short name T153
Test name
Test status
Simulation time 2103613888 ps
CPU time 10.01 seconds
Started Jul 12 05:35:51 PM PDT 24
Finished Jul 12 05:36:03 PM PDT 24
Peak memory 218148 kb
Host smart-4a96469a-ef4a-4a83-88a7-ea05b139efb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884133531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.1
884133531
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.3063017747
Short name T656
Test name
Test status
Simulation time 1494088602 ps
CPU time 13.36 seconds
Started Jul 12 05:35:46 PM PDT 24
Finished Jul 12 05:36:04 PM PDT 24
Peak memory 225904 kb
Host smart-c25b0b15-3324-4497-a004-d87e4e54d964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063017747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.3063017747
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1144970355
Short name T462
Test name
Test status
Simulation time 240024679 ps
CPU time 2.7 seconds
Started Jul 12 05:35:46 PM PDT 24
Finished Jul 12 05:35:53 PM PDT 24
Peak memory 214304 kb
Host smart-d3024f4b-15e6-425c-83a6-21639823881b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144970355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1144970355
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.1031118654
Short name T154
Test name
Test status
Simulation time 416245745 ps
CPU time 24.82 seconds
Started Jul 12 05:35:48 PM PDT 24
Finished Jul 12 05:36:16 PM PDT 24
Peak memory 250832 kb
Host smart-281192f4-a7ed-4aca-9890-df3fc86888d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031118654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1031118654
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.3159040490
Short name T676
Test name
Test status
Simulation time 180549879 ps
CPU time 3.43 seconds
Started Jul 12 05:35:45 PM PDT 24
Finished Jul 12 05:35:53 PM PDT 24
Peak memory 226364 kb
Host smart-881dbd36-133c-4d8d-89af-62e68ed55290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159040490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3159040490
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3006207458
Short name T695
Test name
Test status
Simulation time 31145909765 ps
CPU time 237.39 seconds
Started Jul 12 05:35:54 PM PDT 24
Finished Jul 12 05:39:53 PM PDT 24
Peak memory 227928 kb
Host smart-e8187c2d-5147-444f-ab5f-12847518860f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006207458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3006207458
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3616362109
Short name T265
Test name
Test status
Simulation time 17968284 ps
CPU time 0.94 seconds
Started Jul 12 05:35:45 PM PDT 24
Finished Jul 12 05:35:50 PM PDT 24
Peak memory 217576 kb
Host smart-70e12a9e-289e-4d13-abf7-1b36b954f4ac
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616362109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.3616362109
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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