Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50528 |
1 |
|
|
T1 |
468 |
|
T2 |
14 |
|
T3 |
67 |
auto[1] |
1792 |
1 |
|
|
T1 |
16 |
|
T4 |
20 |
|
T14 |
21 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51775 |
1 |
|
|
T1 |
484 |
|
T2 |
14 |
|
T3 |
67 |
auto[1] |
545 |
1 |
|
|
T56 |
8 |
|
T42 |
19 |
|
T57 |
15 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50417 |
1 |
|
|
T1 |
465 |
|
T2 |
14 |
|
T3 |
67 |
auto[1] |
1903 |
1 |
|
|
T1 |
19 |
|
T4 |
48 |
|
T14 |
40 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50429 |
1 |
|
|
T1 |
461 |
|
T2 |
14 |
|
T3 |
67 |
auto[1] |
1891 |
1 |
|
|
T1 |
23 |
|
T4 |
39 |
|
T14 |
42 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50361 |
1 |
|
|
T1 |
457 |
|
T2 |
14 |
|
T3 |
67 |
auto[1] |
1959 |
1 |
|
|
T1 |
27 |
|
T4 |
41 |
|
T14 |
32 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
47741 |
1 |
|
|
T1 |
395 |
|
T2 |
14 |
|
T3 |
67 |
no_err_inj |
4579 |
1 |
|
|
T1 |
89 |
|
T11 |
16 |
|
T4 |
104 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50562 |
1 |
|
|
T1 |
462 |
|
T2 |
14 |
|
T3 |
67 |
auto[1] |
1758 |
1 |
|
|
T1 |
22 |
|
T4 |
16 |
|
T14 |
13 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51843 |
1 |
|
|
T1 |
484 |
|
T2 |
14 |
|
T3 |
67 |
auto[1] |
477 |
1 |
|
|
T56 |
9 |
|
T42 |
11 |
|
T57 |
11 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
36199 |
1 |
|
|
T1 |
207 |
|
T3 |
67 |
|
T9 |
96 |
auto[1] |
16121 |
1 |
|
|
T1 |
277 |
|
T2 |
14 |
|
T4 |
247 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50412 |
1 |
|
|
T1 |
457 |
|
T2 |
14 |
|
T3 |
67 |
auto[1] |
1908 |
1 |
|
|
T1 |
27 |
|
T4 |
40 |
|
T14 |
34 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50434 |
1 |
|
|
T1 |
463 |
|
T2 |
14 |
|
T3 |
67 |
auto[1] |
1886 |
1 |
|
|
T1 |
21 |
|
T4 |
45 |
|
T14 |
40 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50404 |
1 |
|
|
T1 |
456 |
|
T2 |
14 |
|
T3 |
67 |
auto[1] |
1916 |
1 |
|
|
T1 |
28 |
|
T4 |
47 |
|
T14 |
28 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50531 |
1 |
|
|
T1 |
474 |
|
T2 |
14 |
|
T3 |
67 |
auto[1] |
1789 |
1 |
|
|
T1 |
10 |
|
T4 |
21 |
|
T14 |
13 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50157 |
1 |
|
|
T1 |
451 |
|
T3 |
67 |
|
T9 |
96 |
auto[1] |
2163 |
1 |
|
|
T1 |
33 |
|
T2 |
14 |
|
T4 |
29 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51768 |
1 |
|
|
T1 |
484 |
|
T2 |
14 |
|
T3 |
67 |
auto[1] |
552 |
1 |
|
|
T56 |
11 |
|
T42 |
21 |
|
T57 |
20 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51789 |
1 |
|
|
T1 |
484 |
|
T2 |
14 |
|
T3 |
67 |
auto[1] |
531 |
1 |
|
|
T56 |
8 |
|
T42 |
18 |
|
T57 |
14 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51815 |
1 |
|
|
T1 |
484 |
|
T2 |
14 |
|
T3 |
67 |
auto[1] |
505 |
1 |
|
|
T56 |
14 |
|
T42 |
9 |
|
T57 |
7 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49638 |
1 |
|
|
T1 |
421 |
|
T2 |
14 |
|
T3 |
67 |
auto[1] |
2682 |
1 |
|
|
T1 |
63 |
|
T4 |
66 |
|
T14 |
15 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48412 |
1 |
|
|
T1 |
484 |
|
T2 |
14 |
|
T9 |
96 |
auto[1] |
3908 |
1 |
|
|
T3 |
67 |
|
T10 |
96 |
|
T12 |
89 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50449 |
1 |
|
|
T1 |
457 |
|
T2 |
14 |
|
T3 |
67 |
auto[1] |
1871 |
1 |
|
|
T1 |
27 |
|
T4 |
52 |
|
T14 |
39 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50436 |
1 |
|
|
T1 |
453 |
|
T2 |
14 |
|
T3 |
67 |
auto[1] |
1884 |
1 |
|
|
T1 |
31 |
|
T4 |
46 |
|
T14 |
42 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50444 |
1 |
|
|
T1 |
464 |
|
T2 |
14 |
|
T3 |
67 |
auto[1] |
1876 |
1 |
|
|
T1 |
20 |
|
T4 |
48 |
|
T14 |
45 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50554 |
1 |
|
|
T1 |
469 |
|
T2 |
14 |
|
T3 |
67 |
auto[1] |
1766 |
1 |
|
|
T1 |
15 |
|
T4 |
16 |
|
T14 |
22 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46908 |
1 |
|
|
T1 |
465 |
|
T2 |
14 |
|
T3 |
67 |
auto[1] |
5412 |
1 |
|
|
T1 |
19 |
|
T4 |
23 |
|
T14 |
16 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48328 |
1 |
|
|
T1 |
484 |
|
T2 |
14 |
|
T3 |
67 |
auto[1] |
3992 |
1 |
|
|
T9 |
96 |
|
T16 |
96 |
|
T47 |
80 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52320 |
1 |
|
|
T1 |
484 |
|
T2 |
14 |
|
T3 |
67 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50520 |
1 |
|
|
T1 |
463 |
|
T2 |
14 |
|
T3 |
67 |
auto[1] |
1800 |
1 |
|
|
T1 |
21 |
|
T4 |
17 |
|
T14 |
26 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50487 |
1 |
|
|
T1 |
468 |
|
T2 |
14 |
|
T3 |
67 |
auto[1] |
1833 |
1 |
|
|
T1 |
16 |
|
T4 |
25 |
|
T14 |
22 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50496 |
1 |
|
|
T1 |
464 |
|
T2 |
14 |
|
T3 |
67 |
auto[1] |
1824 |
1 |
|
|
T1 |
20 |
|
T4 |
16 |
|
T14 |
21 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
46381 |
1 |
|
|
T1 |
366 |
|
T2 |
14 |
|
T3 |
67 |
auto[0] |
no_err_inj |
3257 |
1 |
|
|
T1 |
55 |
|
T11 |
16 |
|
T4 |
67 |
auto[1] |
err_inj |
1360 |
1 |
|
|
T1 |
29 |
|
T4 |
29 |
|
T14 |
8 |
auto[1] |
no_err_inj |
1322 |
1 |
|
|
T1 |
34 |
|
T4 |
37 |
|
T14 |
7 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47908 |
1 |
|
|
T1 |
395 |
|
T2 |
14 |
|
T3 |
67 |
auto[0] |
auto[1] |
1730 |
1 |
|
|
T1 |
26 |
|
T4 |
44 |
|
T14 |
41 |
auto[1] |
auto[0] |
2528 |
1 |
|
|
T1 |
58 |
|
T4 |
64 |
|
T14 |
14 |
auto[1] |
auto[1] |
154 |
1 |
|
|
T1 |
5 |
|
T4 |
2 |
|
T14 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47920 |
1 |
|
|
T1 |
405 |
|
T2 |
14 |
|
T3 |
67 |
auto[0] |
auto[1] |
1718 |
1 |
|
|
T1 |
16 |
|
T4 |
43 |
|
T14 |
38 |
auto[1] |
auto[0] |
2514 |
1 |
|
|
T1 |
58 |
|
T4 |
64 |
|
T14 |
13 |
auto[1] |
auto[1] |
168 |
1 |
|
|
T1 |
5 |
|
T4 |
2 |
|
T14 |
2 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47914 |
1 |
|
|
T1 |
406 |
|
T2 |
14 |
|
T3 |
67 |
auto[0] |
auto[1] |
1724 |
1 |
|
|
T1 |
15 |
|
T4 |
45 |
|
T14 |
43 |
auto[1] |
auto[0] |
2530 |
1 |
|
|
T1 |
58 |
|
T4 |
63 |
|
T14 |
13 |
auto[1] |
auto[1] |
152 |
1 |
|
|
T1 |
5 |
|
T4 |
3 |
|
T14 |
2 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47894 |
1 |
|
|
T1 |
403 |
|
T2 |
14 |
|
T3 |
67 |
auto[0] |
auto[1] |
1744 |
1 |
|
|
T1 |
18 |
|
T4 |
36 |
|
T14 |
42 |
auto[1] |
auto[0] |
2535 |
1 |
|
|
T1 |
58 |
|
T4 |
63 |
|
T14 |
15 |
auto[1] |
auto[1] |
147 |
1 |
|
|
T1 |
5 |
|
T4 |
3 |
|
T19 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47815 |
1 |
|
|
T1 |
398 |
|
T2 |
14 |
|
T3 |
67 |
auto[0] |
auto[1] |
1823 |
1 |
|
|
T1 |
23 |
|
T4 |
39 |
|
T14 |
32 |
auto[1] |
auto[0] |
2546 |
1 |
|
|
T1 |
59 |
|
T4 |
64 |
|
T14 |
15 |
auto[1] |
auto[1] |
136 |
1 |
|
|
T1 |
4 |
|
T4 |
2 |
|
T22 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47857 |
1 |
|
|
T1 |
403 |
|
T2 |
14 |
|
T3 |
67 |
auto[0] |
auto[1] |
1781 |
1 |
|
|
T1 |
18 |
|
T4 |
45 |
|
T14 |
39 |
auto[1] |
auto[0] |
2560 |
1 |
|
|
T1 |
62 |
|
T4 |
63 |
|
T14 |
14 |
auto[1] |
auto[1] |
122 |
1 |
|
|
T1 |
1 |
|
T4 |
3 |
|
T14 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35201 |
1 |
|
|
T1 |
207 |
|
T3 |
67 |
|
T9 |
96 |
auto[0] |
auto[1] |
998 |
1 |
|
|
T4 |
9 |
|
T14 |
10 |
|
T17 |
11 |
auto[1] |
auto[0] |
15327 |
1 |
|
|
T1 |
261 |
|
T2 |
14 |
|
T4 |
236 |
auto[1] |
auto[1] |
794 |
1 |
|
|
T1 |
16 |
|
T4 |
11 |
|
T14 |
11 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35220 |
1 |
|
|
T1 |
207 |
|
T3 |
67 |
|
T9 |
96 |
auto[0] |
auto[1] |
979 |
1 |
|
|
T4 |
5 |
|
T14 |
7 |
|
T17 |
11 |
auto[1] |
auto[0] |
15342 |
1 |
|
|
T1 |
255 |
|
T2 |
14 |
|
T4 |
236 |
auto[1] |
auto[1] |
779 |
1 |
|
|
T1 |
22 |
|
T4 |
11 |
|
T14 |
6 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34923 |
1 |
|
|
T1 |
174 |
|
T3 |
67 |
|
T9 |
96 |
auto[0] |
auto[1] |
1276 |
1 |
|
|
T1 |
33 |
|
T4 |
29 |
|
T238 |
5 |
auto[1] |
auto[0] |
15234 |
1 |
|
|
T1 |
277 |
|
T4 |
247 |
|
T14 |
203 |
auto[1] |
auto[1] |
887 |
1 |
|
|
T2 |
14 |
|
T20 |
2 |
|
T60 |
14 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35205 |
1 |
|
|
T1 |
207 |
|
T3 |
67 |
|
T9 |
96 |
auto[0] |
auto[1] |
994 |
1 |
|
|
T4 |
14 |
|
T14 |
5 |
|
T17 |
10 |
auto[1] |
auto[0] |
15326 |
1 |
|
|
T1 |
267 |
|
T2 |
14 |
|
T4 |
240 |
auto[1] |
auto[1] |
795 |
1 |
|
|
T1 |
10 |
|
T4 |
7 |
|
T14 |
8 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
31563 |
1 |
|
|
T1 |
207 |
|
T3 |
67 |
|
T9 |
96 |
auto[0] |
auto[1] |
4636 |
1 |
|
|
T4 |
14 |
|
T14 |
8 |
|
T17 |
14 |
auto[1] |
auto[0] |
15345 |
1 |
|
|
T1 |
258 |
|
T2 |
14 |
|
T4 |
238 |
auto[1] |
auto[1] |
776 |
1 |
|
|
T1 |
19 |
|
T4 |
9 |
|
T14 |
8 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35086 |
1 |
|
|
T1 |
188 |
|
T3 |
67 |
|
T9 |
96 |
auto[0] |
auto[1] |
1113 |
1 |
|
|
T1 |
19 |
|
T4 |
29 |
|
T14 |
32 |
auto[1] |
auto[0] |
15350 |
1 |
|
|
T1 |
265 |
|
T2 |
14 |
|
T4 |
230 |
auto[1] |
auto[1] |
771 |
1 |
|
|
T1 |
12 |
|
T4 |
17 |
|
T14 |
10 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35089 |
1 |
|
|
T1 |
193 |
|
T3 |
67 |
|
T9 |
96 |
auto[0] |
auto[1] |
1110 |
1 |
|
|
T1 |
14 |
|
T4 |
38 |
|
T14 |
26 |
auto[1] |
auto[0] |
15360 |
1 |
|
|
T1 |
264 |
|
T2 |
14 |
|
T4 |
233 |
auto[1] |
auto[1] |
761 |
1 |
|
|
T1 |
13 |
|
T4 |
14 |
|
T14 |
13 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35073 |
1 |
|
|
T1 |
193 |
|
T3 |
67 |
|
T9 |
96 |
auto[0] |
auto[1] |
1126 |
1 |
|
|
T1 |
14 |
|
T4 |
36 |
|
T14 |
29 |
auto[1] |
auto[0] |
15361 |
1 |
|
|
T1 |
270 |
|
T2 |
14 |
|
T4 |
238 |
auto[1] |
auto[1] |
760 |
1 |
|
|
T1 |
7 |
|
T4 |
9 |
|
T14 |
11 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35086 |
1 |
|
|
T1 |
188 |
|
T3 |
67 |
|
T9 |
96 |
auto[0] |
auto[1] |
1113 |
1 |
|
|
T1 |
19 |
|
T4 |
26 |
|
T14 |
21 |
auto[1] |
auto[0] |
15326 |
1 |
|
|
T1 |
269 |
|
T2 |
14 |
|
T4 |
233 |
auto[1] |
auto[1] |
795 |
1 |
|
|
T1 |
8 |
|
T4 |
14 |
|
T14 |
13 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35075 |
1 |
|
|
T1 |
195 |
|
T3 |
67 |
|
T9 |
96 |
auto[0] |
auto[1] |
1124 |
1 |
|
|
T1 |
12 |
|
T4 |
29 |
|
T14 |
28 |
auto[1] |
auto[0] |
15354 |
1 |
|
|
T1 |
266 |
|
T2 |
14 |
|
T4 |
237 |
auto[1] |
auto[1] |
767 |
1 |
|
|
T1 |
11 |
|
T4 |
10 |
|
T14 |
14 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35051 |
1 |
|
|
T1 |
193 |
|
T3 |
67 |
|
T9 |
96 |
auto[0] |
auto[1] |
1148 |
1 |
|
|
T1 |
14 |
|
T4 |
29 |
|
T14 |
29 |
auto[1] |
auto[0] |
15366 |
1 |
|
|
T1 |
272 |
|
T2 |
14 |
|
T4 |
228 |
auto[1] |
auto[1] |
755 |
1 |
|
|
T1 |
5 |
|
T4 |
19 |
|
T14 |
11 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35226 |
1 |
|
|
T1 |
207 |
|
T3 |
67 |
|
T9 |
96 |
auto[0] |
auto[1] |
973 |
1 |
|
|
T4 |
8 |
|
T14 |
8 |
|
T17 |
9 |
auto[1] |
auto[0] |
15270 |
1 |
|
|
T1 |
257 |
|
T2 |
14 |
|
T4 |
239 |
auto[1] |
auto[1] |
851 |
1 |
|
|
T1 |
20 |
|
T4 |
8 |
|
T14 |
13 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35179 |
1 |
|
|
T1 |
207 |
|
T3 |
67 |
|
T9 |
96 |
auto[0] |
auto[1] |
1020 |
1 |
|
|
T4 |
9 |
|
T14 |
13 |
|
T17 |
8 |
auto[1] |
auto[0] |
15308 |
1 |
|
|
T1 |
261 |
|
T2 |
14 |
|
T4 |
231 |
auto[1] |
auto[1] |
813 |
1 |
|
|
T1 |
16 |
|
T4 |
16 |
|
T14 |
9 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34484 |
1 |
|
|
T1 |
207 |
|
T3 |
67 |
|
T9 |
96 |
auto[0] |
auto[1] |
1715 |
1 |
|
|
T4 |
44 |
|
T14 |
15 |
|
T84 |
14 |
auto[1] |
auto[0] |
15154 |
1 |
|
|
T1 |
214 |
|
T2 |
14 |
|
T4 |
225 |
auto[1] |
auto[1] |
967 |
1 |
|
|
T1 |
63 |
|
T4 |
22 |
|
T19 |
15 |