ASSERT | PROPERTIES | SEQUENCES | |
Total | 392 | 0 | 10 |
Category 0 | 392 | 0 | 10 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 392 | 0 | 10 |
Severity 0 | 392 | 0 | 10 |
NUMBER | PERCENT | |
Total Number | 392 | 100.00 |
Uncovered | 4 | 1.02 |
Success | 388 | 98.98 |
Failure | 0 | 0.00 |
Incomplete | 7 | 1.79 |
Without Attempts | 0 | 0.00 |
NUMBER | PERCENT | |
Total Number | 10 | 100.00 |
Uncovered | 0 | 0.00 |
All Matches | 10 | 100.00 |
First Matches | 10 | 100.00 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.FpvSecCmCtrlKmacIfFsmCheck_A | 0 | 0 | 93430935 | 0 | 0 | 0 | |
tb.dut.FpvSecCmCtrlLcFsmCheck_A | 0 | 0 | 93437968 | 0 | 0 | 0 | |
tb.dut.FpvSecCmTapRegWeOnehotCheck_A | 0 | 0 | 96074805 | 0 | 0 | 0 | |
tb.dut.u_lc_ctrl_fsm.SecCmCFILinear_A | 0 | 0 | 96074805 | 0 | 0 | 2152 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.u_lc_ctrl_fsm.ClkBypStaysOnOnceAsserted_A | 0 | 0 | 96074805 | 4683163 | 0 | 55 | |
tb.dut.u_lc_ctrl_fsm.EscStaysOnOnceAsserted_A | 0 | 0 | 96074805 | 18029627 | 0 | 9 | |
tb.dut.u_lc_ctrl_fsm.FlashRmaStaysOnOnceAsserted_A | 0 | 0 | 96074805 | 561646 | 0 | 8 | |
tb.dut.u_lc_ctrl_fsm.SecCmCFILinear_A | 0 | 0 | 96074805 | 0 | 0 | 2152 | |
tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack.gen_flops.OutputDelay_A | 0 | 0 | 95840854 | 91667409 | 0 | 2394 | |
tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack.gen_flops.OutputDelay_A | 0 | 0 | 95840854 | 91667409 | 0 | 2394 | |
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_flops.OutputDelay_A | 0 | 0 | 95868104 | 91700711 | 0 | 2397 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 98108714 | 917 | 917 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 98108714 | 97 | 97 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 98108714 | 97 | 97 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 98108714 | 56 | 56 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 98108714 | 28 | 28 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 98108714 | 41 | 41 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 98108714 | 54 | 54 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 98108714 | 2121 | 2121 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 98108714 | 8215 | 8215 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 98108714 | 724964 | 724964 | 301 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 98108714 | 917 | 917 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 98108714 | 97 | 97 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 98108714 | 97 | 97 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 98108714 | 56 | 56 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 98108714 | 28 | 28 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C | 0 | 0 | 98108714 | 41 | 41 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C | 0 | 0 | 98108714 | 54 | 54 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C | 0 | 0 | 98108714 | 2121 | 2121 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C | 0 | 0 | 98108714 | 8215 | 8215 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C | 0 | 0 | 98108714 | 724964 | 724964 | 301 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |