Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

96713127

1

T1

152046

T2

64627

T3

15478

auto[1]

1395275

1

T1

11057

T2

490

T3

9219

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

96727874

1

T1

152046

T2

64235

T3

15541

auto[1]

1380528

1

T1

11054

T2

882

T3

9156

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7086225	1			T1	74841		T2	1769		T3	6060
auto[IdleSt]	20391147	1			T1	484086		T2	36731		T3	5184
auto[ClkMuxSt]	34215	1			T1	259		T2	14		T3	59
auto[CntIncrSt]	34035	1			T1	259		T2	14		T3	57
auto[CntProgSt]	1463207	1			T1	58835		T2	646		T3	104
auto[TransCheckSt]	26621	1			T1	194		T3	43		T9	96
auto[TokenHashSt]	38175412	1			T1	158115		T3	312		T9	994
auto[FlashRmaSt]	33873	1			T1	317		T3	41		T9	182
auto[TokenCheck0St]	11998	1			T1	118		T3	25		T9	37
auto[TokenCheck1St]	8984	1			T1	99		T3	25		T9	16
auto[TransProgSt]	378320	1			T1	23301		T3	42		T10	46
auto[PostTransSt]	12221213	1			T1	391641		T2	14951		T3	13
auto[ScrapSt]	240976	1			T1	830		T10	9		T11	12
auto[EscalateSt]	6542663	1			T1	121590		T2	10992		T3	12732
auto[InvalidSt]	11457565	1			T1	217011		T4	170075		T14	216605

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1948	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11457565	1			T1	217011		T4	170075		T14	216605
EscalateSt	6542663	1			T1	121590		T2	10992		T3	12732
ScrapSt	240976	1			T1	830		T10	9		T11	12
PostTransSt	12221213	1			T1	391641		T2	14951		T3	13
TransProgSt	378320	1			T1	23301		T3	42		T10	46
TokenCheck1St	8984	1			T1	99		T3	25		T9	16
TokenCheck0St	11998	1			T1	118		T3	25		T9	37
FlashRmaSt	33873	1			T1	317		T3	41		T9	182
TokenHashSt	38175412	1			T1	158115		T3	312		T9	994
TransCheckSt	26621	1			T1	194		T3	43		T9	96
CntProgSt	1463207	1			T1	58835		T2	646		T3	104
CntIncrSt	34035	1			T1	259		T2	14		T3	57
ClkMuxSt	34215	1			T1	259		T2	14		T3	59
IdleSt	20391147	1			T1	484086		T2	36731		T3	5184
ResetSt	7086225	1			T1	74841		T2	1769		T3	6060
arcs[ResetSt=>IdleSt]	52428	1			T1	471		T2	15		T3	64
arcs[IdleSt=>ScrapSt]	263	1			T1	3		T10	3		T11	1
arcs[IdleSt=>ClkMuxSt]	34106	1			T1	259		T2	14		T3	59
arcs[ClkMuxSt=>CntIncrSt]	34035	1			T1	259		T2	14		T3	57
arcs[CntIncrSt=>PostTransSt]	1834	1			T1	16		T4	25		T14	22
arcs[CntIncrSt=>CntProgSt]	32115	1			T1	243		T2	14		T3	55
arcs[CntProgSt=>PostTransSt]	4459	1			T1	49		T2	14		T4	49
arcs[CntProgSt=>TransCheckSt]	26621	1			T1	194		T3	43		T9	96
arcs[TransCheckSt=>PostTransSt]	3851	1			T1	20		T9	48		T4	16
arcs[TransCheckSt=>TokenHashSt]	22630	1			T1	174		T3	39		T9	48
arcs[TokenHashSt=>PostTransSt]	9793	1			T1	56		T9	11		T4	56
arcs[TokenHashSt=>FlashRmaSt]	12080	1			T1	118		T3	25		T9	37
arcs[FlashRmaSt=>TokenCheck0St]	11998	1			T1	118		T3	25		T9	37
arcs[TokenCheck0St=>PostTransSt]	2988	1			T1	19		T9	21		T4	16
arcs[TokenCheck0St=>TokenCheck1St]	8984	1			T1	99		T3	25		T9	16
arcs[TokenCheck1St=>PostTransSt]	661	1			T1	2		T9	16		T14	2
arcs[TransProgSt=>PostTransSt]	7400	1			T1	97		T3	9		T11	15
arcs[IdleSt=>EscalateSt]	204	1			T3	4		T12	7		T48	6
arcs[ClkMuxSt=>EscalateSt]	71	1			T3	2		T10	1		T12	2
arcs[CntIncrSt=>EscalateSt]	86	1			T3	2		T10	6		T12	3
arcs[CntProgSt=>EscalateSt]	1035	1			T3	12		T10	49		T12	30
arcs[TransCheckSt=>EscalateSt]	140	1			T3	4		T10	1		T12	1
arcs[TokenHashSt=>EscalateSt]	756	1			T3	14		T10	6		T12	10
arcs[FlashRmaSt=>EscalateSt]	82	1			T10	3		T12	3		T48	2
arcs[TokenCheck0St=>EscalateSt]	26	1			T48	1		T51	1		T52	1
arcs[TokenCheck1St=>EscalateSt]	145	1			T3	2		T10	4		T12	1
arcs[TransProgSt=>EscalateSt]	778	1			T3	14		T10	19		T12	25
arcs[PostTransSt=>EscalateSt]	4749	1			T1	49		T2	14		T3	9
arcs[InvalidSt=>EscalateSt]	13846	1			T1	175		T4	311		T14	269

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7086047	1			T1	74841		T2	1769		T3	6056
auto[0]	auto[IdleSt]	20391008	1			T1	484086		T2	36731		T3	5180
auto[0]	auto[ClkMuxSt]	34168	1			T1	259		T2	14		T3	57
auto[0]	auto[CntIncrSt]	33978	1			T1	259		T2	14		T3	55
auto[0]	auto[CntProgSt]	1462517	1			T1	58835		T2	646		T3	98
auto[0]	auto[TransCheckSt]	26529	1			T1	194		T3	41		T9	96
auto[0]	auto[TokenHashSt]	38174892	1			T1	158115		T3	301		T9	994
auto[0]	auto[FlashRmaSt]	33816	1			T1	317		T3	41		T9	182
auto[0]	auto[TokenCheck0St]	11978	1			T1	118		T3	25		T9	37
auto[0]	auto[TokenCheck1St]	8887	1			T1	99		T3	24		T9	16
auto[0]	auto[TransProgSt]	377803	1			T1	23301		T3	31		T10	35
auto[0]	auto[PostTransSt]	12218773	1			T1	391610		T2	14946		T3	8
auto[0]	auto[ScrapSt]	240920	1			T1	830		T10	7		T11	12
auto[0]	auto[EscalateSt]	5159242	1			T1	110645		T2	10507		T3	3561
auto[0]	auto[InvalidSt]	11450621	1			T1	216930		T4	169920		T14	216475
auto[1]	auto[ResetSt]	178	1			T3	4		T10	2		T12	4
auto[1]	auto[IdleSt]	139	1			T3	4		T12	6		T48	4
auto[1]	auto[ClkMuxSt]	47	1			T3	2		T12	1		T235	1
auto[1]	auto[CntIncrSt]	57	1			T3	2		T10	5		T12	1
auto[1]	auto[CntProgSt]	690	1			T3	6		T10	37		T12	19
auto[1]	auto[TransCheckSt]	92	1			T3	2		T10	1		T48	3
auto[1]	auto[TokenHashSt]	520	1			T3	11		T10	6		T12	7
auto[1]	auto[FlashRmaSt]	57	1			T10	3		T12	3		T48	2
auto[1]	auto[TokenCheck0St]	20	1			T51	1		T52	1		T236	3
auto[1]	auto[TokenCheck1St]	97	1			T3	1		T10	1		T12	1
auto[1]	auto[TransProgSt]	517	1			T3	11		T10	11		T12	15
auto[1]	auto[PostTransSt]	2440	1			T1	31		T2	5		T3	5
auto[1]	auto[ScrapSt]	56	1			T10	2		T12	1		T48	3
auto[1]	auto[EscalateSt]	1383421	1			T1	10945		T2	485		T3	9171
auto[1]	auto[InvalidSt]	6944	1			T1	81		T4	155		T14	130

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7086045	1			T1	74841		T2	1769		T3	6058
auto[0]	auto[IdleSt]	20391018	1			T1	484086		T2	36731		T3	5182
auto[0]	auto[ClkMuxSt]	34165	1			T1	259		T2	14		T3	58
auto[0]	auto[CntIncrSt]	33978	1			T1	259		T2	14		T3	56
auto[0]	auto[CntProgSt]	1462517	1			T1	58835		T2	646		T3	93
auto[0]	auto[TransCheckSt]	26526	1			T1	194		T3	39		T9	96
auto[0]	auto[TokenHashSt]	38174936	1			T1	158115		T3	300		T9	994
auto[0]	auto[FlashRmaSt]	33817	1			T1	317		T3	41		T9	182
auto[0]	auto[TokenCheck0St]	11982	1			T1	118		T3	25		T9	37
auto[0]	auto[TokenCheck1St]	8881	1			T1	99		T3	23		T9	16
auto[0]	auto[TransProgSt]	377790	1			T1	23301		T3	37		T10	31
auto[0]	auto[PostTransSt]	12218812	1			T1	391623		T2	14942		T3	5
auto[0]	auto[ScrapSt]	240935	1			T1	830		T10	8		T11	12
auto[0]	auto[EscalateSt]	5173861	1			T1	110648		T2	10119		T3	3624
auto[0]	auto[InvalidSt]	11450663	1			T1	216917		T4	169919		T14	216466
auto[1]	auto[ResetSt]	180	1			T3	2		T10	3		T12	4
auto[1]	auto[IdleSt]	129	1			T3	2		T12	5		T48	3
auto[1]	auto[ClkMuxSt]	50	1			T3	1		T10	1		T12	2
auto[1]	auto[CntIncrSt]	57	1			T3	1		T10	3		T12	2
auto[1]	auto[CntProgSt]	690	1			T3	11		T10	27		T12	20
auto[1]	auto[TransCheckSt]	95	1			T3	4		T10	1		T12	1
auto[1]	auto[TokenHashSt]	476	1			T3	12		T10	4		T12	5
auto[1]	auto[FlashRmaSt]	56	1			T10	2		T12	1		T48	1
auto[1]	auto[TokenCheck0St]	16	1			T48	1		T236	1		T237	1
auto[1]	auto[TokenCheck1St]	103	1			T3	2		T10	3		T12	1
auto[1]	auto[TransProgSt]	530	1			T3	5		T10	15		T12	15
auto[1]	auto[PostTransSt]	2401	1			T1	18		T2	9		T3	8
auto[1]	auto[ScrapSt]	41	1			T10	1		T48	3		T51	1
auto[1]	auto[EscalateSt]	1368802	1			T1	10942		T2	873		T3	9108
auto[1]	auto[InvalidSt]	6902	1			T1	94		T4	156		T14	139